1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-asx0-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon asx0. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_ASX0_DEFS_H__ 53#define __CVMX_ASX0_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_ASX0_DBG_DATA_DRV CVMX_ASX0_DBG_DATA_DRV_FUNC() 57static inline uint64_t CVMX_ASX0_DBG_DATA_DRV_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 60 cvmx_warn("CVMX_ASX0_DBG_DATA_DRV not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x00011800B0000208ull); 62} 63#else 64#define CVMX_ASX0_DBG_DATA_DRV (CVMX_ADD_IO_SEG(0x00011800B0000208ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_ASX0_DBG_DATA_ENABLE CVMX_ASX0_DBG_DATA_ENABLE_FUNC() 68static inline uint64_t CVMX_ASX0_DBG_DATA_ENABLE_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 71 cvmx_warn("CVMX_ASX0_DBG_DATA_ENABLE not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x00011800B0000200ull); 73} 74#else 75#define CVMX_ASX0_DBG_DATA_ENABLE (CVMX_ADD_IO_SEG(0x00011800B0000200ull)) 76#endif 77 78/** 79 * cvmx_asx0_dbg_data_drv 80 * 81 * ASX_DBG_DATA_DRV 82 * 83 */ 84union cvmx_asx0_dbg_data_drv { 85 uint64_t u64; 86 struct cvmx_asx0_dbg_data_drv_s { 87#ifdef __BIG_ENDIAN_BITFIELD 88 uint64_t reserved_9_63 : 55; 89 uint64_t pctl : 5; /**< These bits control the driving strength of the dbg 90 interface. */ 91 uint64_t nctl : 4; /**< These bits control the driving strength of the dbg 92 interface. */ 93#else 94 uint64_t nctl : 4; 95 uint64_t pctl : 5; 96 uint64_t reserved_9_63 : 55; 97#endif 98 } s; 99 struct cvmx_asx0_dbg_data_drv_cn38xx { 100#ifdef __BIG_ENDIAN_BITFIELD 101 uint64_t reserved_8_63 : 56; 102 uint64_t pctl : 4; /**< These bits control the driving strength of the dbg 103 interface. */ 104 uint64_t nctl : 4; /**< These bits control the driving strength of the dbg 105 interface. */ 106#else 107 uint64_t nctl : 4; 108 uint64_t pctl : 4; 109 uint64_t reserved_8_63 : 56; 110#endif 111 } cn38xx; 112 struct cvmx_asx0_dbg_data_drv_cn38xx cn38xxp2; 113 struct cvmx_asx0_dbg_data_drv_s cn58xx; 114 struct cvmx_asx0_dbg_data_drv_s cn58xxp1; 115}; 116typedef union cvmx_asx0_dbg_data_drv cvmx_asx0_dbg_data_drv_t; 117 118/** 119 * cvmx_asx0_dbg_data_enable 120 * 121 * ASX_DBG_DATA_ENABLE 122 * 123 */ 124union cvmx_asx0_dbg_data_enable { 125 uint64_t u64; 126 struct cvmx_asx0_dbg_data_enable_s { 127#ifdef __BIG_ENDIAN_BITFIELD 128 uint64_t reserved_1_63 : 63; 129 uint64_t en : 1; /**< A 1->0 transistion, turns the dbg interface OFF. */ 130#else 131 uint64_t en : 1; 132 uint64_t reserved_1_63 : 63; 133#endif 134 } s; 135 struct cvmx_asx0_dbg_data_enable_s cn38xx; 136 struct cvmx_asx0_dbg_data_enable_s cn38xxp2; 137 struct cvmx_asx0_dbg_data_enable_s cn58xx; 138 struct cvmx_asx0_dbg_data_enable_s cn58xxp1; 139}; 140typedef union cvmx_asx0_dbg_data_enable cvmx_asx0_dbg_data_enable_t; 141 142#endif 143