beri-netfpga.dts revision 270061 
1/*-
2 * Copyright (c) 2012-2013 Robert N. M. Watson
3 * Copyright (c) 2013 SRI International
4 * Copyright (c) 2013-2014 Bjoern A. Zeeb
5 * All rights reserved.
6 *
7 * This software was developed by SRI International and the University of
8 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
9 * ("CTSRD"), as part of the DARPA CRASH research programme.
10 *
11 * This software was developed by SRI International and the University of
12 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249)
13 * ("MRC2"), as part of the DARPA MRC research programme.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * $FreeBSD: stable/10/sys/boot/fdt/dts/mips/beri-netfpga.dts 270061 2014-08-16 14:30:46Z bz $
37 */
38
39/dts-v1/;
40
41/*
42 * Device names here have been largely made up on the spot, especially for the
43 * "compatible" strings, and might want to be revised.
44 */
45
46/ {
47	model = "SRI/Cambridge Beri (NetFPGA)";
48	compatible = "sri-cambridge,beri-netfpga";
49	#address-cells = <1>;
50	#size-cells = <1>;
51
52	cpus {
53		#address-cells = <1>;
54		#size-cells = <1>;
55
56		/*
57		 * Secondary CPUs all start disabled and use the
58		 * spin-table enable method.  cpu-release-addr must be
59		 * specified for each cpu other than cpu@0.  Values of
60		 * cpu-release-addr grow down from 0x100000 (kernel).
61		 */
62		status = "disabled";
63		enable-method = "spin-table";
64
65		cpu@0 {
66			device-type = "cpu";
67			compatible = "sri-cambridge,beri";
68
69			reg = <0 1>;
70			status = "okay";
71		};
72
73/*
74		cpu@1 {
75			device-type = "cpu";
76			compatible = "sri-cambridge,beri";
77
78			reg = <1 1>;
79			// XXX: should we need cached prefix?
80			cpu-release-addr = <0xffffffff 0x800fffe0>;
81		};
82*/
83	};
84
85	soc {
86		#address-cells = <1>;
87		#size-cells = <1>;
88		#interrupt-cells = <1>;
89
90		/*
91		 * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
92		 * we use mips4k coprocessor 0 interrupt management directly.
93		 */
94		compatible = "simple-bus", "mips,mips4k";
95		ranges = <>;
96
97		memory {
98			device_type = "memory";
99			reg = <0x0 0x0FFFFFFF>;		// ~256M at 0x0
100		};
101
102		beripic: beripic@7f804000 {
103			compatible = "sri-cambridge,beri-pic";
104			interrupt-controller;
105			#address-cells = <0>;
106			#interrupt-cells = <1>;
107			reg = <0x7f804000 0x400
108			       0x7f806000 0x10
109			       0x7f806080 0x10
110			       0x7f806100 0x10>;
111			interrupts = <0 1 2 3 4>;
112			hard-interrupt-sources = <64>;
113			soft-interrupt-sources = <64>;
114		};
115
116		serial0: serial@7f000000 {
117			compatible = "altera,jtag_uart-11_0";
118			reg = <0x7f000000 0x40>;
119			interrupts = <0>;
120			interrupt-parent = <&beripic>;
121		};
122
123/*
124		serial0: serial@7f002100 {
125			compatible = "ns16550";
126			reg = <0x7f002100 0x20>;
127			reg-shift = <2>;
128			clock-frequency = <100000000>;
129			interrupts = <8>;
130			interrupt-parent = <&beripic>;
131		};
132*/
133
134		ethernet@7f005000 {
135			compatible = "netfpag10g,nf10bmac";
136			// LOOP, TX, RX, INTR
137			reg = <0x7f005000 0x20
138			       0x7f005020 0x30
139			       0x7f005050 0x30
140			       0x7f005100 0x10>;
141			// RX
142			interrupts = <1>;
143			interrupt-parent = <&beripic>;
144		};
145	};
146
147	aliases { 
148		serial0 = &serial0;
149	};
150
151	chosen {
152		stdin = "serial0";
153		stdout = "serial0";
154		bootargs = "-v";
155	};
156};
157