1157873Simp/*- 2157873Simp * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3157873Simp * 4157873Simp * Redistribution and use in source and binary forms, with or without 5157873Simp * modification, are permitted provided that the following conditions 6157873Simp * are met: 7157873Simp * 1. Redistributions of source code must retain the above copyright 8157873Simp * notice, this list of conditions and the following disclaimer. 9157873Simp * 2. Redistributions in binary form must reproduce the above copyright 10157873Simp * notice, this list of conditions and the following disclaimer in the 11157873Simp * documentation and/or other materials provided with the distribution. 12157873Simp * 13157873Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14157873Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15157873Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16157873Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17157873Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18157873Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19157873Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20157873Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21157873Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22157873Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23157873Simp * 24157873Simp * $FreeBSD$ 25157873Simp */ 26157873Simp 27157873Simp#ifndef _AT91RM9200_LOWLEVEL_H_ 28157873Simp#define _AT91RM9200_LOWLEVEL_H_ 29157873Simp 30157873Simp/* default system config parameters */ 31157873Simp 32157873Simp#define SDRAM_BASE 0x20000000 33157873Simp 34164137Simp#ifdef BOOT_KB920X 35157873Simp/* The following divisor sets PLLA frequency: e.g. 10/5 * 90 = 180MHz */ 36157873Simp#define OSC_MAIN_FREQ_DIV 5 /* for 10MHz osc */ 37157873Simp#define SDRAM_WIDTH AT91C_SDRC_DBW_16_BITS 38157873Simptypedef unsigned short sdram_size_t; 39157873Simp#define OSC_MAIN_MULT 90 40157873Simp#endif 41157873Simp 42171426Simp#ifdef BOOT_CENTIPAD 43171426Simp/* The following divisor sets PLLA frequency: e.g. 10/5 * 90 = 180MHz */ 44171426Simp#define OSC_MAIN_FREQ_DIV 5 /* for 10MHz osc */ 45171426Simp#define SDRAM_WIDTH AT91C_SDRC_DBW_16_BITS 46171426Simptypedef unsigned short sdram_size_t; 47171426Simp#define OSC_MAIN_MULT 90 48171426Simp#endif 49171426Simp 50165398Simp#ifdef BOOT_BWCT 51165398Simp/* The following divisor sets PLLA frequency: e.g. 16/4 * 45 = 180MHz */ 52165398Simp#define OSC_MAIN_FREQ_DIV 4 /* for 16MHz osc */ 53165398Simp#define SDRAM_WIDTH AT91C_SDRC_DBW_32_BITS 54165398Simptypedef unsigned int sdram_size_t; 55165398Simp#define OSC_MAIN_MULT 45 56165398Simp#endif 57165398Simp 58157873Simp#ifdef BOOT_TSC 59157873Simp/* The following divisor sets PLLA frequency: e.g. 16/4 * 45 = 180MHz */ 60157873Simp#define OSC_MAIN_FREQ_DIV 4 /* for 16MHz osc */ 61161191Simp#define SDRAM_WIDTH AT91C_SDRC_DBW_32_BITS 62157873Simptypedef unsigned int sdram_size_t; 63157873Simp#define OSC_MAIN_MULT 45 64157873Simp#endif 65157873Simp 66157873Simp/* Master clock frequency at power-up */ 67157873Simp#define AT91C_MASTER_CLOCK 60000000 68157873Simp 69168013Simp/* #define GetSeconds() (AT91C_BASE_RTC->RTC_TIMR & AT91C_RTC_SEC) */ 70168013Simp#define GetSeconds() (AT91C_BASE_ST->ST_CRTR >> 15) 71157873Simp 72157873Simpextern void _init(void); 73157873Simp 74157873Simp#endif /* _AT91RM9200_LOWLEVEL_H_ */ 75