1/*-
2 * Copyright (c) 2006 M. Warner Losh.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * $FreeBSD$
25 */
26
27#ifndef _AT91RM9200_LOWLEVEL_H_
28#define _AT91RM9200_LOWLEVEL_H_
29
30/* default system config parameters */
31
32#define SDRAM_BASE		0x20000000
33
34#ifdef BOOT_KB920X
35/* The following divisor sets PLLA frequency: e.g. 10/5 * 90 = 180MHz */
36#define OSC_MAIN_FREQ_DIV	5	/* for 10MHz osc */
37#define SDRAM_WIDTH	AT91C_SDRC_DBW_16_BITS
38typedef unsigned short sdram_size_t;
39#define OSC_MAIN_MULT		90
40#endif
41
42#ifdef BOOT_CENTIPAD
43/* The following divisor sets PLLA frequency: e.g. 10/5 * 90 = 180MHz */
44#define OSC_MAIN_FREQ_DIV	5	/* for 10MHz osc */
45#define SDRAM_WIDTH	AT91C_SDRC_DBW_16_BITS
46typedef unsigned short sdram_size_t;
47#define OSC_MAIN_MULT		90
48#endif
49
50#ifdef BOOT_BWCT
51/* The following divisor sets PLLA frequency: e.g. 16/4 * 45 = 180MHz */
52#define OSC_MAIN_FREQ_DIV	4	/* for 16MHz osc */
53#define SDRAM_WIDTH	AT91C_SDRC_DBW_32_BITS
54typedef unsigned int sdram_size_t;
55#define OSC_MAIN_MULT		45
56#endif
57
58#ifdef BOOT_TSC
59/* The following divisor sets PLLA frequency: e.g. 16/4 * 45 = 180MHz */
60#define OSC_MAIN_FREQ_DIV	4	/* for 16MHz osc */
61#define SDRAM_WIDTH	AT91C_SDRC_DBW_32_BITS
62typedef unsigned int sdram_size_t;
63#define OSC_MAIN_MULT		45
64#endif
65
66/* Master clock frequency at power-up */
67#define AT91C_MASTER_CLOCK 60000000
68
69/* #define GetSeconds() (AT91C_BASE_RTC->RTC_TIMR & AT91C_RTC_SEC) */
70#define GetSeconds() (AT91C_BASE_ST->ST_CRTR >> 15)
71
72extern void _init(void);
73
74#endif /* _AT91RM9200_LOWLEVEL_H_ */
75