1/*- 2 * Copyright (c) 2006 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32/* 33 * Copyright (c) 2001-2005, Intel Corporation. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the Intel Corporation nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 50 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59 * SUCH DAMAGE. 60 */ 61 62#ifndef ARM_XSCALE_IF_NPEREG_H 63#define ARM_XSCALE_IF_NPEREG_H 64 65/* 66 * NPE/NPE tx/rx descriptor format. This is just the area 67 * shared with ucode running in the NPE; the driver-specific 68 * state is defined in the driver. The shared area must be 69 * cacheline-aligned. We allocate NPE_MAXSEG "descriptors" 70 * per buffer; this allows us to do minimal s/g. The number 71 * of descriptors can be expanded but doing so uses memory 72 * so should be done with care. 73 * 74 * The driver sets up buffers in uncached memory. 75 */ 76#define NPE_MAXSEG 3 /* empirically selected */ 77 78struct npehwbuf { 79 struct { /* NPE shared area, cacheline aligned */ 80 uint32_t next; /* phys addr of next segment */ 81 uint32_t len; /* buffer/segment length (bytes) */ 82 uint32_t data; /* phys addr of data segment */ 83 uint32_t pad[5]; /* pad to cacheline */ 84 } ix_ne[NPE_MAXSEG]; 85}; 86 87#define NPE_FRAME_SIZE_DEFAULT 1536 88#define NPE_FRAME_SIZE_MAX (65536-64) 89#define NPE_FRAME_SIZE_MIN 64 90 91/* 92 * Queue Manager-related definitions. 93 * 94 * These define the layout of 32-bit Q entries passed 95 * between the host cpu and the NPE's. 96 */ 97#define NPE_QM_Q_NPE(e) (((e)>>0)&0x3) /* NPE ID */ 98#define NPE_QM_Q_PORT(e) (((e)>>3)&0x1) /* Port ID */ 99#define NPE_QM_Q_PRIO(e) (((e)>>0)&0x3) /* 802.1d priority */ 100#define NPE_QM_Q_ADDR(e) ((e)&0xfffffffe0) /* phys address */ 101 102/* 103 * Host->NPE requests written to the shared mailbox. 104 * The NPE writes the same value back as an ACK. 105 */ 106#define NPE_GETSTATUS 0x00 /* get firmware revision */ 107#define NPE_SETPORTADDRESS 0x01 /* set port id and mac address */ 108#define NPE_GETMACADDRDB 0x02 /* upload filter database */ 109#define NPE_SETMACADDRDB 0x03 /* download filter database */ 110#define NPE_GETSTATS 0x04 /* get statistics */ 111#define NPE_RESETSTATS 0x05 /* reset stats + return result */ 112#define NPE_SETMAXFRAME 0x06 /* configure max tx/rx frame lengths */ 113#define NPE_SETRXTAGMODE 0x07 /* configure VLAN rx operating mode */ 114#define NPE_SETDEFRXVID 0x08 /* set def VLAN tag + traffic class */ 115#define NPE_SETRXQOSENTRY 0x0b /* map user pri -> QoS class+rx qid */ 116#define NPE_SETFIREWALLMODE 0x0e /* config firewall services */ 117#define NPE_SETLOOPBACK 0x12 /* enable/disable loopback */ 118/* ... XXX more */ 119 120#define NPE_MAC_MSGID_SHL 24 121#define NPE_MAC_PORTID_SHL 16 122 123/* 124 * MAC register definitions; see section 125 * 15.2 of the Intel Developers Manual. 126 */ 127#define NPE_MAC_TX_CNTRL1 0x000 128#define NPE_MAC_TX_CNTRL2 0x004 129#define NPE_MAC_RX_CNTRL1 0x010 130#define NPE_MAC_RX_CNTRL2 0x014 131#define NPE_MAC_RANDOM_SEED 0x020 132#define NPE_MAC_THRESH_P_EMPTY 0x030 133#define NPE_MAC_THRESH_P_FULL 0x038 134#define NPE_MAC_BUF_SIZE_TX 0x040 135#define NPE_MAC_TX_DEFER 0x050 136#define NPE_MAC_RX_DEFER 0x054 137#define NPE_MAC_TX_TWO_DEFER_1 0x060 138#define NPE_MAC_TX_TWO_DEFER_2 0x064 139#define NPE_MAC_SLOT_TIME 0x070 140#define NPE_MAC_MDIO_CMD_1 0x080 141#define NPE_MAC_MDIO_CMD_2 0x084 142#define NPE_MAC_MDIO_CMD_3 0x088 143#define NPE_MAC_MDIO_CMD_4 0x08c 144#define NPE_MAC_MDIO_STS_1 0x090 145#define NPE_MAC_MDIO_STS_2 0x094 146#define NPE_MAC_MDIO_STS_3 0x098 147#define NPE_MAC_MDIO_STS_4 0x09c 148#define NPE_MAC_ADDR_MASK_1 0x0A0 149#define NPE_MAC_ADDR_MASK_2 0x0A4 150#define NPE_MAC_ADDR_MASK_3 0x0A8 151#define NPE_MAC_ADDR_MASK_4 0x0AC 152#define NPE_MAC_ADDR_MASK_5 0x0B0 153#define NPE_MAC_ADDR_MASK_6 0x0B4 154#define NPE_MAC_ADDR_1 0x0C0 155#define NPE_MAC_ADDR_2 0x0C4 156#define NPE_MAC_ADDR_3 0x0C8 157#define NPE_MAC_ADDR_4 0x0CC 158#define NPE_MAC_ADDR_5 0x0D0 159#define NPE_MAC_ADDR_6 0x0D4 160#define NPE_MAC_INT_CLK_THRESH 0x0E0 161#define NPE_MAC_UNI_ADDR_1 0x0F0 162#define NPE_MAC_UNI_ADDR_2 0x0F4 163#define NPE_MAC_UNI_ADDR_3 0x0F8 164#define NPE_MAC_UNI_ADDR_4 0x0FC 165#define NPE_MAC_UNI_ADDR_5 0x100 166#define NPE_MAC_UNI_ADDR_6 0x104 167#define NPE_MAC_CORE_CNTRL 0x1FC 168 169#define NPE_MAC_ADDR_MASK(i) (NPE_MAC_ADDR_MASK_1 + ((i)<<2)) 170#define NPE_MAC_ADDR(i) (NPE_MAC_ADDR_1 + ((i)<<2)) 171#define NPE_MAC_UNI_ADDR(i) (NPE_MAC_UNI_ADDR_1 + ((i)<<2)) 172 173/* 174 * Bit definitions 175 */ 176 177/* TX Control Register 1*/ 178#define NPE_TX_CNTRL1_TX_EN 0x01 /* enable TX engine */ 179#define NPE_TX_CNTRL1_DUPLEX 0x02 /* select half duplex */ 180#define NPE_TX_CNTRL1_RETRY 0x04 /* auto-retry on collision */ 181#define NPE_TX_CNTRL1_PAD_EN 0x08 /* pad frames <64 bytes */ 182#define NPE_TX_CNTRL1_FCS_EN 0x10 /* append FCS */ 183#define NPE_TX_CNTRL1_2DEFER 0x20 /* select 2-part deferral */ 184#define NPE_TX_CNTRL1_RMII 0x40 185 186/* TX Control Register 2 */ 187#define NPE_TX_CNTRL2_RETRIES_MASK 0xf /* max retry count */ 188 189/* RX Control Register 1 */ 190#define NPE_RX_CNTRL1_RX_EN 0x01 /* enable RX engine */ 191#define NPE_RX_CNTRL1_PADSTRIP_EN 0x02 /* strip frame padding */ 192#define NPE_RX_CNTRL1_CRC_EN 0x04 /* include CRC in RX frame */ 193#define NPE_RX_CNTRL1_PAUSE_EN 0x08 /* detect Pause frames */ 194#define NPE_RX_CNTRL1_LOOP_EN 0x10 /* loopback tx/rx */ 195#define NPE_RX_CNTRL1_ADDR_FLTR_EN 0x20 /* enable address filtering */ 196#define NPE_RX_CNTRL1_RX_RUNT_EN 0x40 /* enable RX of runt frames */ 197#define NPE_RX_CNTRL1_BCAST_DIS 0x80 /* discard broadcast frames */ 198 199/* RX Control Register 2 */ 200#define NPE_RX_CNTRL2_DEFER_EN 0x01 201 202/* Core Control Register */ 203#define NPE_CORE_RESET 0x01 /* MAC reset state */ 204#define NPE_CORE_RX_FIFO_FLUSH 0x02 /* flush RX FIFO */ 205#define NPE_CORE_TX_FIFO_FLUSH 0x04 /* flush TX FIFO */ 206#define NPE_CORE_SEND_JAM 0x08 /* send JAM on packet RX */ 207#define NPE_CORE_MDC_EN 0x10 /* IXP42X drives MDC clock */ 208 209/* 210 * Stat block returned by NPE with NPE_GETSTATS msg. 211 */ 212struct npestats { 213 uint32_t dot3StatsAlignmentErrors; 214 uint32_t dot3StatsFCSErrors; 215 uint32_t dot3StatsInternalMacReceiveErrors; 216 uint32_t RxOverrunDiscards; 217 uint32_t RxLearnedEntryDiscards; 218 uint32_t RxLargeFramesDiscards; 219 uint32_t RxSTPBlockedDiscards; 220 uint32_t RxVLANTypeFilterDiscards; 221 uint32_t RxVLANIdFilterDiscards; 222 uint32_t RxInvalidSourceDiscards; 223 uint32_t RxBlackListDiscards; 224 uint32_t RxWhiteListDiscards; 225 uint32_t RxUnderflowEntryDiscards; 226 uint32_t dot3StatsSingleCollisionFrames; 227 uint32_t dot3StatsMultipleCollisionFrames; 228 uint32_t dot3StatsDeferredTransmissions; 229 uint32_t dot3StatsLateCollisions; 230 uint32_t dot3StatsExcessiveCollisions; 231 uint32_t dot3StatsInternalMacTransmitErrors; 232 uint32_t dot3StatsCarrierSenseErrors; 233 uint32_t TxLargeFrameDiscards; 234 uint32_t TxVLANIdFilterDiscards; 235}; 236 237/* 238 * Default values 239 */ 240#define NPE_MAC_INT_CLK_THRESH_DEFAULT 0x1 241 242#define NPE_MAC_RESET_DELAY 1 243 244/* This value applies to RMII */ 245#define NPE_MAC_SLOT_TIME_RMII_DEFAULT 0xFF 246 247/* 248 * MII definitions - these have been verified against the LXT971 and LXT972 PHYs 249 */ 250#define NPE_MII_REG_SHL 16 251#define NPE_MII_ADDR_SHL 21 252 253/* NB: shorthands for mii bus mdio routines */ 254#define NPE_MAC_MDIO_CMD NPE_MAC_MDIO_CMD_1 255#define NPE_MAC_MDIO_STS NPE_MAC_MDIO_STS_1 256 257#define NPE_MII_GO (1<<31) 258#define NPE_MII_WRITE (1<<26) 259#define NPE_MII_TIMEOUT_10TH_SECS 5 260#define NPE_MII_10TH_SEC_IN_MILLIS 100 261#define NPE_MII_READ_FAIL (1<<31) 262 263#define NPE_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */ 264#define NPE_MII_PHY_NO_DELAY 0x0 /* do not delay */ 265#define NPE_MII_PHY_NULL 0xff /* PHY is not present */ 266#define NPE_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */ 267 268/* Register definition */ 269#define NPE_MII_CTRL_REG 0x0 /* Control Register */ 270#define NPE_MII_STAT_REG 0x1 /* Status Register */ 271#define NPE_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ 272#define NPE_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ 273#define NPE_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ 274 /* Advertisement Register */ 275#define NPE_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ 276 /* partner ability Register */ 277#define NPE_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ 278 /* Expansion Register */ 279#define NPE_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ 280 /* next-page transmit Register */ 281#endif /* ARM_XSCALE_IF_NPEREG_H */ 282