avila_machdep.c revision 259364
1/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ 2 3/*- 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * machdep.c 40 * 41 * Machine dependant functions for kernel setup 42 * 43 * This file needs a lot of work. 44 * 45 * Created : 17/09/94 46 */ 47 48#include <sys/cdefs.h> 49__FBSDID("$FreeBSD: stable/10/sys/arm/xscale/ixp425/avila_machdep.c 259364 2013-12-13 23:56:53Z ian $"); 50 51#define _ARM32_BUS_DMA_PRIVATE 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysproto.h> 55#include <sys/signalvar.h> 56#include <sys/imgact.h> 57#include <sys/kernel.h> 58#include <sys/ktr.h> 59#include <sys/linker.h> 60#include <sys/lock.h> 61#include <sys/malloc.h> 62#include <sys/mutex.h> 63#include <sys/pcpu.h> 64#include <sys/proc.h> 65#include <sys/ptrace.h> 66#include <sys/cons.h> 67#include <sys/bio.h> 68#include <sys/bus.h> 69#include <sys/buf.h> 70#include <sys/exec.h> 71#include <sys/kdb.h> 72#include <sys/msgbuf.h> 73#include <machine/reg.h> 74#include <machine/cpu.h> 75 76#include <vm/vm.h> 77#include <vm/pmap.h> 78#include <vm/vm_object.h> 79#include <vm/vm_page.h> 80#include <vm/vm_map.h> 81#include <machine/devmap.h> 82#include <machine/vmparam.h> 83#include <machine/pcb.h> 84#include <machine/undefined.h> 85#include <machine/machdep.h> 86#include <machine/metadata.h> 87#include <machine/armreg.h> 88#include <machine/bus.h> 89#include <sys/reboot.h> 90 91#include <arm/xscale/ixp425/ixp425reg.h> 92#include <arm/xscale/ixp425/ixp425var.h> 93 94/* kernel text starts where we were loaded at boot */ 95#define KERNEL_TEXT_OFF (KERNPHYSADDR - PHYSADDR) 96#define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF) 97#define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF) 98 99#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ 100#define KERNEL_PT_IO 1 101#define KERNEL_PT_IO_NUM 3 102#define KERNEL_PT_BEFOREKERN KERNEL_PT_IO + KERNEL_PT_IO_NUM 103#define KERNEL_PT_AFKERNEL KERNEL_PT_BEFOREKERN + 1 /* L2 table for mapping after kernel */ 104#define KERNEL_PT_AFKERNEL_NUM 9 105 106/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ 107#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) 108 109extern u_int data_abort_handler_address; 110extern u_int prefetch_abort_handler_address; 111extern u_int undefined_handler_address; 112 113struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; 114 115/* Physical and virtual addresses for some global pages */ 116 117vm_paddr_t phys_avail[10]; 118vm_paddr_t dump_avail[4]; 119 120struct pv_addr systempage; 121struct pv_addr msgbufpv; 122struct pv_addr irqstack; 123struct pv_addr undstack; 124struct pv_addr abtstack; 125struct pv_addr kernelstack; 126struct pv_addr minidataclean; 127 128/* Static device mappings. */ 129static const struct arm_devmap_entry ixp425_devmap[] = { 130 /* Physical/Virtual address for I/O space */ 131 { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, 132 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 133 134 /* Expansion Bus */ 135 { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 136 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 137 138 /* CFI Flash on the Expansion Bus */ 139 { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, 140 IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 141 142 /* IXP425 PCI Configuration */ 143 { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, 144 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 145 146 /* SDRAM Controller */ 147 { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE, 148 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 149 150 /* PCI Memory Space */ 151 { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, 152 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 153 154 /* Q-Mgr Memory Space */ 155 { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, 156 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 157 158 { 0 }, 159}; 160 161/* Static device mappings. */ 162static const struct arm_devmap_entry ixp435_devmap[] = { 163 /* Physical/Virtual address for I/O space */ 164 { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, 165 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 166 167 { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 168 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 169 170 /* IXP425 PCI Configuration */ 171 { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, 172 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 173 174 /* DDRII Controller NB: mapped same place as IXP425 */ 175 { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE, 176 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 177 178 /* PCI Memory Space */ 179 { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, 180 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 181 182 /* Q-Mgr Memory Space */ 183 { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, 184 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 185 186 /* CFI Flash on the Expansion Bus */ 187 { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, 188 IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 189 190 /* USB1 Memory Space */ 191 { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE, 192 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 193 /* USB2 Memory Space */ 194 { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE, 195 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 196 197 /* GPS Memory Space */ 198 { CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE, 199 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 200 201 /* RS485 Memory Space */ 202 { CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE, 203 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 204 205 { 0 } 206}; 207 208extern vm_offset_t xscale_cache_clean_addr; 209 210void * 211initarm(struct arm_boot_params *abp) 212{ 213#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1)) 214#define next_page(a) next_chunk2(a,PAGE_SIZE) 215 struct pv_addr kernel_l1pt; 216 struct pv_addr dpcpu; 217 int loop, i; 218 u_int l1pagetable; 219 vm_offset_t freemempos; 220 vm_offset_t freemem_pt; 221 vm_offset_t afterkern; 222 vm_offset_t freemem_after; 223 vm_offset_t lastaddr; 224 uint32_t memsize; 225 226 lastaddr = parse_boot_param(abp); 227 set_cpufuncs(); /* NB: sets cputype */ 228 pcpu_init(pcpup, 0, sizeof(struct pcpu)); 229 PCPU_SET(curthread, &thread0); 230 231 /* Do basic tuning, hz etc */ 232 init_param1(); 233 234 /* 235 * We allocate memory downwards from where we were loaded 236 * by RedBoot; first the L1 page table, then NUM_KERNEL_PTS 237 * entries in the L2 page table. Past that we re-align the 238 * allocation boundary so later data structures (stacks, etc) 239 * can be mapped with different attributes (write-back vs 240 * write-through). Note this leaves a gap for expansion 241 * (or might be repurposed). 242 */ 243 freemempos = KERNPHYSADDR; 244 245 /* macros to simplify initial memory allocation */ 246#define alloc_pages(var, np) do { \ 247 freemempos -= (np * PAGE_SIZE); \ 248 (var) = freemempos; \ 249 /* NB: this works because locore maps PA=VA */ \ 250 memset((char *)(var), 0, ((np) * PAGE_SIZE)); \ 251} while (0) 252#define valloc_pages(var, np) do { \ 253 alloc_pages((var).pv_pa, (np)); \ 254 (var).pv_va = (var).pv_pa + (KERNVIRTADDR - KERNPHYSADDR); \ 255} while (0) 256 257 /* force L1 page table alignment */ 258 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 259 freemempos -= PAGE_SIZE; 260 /* allocate contiguous L1 page table */ 261 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 262 /* now allocate L2 page tables; they are linked to L1 below */ 263 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { 264 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 265 valloc_pages(kernel_pt_table[loop], 266 L2_TABLE_SIZE / PAGE_SIZE); 267 } else { 268 kernel_pt_table[loop].pv_pa = freemempos + 269 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * 270 L2_TABLE_SIZE_REAL; 271 kernel_pt_table[loop].pv_va = 272 kernel_pt_table[loop].pv_pa + 273 (KERNVIRTADDR - KERNPHYSADDR); 274 } 275 } 276 freemem_pt = freemempos; /* base of allocated pt's */ 277 278 /* 279 * Re-align allocation boundary so we can map the area 280 * write-back instead of write-through for the stacks and 281 * related structures allocated below. 282 */ 283 freemempos = PHYSADDR + 0x100000; 284 /* 285 * Allocate a page for the system page mapped to V0x00000000 286 * This page will just contain the system vectors and can be 287 * shared by all processes. 288 */ 289 valloc_pages(systempage, 1); 290 291 /* Allocate dynamic per-cpu area. */ 292 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 293 dpcpu_init((void *)dpcpu.pv_va, 0); 294 295 /* Allocate stacks for all modes */ 296 valloc_pages(irqstack, IRQ_STACK_SIZE); 297 valloc_pages(abtstack, ABT_STACK_SIZE); 298 valloc_pages(undstack, UND_STACK_SIZE); 299 valloc_pages(kernelstack, KSTACK_PAGES); 300 alloc_pages(minidataclean.pv_pa, 1); 301 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 302#ifdef ARM_USE_SMALL_ALLOC 303 freemempos -= PAGE_SIZE; 304 freemem_pt = trunc_page(freemem_pt); 305 freemem_after = freemempos - ((freemem_pt - (PHYSADDR + 0x100000)) / 306 PAGE_SIZE) * sizeof(struct arm_small_page); 307 arm_add_smallalloc_pages( 308 (void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)), 309 (void *)0xc0100000, 310 freemem_pt - (PHYSADDR + 0x100000), 1); 311 freemem_after -= ((freemem_after - (PHYSADDR + 0x1000)) / PAGE_SIZE) * 312 sizeof(struct arm_small_page); 313 arm_add_smallalloc_pages( 314 (void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)), 315 (void *)0xc0001000, 316 trunc_page(freemem_after) - (PHYSADDR + 0x1000), 0); 317 freemempos = trunc_page(freemem_after); 318 freemempos -= PAGE_SIZE; 319#endif 320 321 /* 322 * Now construct the L1 page table. First map the L2 323 * page tables into the L1 so we can replace L1 mappings 324 * later on if necessary 325 */ 326 l1pagetable = kernel_l1pt.pv_va; 327 328 /* Map the L2 pages tables in the L1 page table */ 329 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), 330 &kernel_pt_table[KERNEL_PT_SYS]); 331 pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE, 332 &kernel_pt_table[KERNEL_PT_IO]); 333 pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE, 334 &kernel_pt_table[KERNEL_PT_IO + 1]); 335 pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE, 336 &kernel_pt_table[KERNEL_PT_IO + 2]); 337 pmap_link_l2pt(l1pagetable, KERNBASE, 338 &kernel_pt_table[KERNEL_PT_BEFOREKERN]); 339 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000, 340 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 341 pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000, 342 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 343 pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS, 344 next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE), 345 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 346 freemem_after = next_page((int)lastaddr); 347 afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE)); 348 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { 349 pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, 350 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); 351 } 352 pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, 353 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 354 355#ifdef ARM_USE_SMALL_ALLOC 356 if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) { 357 arm_add_smallalloc_pages((void *)(freemem_after), 358 (void*)(freemem_after + PAGE_SIZE), 359 afterkern - (freemem_after + PAGE_SIZE), 0); 360 361 } 362#endif 363 364 /* Map the Mini-Data cache clean area. */ 365 xscale_setup_minidata(l1pagetable, afterkern, 366 minidataclean.pv_pa); 367 368 /* Map the vector page. */ 369 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 370 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 371 if (cpu_is_ixp43x()) 372 arm_devmap_bootstrap(l1pagetable, ixp435_devmap); 373 else 374 arm_devmap_bootstrap(l1pagetable, ixp425_devmap); 375 /* 376 * Give the XScale global cache clean code an appropriately 377 * sized chunk of unmapped VA space starting at 0xff000000 378 * (our device mappings end before this address). 379 */ 380 xscale_cache_clean_addr = 0xff000000U; 381 382 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 383 setttb(kernel_l1pt.pv_pa); 384 cpu_tlb_flushID(); 385 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); 386 387 /* 388 * Pages were allocated during the secondary bootstrap for the 389 * stacks for different CPU modes. 390 * We must now set the r13 registers in the different CPU modes to 391 * point to these stacks. 392 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 393 * of the stack memory. 394 */ 395 set_stackptrs(0); 396 397 /* 398 * We must now clean the cache again.... 399 * Cleaning may be done by reading new data to displace any 400 * dirty data in the cache. This will have happened in setttb() 401 * but since we are boot strapping the addresses used for the read 402 * may have just been remapped and thus the cache could be out 403 * of sync. A re-clean after the switch will cure this. 404 * After booting there are no gross relocations of the kernel thus 405 * this problem will not occur after initarm(). 406 */ 407 cpu_idcache_wbinv_all(); 408 /* ready to setup the console (XXX move earlier if possible) */ 409 cninit(); 410 /* 411 * Fetch the RAM size from the MCU registers. The 412 * expansion bus was mapped above so we can now read 'em. 413 */ 414 if (cpu_is_ixp43x()) 415 memsize = ixp435_ddram_size(); 416 else 417 memsize = ixp425_sdram_size(); 418 physmem = memsize / PAGE_SIZE; 419 420 /* Set stack for exception handlers */ 421 422 data_abort_handler_address = (u_int)data_abort_handler; 423 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 424 undefined_handler_address = (u_int)undefinedinstruction_bounce; 425 undefined_init(); 426 427 init_proc0(kernelstack.pv_va); 428 429 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 430 431 pmap_curmaxkvaddr = afterkern + PAGE_SIZE; 432 arm_dump_avail_init(memsize, sizeof(dump_avail) / sizeof(dump_avail[0])); 433 vm_max_kernel_address = 0xd0000000; 434 pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); 435 msgbufp = (void*)msgbufpv.pv_va; 436 msgbufinit(msgbufp, msgbufsize); 437 mutex_init(); 438 439 i = 0; 440#ifdef ARM_USE_SMALL_ALLOC 441 phys_avail[i++] = PHYSADDR; 442 phys_avail[i++] = PHYSADDR + PAGE_SIZE; /* 443 *XXX: Gross hack to get our 444 * pages in the vm_page_array. 445 */ 446#endif 447 phys_avail[i++] = round_page(virtual_avail - KERNBASE + PHYSADDR); 448 phys_avail[i++] = trunc_page(PHYSADDR + memsize - 1); 449 phys_avail[i++] = 0; 450 phys_avail[i] = 0; 451 452 init_param2(physmem); 453 kdb_init(); 454 455 /* use static kernel environment if so configured */ 456 if (envmode == 1) 457 kern_envp = static_env; 458 459 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 460 sizeof(struct pcb))); 461#undef next_page 462#undef next_chunk2 463} 464