1/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ 2 3/*- 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * machdep.c 40 * 41 * Machine dependant functions for kernel setup 42 * 43 * This file needs a lot of work. 44 * 45 * Created : 17/09/94 46 */ 47 48#include <sys/cdefs.h> 49__FBSDID("$FreeBSD$"); 50 51#define _ARM32_BUS_DMA_PRIVATE 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysproto.h> 55#include <sys/signalvar.h> 56#include <sys/imgact.h> 57#include <sys/kernel.h> 58#include <sys/ktr.h> 59#include <sys/linker.h> 60#include <sys/lock.h> 61#include <sys/malloc.h> 62#include <sys/mutex.h> 63#include <sys/pcpu.h> 64#include <sys/proc.h> 65#include <sys/ptrace.h> 66#include <sys/cons.h> 67#include <sys/bio.h> 68#include <sys/bus.h> 69#include <sys/buf.h> 70#include <sys/exec.h> 71#include <sys/kdb.h> 72#include <sys/msgbuf.h> 73#include <machine/physmem.h> 74#include <machine/reg.h> 75#include <machine/cpu.h> 76 77#include <vm/vm.h> 78#include <vm/pmap.h> 79#include <vm/vm_object.h> 80#include <vm/vm_page.h> 81#include <vm/vm_map.h> 82#include <machine/devmap.h> 83#include <machine/vmparam.h> 84#include <machine/pcb.h> 85#include <machine/undefined.h> 86#include <machine/machdep.h> 87#include <machine/metadata.h> 88#include <machine/armreg.h> 89#include <machine/bus.h> 90#include <sys/reboot.h> 91 92#include <arm/xscale/ixp425/ixp425reg.h> 93#include <arm/xscale/ixp425/ixp425var.h> 94 95#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ 96#define KERNEL_PT_IO 1 97#define KERNEL_PT_IO_NUM 3 98#define KERNEL_PT_BEFOREKERN KERNEL_PT_IO + KERNEL_PT_IO_NUM 99#define KERNEL_PT_AFKERNEL KERNEL_PT_BEFOREKERN + 1 /* L2 table for mapping after kernel */ 100#define KERNEL_PT_AFKERNEL_NUM 9 101 102/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ 103#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) 104 105struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; 106 107/* Physical and virtual addresses for some global pages */ 108 109struct pv_addr systempage; 110struct pv_addr msgbufpv; 111struct pv_addr irqstack; 112struct pv_addr undstack; 113struct pv_addr abtstack; 114struct pv_addr kernelstack; 115struct pv_addr minidataclean; 116 117/* Static device mappings. */ 118static const struct arm_devmap_entry ixp425_devmap[] = { 119 /* Physical/Virtual address for I/O space */ 120 { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, 121 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 122 123 /* Expansion Bus */ 124 { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 125 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 126 127 /* CFI Flash on the Expansion Bus */ 128 { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, 129 IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 130 131 /* IXP425 PCI Configuration */ 132 { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, 133 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 134 135 /* SDRAM Controller */ 136 { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE, 137 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 138 139 /* PCI Memory Space */ 140 { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, 141 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 142 143 /* Q-Mgr Memory Space */ 144 { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, 145 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 146 147 { 0 }, 148}; 149 150/* Static device mappings. */ 151static const struct arm_devmap_entry ixp435_devmap[] = { 152 /* Physical/Virtual address for I/O space */ 153 { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, 154 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 155 156 { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 157 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 158 159 /* IXP425 PCI Configuration */ 160 { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, 161 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 162 163 /* DDRII Controller NB: mapped same place as IXP425 */ 164 { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE, 165 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 166 167 /* PCI Memory Space */ 168 { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, 169 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 170 171 /* Q-Mgr Memory Space */ 172 { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, 173 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 174 175 /* CFI Flash on the Expansion Bus */ 176 { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, 177 IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 178 179 /* USB1 Memory Space */ 180 { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE, 181 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 182 /* USB2 Memory Space */ 183 { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE, 184 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 185 186 /* GPS Memory Space */ 187 { CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE, 188 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 189 190 /* RS485 Memory Space */ 191 { CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE, 192 VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, 193 194 { 0 } 195}; 196 197extern vm_offset_t xscale_cache_clean_addr; 198 199void * 200initarm(struct arm_boot_params *abp) 201{ 202#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1)) 203#define next_page(a) next_chunk2(a,PAGE_SIZE) 204 struct pv_addr kernel_l1pt; 205 struct pv_addr dpcpu; 206 int loop, i; 207 u_int l1pagetable; 208 vm_offset_t freemempos; 209 vm_offset_t freemem_pt; 210 vm_offset_t afterkern; 211 vm_offset_t freemem_after; 212 vm_offset_t lastaddr; 213 uint32_t memsize; 214 215 /* kernel text starts where we were loaded at boot */ 216#define KERNEL_TEXT_OFF (abp->abp_physaddr - PHYSADDR) 217#define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF) 218#define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF) 219 220 lastaddr = parse_boot_param(abp); 221 arm_physmem_kernaddr = abp->abp_physaddr; 222 set_cpufuncs(); /* NB: sets cputype */ 223 pcpu_init(pcpup, 0, sizeof(struct pcpu)); 224 PCPU_SET(curthread, &thread0); 225 226 init_static_kenv(NULL, 0); 227 228 /* Do basic tuning, hz etc */ 229 init_param1(); 230 231 /* 232 * We allocate memory downwards from where we were loaded 233 * by RedBoot; first the L1 page table, then NUM_KERNEL_PTS 234 * entries in the L2 page table. Past that we re-align the 235 * allocation boundary so later data structures (stacks, etc) 236 * can be mapped with different attributes (write-back vs 237 * write-through). Note this leaves a gap for expansion 238 * (or might be repurposed). 239 */ 240 freemempos = abp->abp_physaddr; 241 242 /* macros to simplify initial memory allocation */ 243#define alloc_pages(var, np) do { \ 244 freemempos -= (np * PAGE_SIZE); \ 245 (var) = freemempos; \ 246 /* NB: this works because locore maps PA=VA */ \ 247 memset((char *)(var), 0, ((np) * PAGE_SIZE)); \ 248} while (0) 249#define valloc_pages(var, np) do { \ 250 alloc_pages((var).pv_pa, (np)); \ 251 (var).pv_va = (var).pv_pa + (KERNVIRTADDR - abp->abp_physaddr); \ 252} while (0) 253 254 /* force L1 page table alignment */ 255 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 256 freemempos -= PAGE_SIZE; 257 /* allocate contiguous L1 page table */ 258 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 259 /* now allocate L2 page tables; they are linked to L1 below */ 260 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { 261 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 262 valloc_pages(kernel_pt_table[loop], 263 L2_TABLE_SIZE / PAGE_SIZE); 264 } else { 265 kernel_pt_table[loop].pv_pa = freemempos + 266 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * 267 L2_TABLE_SIZE_REAL; 268 kernel_pt_table[loop].pv_va = 269 kernel_pt_table[loop].pv_pa + 270 (KERNVIRTADDR - abp->abp_physaddr); 271 } 272 } 273 freemem_pt = freemempos; /* base of allocated pt's */ 274 275 /* 276 * Re-align allocation boundary so we can map the area 277 * write-back instead of write-through for the stacks and 278 * related structures allocated below. 279 */ 280 freemempos = PHYSADDR + 0x100000; 281 /* 282 * Allocate a page for the system page mapped to V0x00000000 283 * This page will just contain the system vectors and can be 284 * shared by all processes. 285 */ 286 valloc_pages(systempage, 1); 287 288 /* Allocate dynamic per-cpu area. */ 289 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 290 dpcpu_init((void *)dpcpu.pv_va, 0); 291 292 /* Allocate stacks for all modes */ 293 valloc_pages(irqstack, IRQ_STACK_SIZE); 294 valloc_pages(abtstack, ABT_STACK_SIZE); 295 valloc_pages(undstack, UND_STACK_SIZE); 296 valloc_pages(kernelstack, KSTACK_PAGES); 297 alloc_pages(minidataclean.pv_pa, 1); 298 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 299 300 /* 301 * Now construct the L1 page table. First map the L2 302 * page tables into the L1 so we can replace L1 mappings 303 * later on if necessary 304 */ 305 l1pagetable = kernel_l1pt.pv_va; 306 307 /* Map the L2 pages tables in the L1 page table */ 308 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), 309 &kernel_pt_table[KERNEL_PT_SYS]); 310 pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE, 311 &kernel_pt_table[KERNEL_PT_IO]); 312 pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE, 313 &kernel_pt_table[KERNEL_PT_IO + 1]); 314 pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE, 315 &kernel_pt_table[KERNEL_PT_IO + 2]); 316 pmap_link_l2pt(l1pagetable, KERNBASE, 317 &kernel_pt_table[KERNEL_PT_BEFOREKERN]); 318 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000, 319 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 320 pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000, 321 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 322 pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS, 323 next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE), 324 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 325 freemem_after = next_page((int)lastaddr); 326 afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE)); 327 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { 328 pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, 329 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); 330 } 331 pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, 332 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 333 334 335 /* Map the Mini-Data cache clean area. */ 336 xscale_setup_minidata(l1pagetable, afterkern, 337 minidataclean.pv_pa); 338 339 /* Map the vector page. */ 340 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 341 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 342 if (cpu_is_ixp43x()) 343 arm_devmap_bootstrap(l1pagetable, ixp435_devmap); 344 else 345 arm_devmap_bootstrap(l1pagetable, ixp425_devmap); 346 /* 347 * Give the XScale global cache clean code an appropriately 348 * sized chunk of unmapped VA space starting at 0xff000000 349 * (our device mappings end before this address). 350 */ 351 xscale_cache_clean_addr = 0xff000000U; 352 353 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 354 setttb(kernel_l1pt.pv_pa); 355 cpu_tlb_flushID(); 356 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); 357 358 /* 359 * Pages were allocated during the secondary bootstrap for the 360 * stacks for different CPU modes. 361 * We must now set the r13 registers in the different CPU modes to 362 * point to these stacks. 363 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 364 * of the stack memory. 365 */ 366 set_stackptrs(0); 367 368 /* 369 * We must now clean the cache again.... 370 * Cleaning may be done by reading new data to displace any 371 * dirty data in the cache. This will have happened in setttb() 372 * but since we are boot strapping the addresses used for the read 373 * may have just been remapped and thus the cache could be out 374 * of sync. A re-clean after the switch will cure this. 375 * After booting there are no gross relocations of the kernel thus 376 * this problem will not occur after initarm(). 377 */ 378 cpu_idcache_wbinv_all(); 379 cpu_setup(""); 380 381 /* ready to setup the console (XXX move earlier if possible) */ 382 cninit(); 383 /* 384 * Fetch the RAM size from the MCU registers. The 385 * expansion bus was mapped above so we can now read 'em. 386 */ 387 if (cpu_is_ixp43x()) 388 memsize = ixp435_ddram_size(); 389 else 390 memsize = ixp425_sdram_size(); 391 392 undefined_init(); 393 394 init_proc0(kernelstack.pv_va); 395 396 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 397 398 pmap_curmaxkvaddr = afterkern + PAGE_SIZE; 399 vm_max_kernel_address = 0xd0000000; 400 pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); 401 msgbufp = (void*)msgbufpv.pv_va; 402 msgbufinit(msgbufp, msgbufsize); 403 mutex_init(); 404 405 /* 406 * Add the physical ram we have available. 407 * 408 * Exclude the kernel, and all the things we allocated which immediately 409 * follow the kernel, from the VM allocation pool but not from crash 410 * dumps. virtual_avail is a global variable which tracks the kva we've 411 * "allocated" while setting up pmaps. 412 * 413 * Prepare the list of physical memory available to the vm subsystem. 414 */ 415 arm_physmem_hardware_region(PHYSADDR, memsize); 416 arm_physmem_exclude_region(abp->abp_physaddr, 417 virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC); 418 arm_physmem_init_kernel_globals(); 419 420 init_param2(physmem); 421 kdb_init(); 422 423 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 424 sizeof(struct pcb))); 425#undef next_page 426#undef next_chunk2 427} 428