i80321_intr.h revision 161592
117683Spst/* $NetBSD: i80321_intr.h,v 1.5 2004/01/12 10:25:06 scw Exp $ */ 217683Spst 317683Spst/*- 417683Spst * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 517683Spst * All rights reserved. 617683Spst * 717683Spst * Written by Jason R. Thorpe for Wasabi Systems, Inc. 817683Spst * 917683Spst * Redistribution and use in source and binary forms, with or without 1017683Spst * modification, are permitted provided that the following conditions 1117683Spst * are met: 1217683Spst * 1. Redistributions of source code must retain the above copyright 1317683Spst * notice, this list of conditions and the following disclaimer. 1417683Spst * 2. Redistributions in binary form must reproduce the above copyright 1517683Spst * notice, this list of conditions and the following disclaimer in the 1617683Spst * documentation and/or other materials provided with the distribution. 1717683Spst * 3. All advertising materials mentioning features or use of this software 1817683Spst * must display the following acknowledgement: 1917683Spst * This product includes software developed for the NetBSD Project by 2017683Spst * Wasabi Systems, Inc. 2117683Spst * 4. The name of Wasabi Systems, Inc. may not be used to endorse 2217683Spst * or promote products derived from this software without specific prior 2317683Spst * written permission. 2417683Spst * 2517683Spst * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 2617683Spst * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2717683Spst * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2817683Spst * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 2917683Spst * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 3017683Spst * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 3117683Spst * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 3217683Spst * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3326175Sfenner * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3417683Spst * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3517683Spst * POSSIBILITY OF SUCH DAMAGE. 3617683Spst * 3717683Spst * $FreeBSD: head/sys/arm/xscale/i80321/i80321_intr.h 161592 2006-08-24 23:51:28Z cognet $ 3817683Spst * 3938151Sphk */ 4038151Sphk 4138151Sphk#ifndef _I80321_INTR_H_ 4238151Sphk#define _I80321_INTR_H_ 4317683Spst 4417683Spst#define ARM_IRQ_HANDLER _C_LABEL(i80321_intr_dispatch) 4517683Spst 4617683Spst#ifndef _LOCORE 4717683Spst 4817683Spst#include <machine/armreg.h> 4917683Spst#include <machine/cpufunc.h> 5017683Spst 5117683Spst#include <arm/xscale/i80321/i80321reg.h> 5217683Spst 5317683Spstvoid i80321_do_pending(void); 5417683Spst 5517683Spstextern __volatile uint32_t intr_enabled; 5617683Spstextern uint32_t intr_steer; 5717683Spst 5817683Spststatic __inline void __attribute__((__unused__)) 5917683Spsti80321_set_intrmask(void) 6017683Spst{ 6117683Spst 6217683Spst __asm __volatile("mcr p6, 0, %0, c0, c0, 0" 6317683Spst : 6417683Spst : "r" (intr_enabled & ICU_INT_HWMASK)); 6526175Sfenner} 6626175Sfenner 6726175Sfennerstatic __inline void 6826175Sfenneri80321_set_intrsteer(void) 6926175Sfenner{ 7017683Spst 7117683Spst __asm __volatile("mcr p6, 0, %0, c4, c0, 0" 7217683Spst : 7317683Spst : "r" (intr_steer & ICU_INT_HWMASK)); 7417683Spst} 7517683Spst 7617683Spst#if defined ( CPU_XSCALE_80219 ) 7717683Spst#define INT_SWMASK \ 7817683Spst ((1U << ICU_INT_bit26) | \ 7917683Spst (1U << ICU_INT_bit25) | \ 8017683Spst (1U << ICU_INT_bit23) | \ 8117683Spst (1U << ICU_INT_bit22) | \ 8217683Spst (1U << ICU_INT_bit7) | \ 8317683Spst (1U << ICU_INT_bit6) | \ 8417683Spst (1U << ICU_INT_bit5) | \ 8517683Spst (1U << ICU_INT_bit4)) 8617683Spst#else 8717683Spst#define INT_SWMASK \ 8817683Spst ((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) | \ 8917683Spst (1U << ICU_INT_bit5) | (1U << ICU_INT_bit4)) 9017683Spst#endif 9117683Spst 9217683Spst#if 0 9317683Spststatic __inline void __attribute__((__unused__)) 9417683Spsti80321_splx(int new) 9517683Spst{ 9617683Spst extern __volatile uint32_t intr_enabled; 9717683Spst extern __volatile int current_spl_level; 9817683Spst extern __volatile int i80321_ipending; 9917683Spst extern void i80321_do_pending(void); 10017683Spst int oldirqstate, hwpend; 10117683Spst 10217683Spst /* Don't let the compiler re-order this code with preceding code */ 10317683Spst __insn_barrier(); 10417683Spst 10517683Spst current_spl_level = new; 10617683Spst 10717683Spst hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new; 10817683Spst if (hwpend != 0) { 10917683Spst oldirqstate = disable_interrupts(I32_bit); 11017683Spst intr_enabled |= hwpend; 11117683Spst i80321_set_intrmask(); 11217683Spst restore_interrupts(oldirqstate); 11317683Spst } 11417683Spst 11517683Spst if ((i80321_ipending & INT_SWMASK) & ~new) 11617683Spst i80321_do_pending(); 11717683Spst} 11817683Spst 11917683Spststatic __inline int __attribute__((__unused__)) 12017683Spsti80321_splraise(int ipl) 12138151Sphk{ 12238151Sphk extern __volatile int current_spl_level; 12338151Sphk extern int i80321_imask[]; 12417683Spst int old; 12538151Sphk 12638151Sphk old = current_spl_level; 127 current_spl_level |= i80321_imask[ipl]; 128 129 /* Don't let the compiler re-order this code with subsequent code */ 130 __insn_barrier(); 131 132 return (old); 133} 134 135static __inline int __attribute__((__unused__)) 136i80321_spllower(int ipl) 137{ 138 extern __volatile int current_spl_level; 139 extern int i80321_imask[]; 140 int old = current_spl_level; 141 142 i80321_splx(i80321_imask[ipl]); 143 return(old); 144} 145 146#endif 147#if !defined(EVBARM_SPL_NOINLINE) 148 149#define splx(new) i80321_splx(new) 150#define _spllower(ipl) i80321_spllower(ipl) 151#define _splraise(ipl) i80321_splraise(ipl) 152void _setsoftintr(int); 153 154#else 155 156int _splraise(int); 157int _spllower(int); 158void splx(int); 159void _setsoftintr(int); 160 161#endif /* ! EVBARM_SPL_NOINLINE */ 162 163#endif /* _LOCORE */ 164 165#endif /* _I80321_INTR_H_ */ 166