1/*	$NetBSD: sysarch.h,v 1.5 2003/09/11 09:40:12 kleink Exp $	*/
2
3/*-
4 * Copyright (c) 1996-1997 Mark Brinicombe.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 *    must display the following acknowledgement:
17 *	This product includes software developed by Mark Brinicombe.
18 * 4. The name of the company nor the name of the author may be used to
19 *    endorse or promote products derived from this software without specific
20 *    prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35/* $FreeBSD$ */
36
37#ifndef _ARM_SYSARCH_H_
38#define _ARM_SYSARCH_H_
39
40#include <machine/armreg.h>
41/*
42 * The ARM_TP_ADDRESS points to a special purpose page, which is used as local
43 * store for the ARM per-thread data and Restartable Atomic Sequences support.
44 * Put it just above the "high" vectors' page.
45 * The cpu_switch() code assumes ARM_RAS_START is ARM_TP_ADDRESS + 4, and
46 * ARM_RAS_END is ARM_TP_ADDRESS + 8, so if that ever changes, be sure to
47 * update the cpu_switch() (and cpu_throw()) code as well.
48 * In addition, code in arm/include/atomic.h and arm/arm/exception.S
49 * assumes that ARM_RAS_END is at ARM_RAS_START+4, so be sure to update those
50 * if ARM_RAS_END moves in relation to ARM_RAS_START (look for occurrences
51 * of ldr/str rm,[rn, #4]).
52 */
53
54/* ARM_TP_ADDRESS is needed for processors that don't support
55 * the exclusive-access opcodes introduced with ARMv6K. */
56/* TODO: #if !defined(_HAVE_ARMv6K_INSTRUCTIONS) */
57#if !defined (__ARM_ARCH_7__) && \
58	!defined (__ARM_ARCH_7A__) && \
59	!defined (__ARM_ARCH_6K__) &&  \
60	!defined (__ARM_ARCH_6ZK__)
61#define ARM_TP_ADDRESS		(ARM_VECTORS_HIGH + 0x1000)
62#define ARM_RAS_START		(ARM_TP_ADDRESS + 4)
63#define ARM_RAS_END		(ARM_TP_ADDRESS + 8)
64#endif
65
66#ifndef LOCORE
67#ifndef __ASSEMBLER__
68
69#include <sys/cdefs.h>
70
71/*
72 * Pickup definition of uintptr_t
73 */
74#include <sys/stdint.h>
75
76/*
77 * Architecture specific syscalls (arm)
78 */
79
80#define ARM_SYNC_ICACHE		0
81#define ARM_DRAIN_WRITEBUF	1
82#define ARM_SET_TP		2
83#define ARM_GET_TP		3
84
85struct arm_sync_icache_args {
86	uintptr_t	addr;		/* Virtual start address */
87	size_t		len;		/* Region size */
88};
89
90#ifndef _KERNEL
91__BEGIN_DECLS
92int	arm_sync_icache (u_int addr, int len);
93int	arm_drain_writebuf (void);
94int	sysarch(int, void *);
95__END_DECLS
96#endif
97
98#endif /* __ASSEMBLER__ */
99#endif /* LOCORE */
100
101#endif /* !_ARM_SYSARCH_H_ */
102