1/*-
2 * Copyright (c) 2012 M. Warner Losh.  All Rights Reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD$");
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/bus.h>
32#include <sys/kernel.h>
33#include <sys/malloc.h>
34#include <sys/module.h>
35
36#define	_ARM32_BUS_DMA_PRIVATE
37#include <machine/bus.h>
38
39#include <arm/at91/at91var.h>
40#include <arm/at91/at91board.h>
41#include <arm/at91/at91rm92reg.h>
42#include <arm/at91/at91rm9200var.h>
43#include <arm/at91/at91_pioreg.h>
44#include <arm/at91/at91_piovar.h>
45
46/*
47 * The AT91RM9200 uses the same silicon for both the BGA and PQFP
48 * packages.  There's no documented way to detect this at runtime,
49 * so we require the board code to register what type of SoC is on the
50 * board in question.  The pinouts are not quite compatible, and we
51 * use this information to cope with the slight differences.
52 */
53void
54at91rm9200_set_subtype(enum at91_soc_subtype st)
55{
56
57	switch (st) {
58	case AT91_ST_RM9200_BGA:
59	case AT91_ST_RM9200_PQFP:
60		soc_info.subtype = st;
61		break;
62	default:
63		panic("Bad SoC subtype %d for at91rm9200_set_subtype.", st);
64		break;
65	}
66}
67
68void
69at91rm9200_config_uart(unsigned devid, unsigned unit, unsigned pinmask)
70{
71
72	/*
73	 * Since the USART supports RS-485 multidrop mode, it allows the
74	 * TX pins to float.  However, for RS-232 operations, we don't want
75	 * these pins to float.  Instead, they should be pulled up to avoid
76	 * mismatches.  Linux does something similar when it configures the
77	 * TX lines.  This implies that we also allow the RX lines to float
78	 * rather than be in the state they are left in by the boot loader.
79	 * Since they are input pins, I think that this is the right thing
80	 * to do.
81	 */
82
83	/*
84	 * Current boards supported don't need the extras, but they should be
85	 * implemented.  But that should wait until the new pin api goes in.
86	 */
87	switch (devid) {
88	case AT91_ID_DBGU:
89		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA30, 0); /* DRXD */
90		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA31, 1); /* DTXD */
91		break;
92
93	case AT91RM9200_ID_USART0:
94		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA17, 1); /* TXD0 */
95		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA18, 0); /* RXD0 */
96		/* CTS PA20 */
97		/* RTS -- errata #39 PA21 */
98		break;
99
100	case AT91RM9200_ID_USART1:
101		at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PIO_PB20, 1); /* TXD1 */
102		at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PIO_PB21, 0); /* RXD1 */
103		/* RI - PB18 */
104		/* DTR - PB19 */
105		/* DCD - PB23 */
106		/* CTS - PB24 */
107		/* DSR - PB25 */
108		/* RTS - PB26 */
109		break;
110
111	case AT91RM9200_ID_USART2:
112		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA22, 0); /* RXD2 */
113		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA23, 1); /* TXD2 */
114		/* CTS - PA30 B periph */
115		/* RTS - PA31 B periph */
116		break;
117
118	case AT91RM9200_ID_USART3:
119		at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA5, 1); /* TXD3 */
120		at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA6, 0); /* RXD3 */
121		/* CTS - PB0 B periph */
122		/* RTS - PB1 B periph */
123		break;
124
125	default:
126		break;
127	}
128}
129
130void
131at91rm9200_config_mci(int has_4wire)
132{
133	/* XXX TODO chip changed GPIO, other slots, etc */
134	at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA27,  0); /* MCCK */
135	at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA28, 1);  /* MCCDA */
136	at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA29, 1);  /* MCDA0 */
137	if (has_4wire) {
138		at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB3, 1); /* MCDA1 */
139		at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB4, 1); /* MCDA2 */
140		at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB5, 1); /* MCDA3 */
141	}
142}
143