1/*	$NetBSD: cpufunc_asm_arm11.S,v 1.2 2005/12/11 12:16:41 christos Exp $	*/
2
3/*
4 * Copyright (c) 2002, 2005 ARM Limited
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 *    products derived from this software without specific prior written
17 *    permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * ARM11 assembly functions for CPU / MMU / TLB specific operations
32 *
33 * XXX We make no attempt at present to take advantage of the v6 memroy
34 * architecture or physically tagged cache.
35 */
36
37#include <machine/asm.h>
38__FBSDID("$FreeBSD$");
39
40/*
41 * Functions to set the MMU Translation Table Base register
42 *
43 * We need to clean and flush the cache as it uses virtual
44 * addresses that are about to change.
45 */
46ENTRY(arm11_setttb)
47	mcr	p15, 0, r0, c2, c0, 0	/* load new TTB */
48
49	mcr	p15, 0, r0, c8, c7, 0	/* invalidate I+D TLBs */
50	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
51	RET
52END(arm11_setttb)
53
54/*
55 * TLB functions
56 */
57ENTRY(arm11_tlb_flushID_SE)
58	mcr	p15, 0, r0, c8, c6, 1	/* flush D tlb single entry */
59	mcr	p15, 0, r0, c8, c5, 1	/* flush I tlb single entry */
60	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
61	RET
62END(arm11_tlb_flushID_SE)
63
64ENTRY(arm11_tlb_flushI_SE)
65	mcr	p15, 0, r0, c8, c5, 1	/* flush I tlb single entry */
66	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
67	RET
68END(arm11_tlb_flushI_SE)
69
70/*
71 * Context switch.
72 *
73 * These is the CPU-specific parts of the context switcher cpu_switch()
74 * These functions actually perform the TTB reload.
75 *
76 * NOTE: Special calling convention
77 *	r1, r4-r13 must be preserved
78 */
79ENTRY(arm11_context_switch)
80	/*
81	 * We can assume that the caches will only contain kernel addresses
82	 * at this point.  So no need to flush them again.
83	 */
84	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
85	mcr	p15, 0, r0, c2, c0, 0	/* set the new TTB */
86	mcr	p15, 0, r0, c8, c7, 0	/* and flush the I+D tlbs */
87
88	/* Paranoia -- make sure the pipeline is empty. */
89	nop
90	nop
91	nop
92	RET
93END(arm11_context_switch)
94
95/*
96 * TLB functions
97 */
98ENTRY(arm11_tlb_flushID)
99	mcr	p15, 0, r0, c8, c7, 0	/* flush I+D tlb */
100	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
101	mov	pc, lr
102END(arm11_tlb_flushID)
103
104ENTRY(arm11_tlb_flushI)
105	mcr	p15, 0, r0, c8, c5, 0	/* flush I tlb */
106	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
107	mov	pc, lr
108END(arm11_tlb_flushI)
109
110ENTRY(arm11_tlb_flushD)
111	mcr	p15, 0, r0, c8, c6, 0	/* flush D tlb */
112	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
113	mov	pc, lr
114END(arm11_tlb_flushD)
115
116ENTRY(arm11_tlb_flushD_SE)
117	mcr	p15, 0, r0, c8, c6, 1	/* flush D tlb single entry */
118	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
119	mov	pc, lr
120END(arm11_tlb_flushD_SE)
121
122/*
123 * Other functions
124 */
125ENTRY(arm11_drain_writebuf)
126	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
127	mov	pc, lr
128END(arm11_drain_writebuf)
129
130ENTRY_NP(arm11_sleep)
131	mov	r0, #0
132	mcr	p15, 0, r0, c7, c0, 4   /* wait for interrupt */
133	RET
134END(arm11_sleep)
135
136