svm.c revision 308436
1/*- 2 * Copyright (c) 2013, Anish Gupta (akgupt3@gmail.com) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/amd64/vmm/amd/svm.c 308436 2016-11-08 07:18:39Z avg $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/smp.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/pcpu.h> 36#include <sys/proc.h> 37#include <sys/sysctl.h> 38 39#include <vm/vm.h> 40#include <vm/pmap.h> 41 42#include <machine/cpufunc.h> 43#include <machine/psl.h> 44#include <machine/pmap.h> 45#include <machine/md_var.h> 46#include <machine/specialreg.h> 47#include <machine/smp.h> 48#include <machine/vmm.h> 49#include <machine/vmm_dev.h> 50#include <machine/vmm_instruction_emul.h> 51 52#include "vmm_lapic.h" 53#include "vmm_stat.h" 54#include "vmm_ktr.h" 55#include "vmm_ioport.h" 56#include "vatpic.h" 57#include "vlapic.h" 58#include "vlapic_priv.h" 59 60#include "x86.h" 61#include "vmcb.h" 62#include "svm.h" 63#include "svm_softc.h" 64#include "svm_msr.h" 65#include "npt.h" 66 67SYSCTL_DECL(_hw_vmm); 68SYSCTL_NODE(_hw_vmm, OID_AUTO, svm, CTLFLAG_RW, NULL, NULL); 69 70/* 71 * SVM CPUID function 0x8000_000A, edx bit decoding. 72 */ 73#define AMD_CPUID_SVM_NP BIT(0) /* Nested paging or RVI */ 74#define AMD_CPUID_SVM_LBR BIT(1) /* Last branch virtualization */ 75#define AMD_CPUID_SVM_SVML BIT(2) /* SVM lock */ 76#define AMD_CPUID_SVM_NRIP_SAVE BIT(3) /* Next RIP is saved */ 77#define AMD_CPUID_SVM_TSC_RATE BIT(4) /* TSC rate control. */ 78#define AMD_CPUID_SVM_VMCB_CLEAN BIT(5) /* VMCB state caching */ 79#define AMD_CPUID_SVM_FLUSH_BY_ASID BIT(6) /* Flush by ASID */ 80#define AMD_CPUID_SVM_DECODE_ASSIST BIT(7) /* Decode assist */ 81#define AMD_CPUID_SVM_PAUSE_INC BIT(10) /* Pause intercept filter. */ 82#define AMD_CPUID_SVM_PAUSE_FTH BIT(12) /* Pause filter threshold */ 83#define AMD_CPUID_SVM_AVIC BIT(13) /* AVIC present */ 84 85#define VMCB_CACHE_DEFAULT (VMCB_CACHE_ASID | \ 86 VMCB_CACHE_IOPM | \ 87 VMCB_CACHE_I | \ 88 VMCB_CACHE_TPR | \ 89 VMCB_CACHE_CR2 | \ 90 VMCB_CACHE_CR | \ 91 VMCB_CACHE_DT | \ 92 VMCB_CACHE_SEG | \ 93 VMCB_CACHE_NP) 94 95static uint32_t vmcb_clean = VMCB_CACHE_DEFAULT; 96SYSCTL_INT(_hw_vmm_svm, OID_AUTO, vmcb_clean, CTLFLAG_RDTUN, &vmcb_clean, 97 0, NULL); 98 99static MALLOC_DEFINE(M_SVM, "svm", "svm"); 100static MALLOC_DEFINE(M_SVM_VLAPIC, "svm-vlapic", "svm-vlapic"); 101 102/* Per-CPU context area. */ 103extern struct pcpu __pcpu[]; 104 105static uint32_t svm_feature = ~0U; /* AMD SVM features. */ 106SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, features, CTLFLAG_RDTUN, &svm_feature, 0, 107 "SVM features advertised by CPUID.8000000AH:EDX"); 108 109static int disable_npf_assist; 110SYSCTL_INT(_hw_vmm_svm, OID_AUTO, disable_npf_assist, CTLFLAG_RWTUN, 111 &disable_npf_assist, 0, NULL); 112 113/* Maximum ASIDs supported by the processor */ 114static uint32_t nasid; 115SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, num_asids, CTLFLAG_RDTUN, &nasid, 0, 116 "Number of ASIDs supported by this processor"); 117 118/* Current ASID generation for each host cpu */ 119static struct asid asid[MAXCPU]; 120 121/* 122 * SVM host state saved area of size 4KB for each core. 123 */ 124static uint8_t hsave[MAXCPU][PAGE_SIZE] __aligned(PAGE_SIZE); 125 126static VMM_STAT_AMD(VCPU_EXITINTINFO, "VM exits during event delivery"); 127static VMM_STAT_AMD(VCPU_INTINFO_INJECTED, "Events pending at VM entry"); 128static VMM_STAT_AMD(VMEXIT_VINTR, "VM exits due to interrupt window"); 129 130static int svm_setreg(void *arg, int vcpu, int ident, uint64_t val); 131 132static __inline int 133flush_by_asid(void) 134{ 135 136 return (svm_feature & AMD_CPUID_SVM_FLUSH_BY_ASID); 137} 138 139static __inline int 140decode_assist(void) 141{ 142 143 return (svm_feature & AMD_CPUID_SVM_DECODE_ASSIST); 144} 145 146static void 147svm_disable(void *arg __unused) 148{ 149 uint64_t efer; 150 151 efer = rdmsr(MSR_EFER); 152 efer &= ~EFER_SVM; 153 wrmsr(MSR_EFER, efer); 154} 155 156/* 157 * Disable SVM on all CPUs. 158 */ 159static int 160svm_cleanup(void) 161{ 162 163 smp_rendezvous(NULL, svm_disable, NULL, NULL); 164 return (0); 165} 166 167/* 168 * Verify that all the features required by bhyve are available. 169 */ 170static int 171check_svm_features(void) 172{ 173 u_int regs[4]; 174 175 /* CPUID Fn8000_000A is for SVM */ 176 do_cpuid(0x8000000A, regs); 177 svm_feature &= regs[3]; 178 179 /* 180 * The number of ASIDs can be configured to be less than what is 181 * supported by the hardware but not more. 182 */ 183 if (nasid == 0 || nasid > regs[1]) 184 nasid = regs[1]; 185 KASSERT(nasid > 1, ("Insufficient ASIDs for guests: %#x", nasid)); 186 187 /* bhyve requires the Nested Paging feature */ 188 if (!(svm_feature & AMD_CPUID_SVM_NP)) { 189 printf("SVM: Nested Paging feature not available.\n"); 190 return (ENXIO); 191 } 192 193 /* bhyve requires the NRIP Save feature */ 194 if (!(svm_feature & AMD_CPUID_SVM_NRIP_SAVE)) { 195 printf("SVM: NRIP Save feature not available.\n"); 196 return (ENXIO); 197 } 198 199 return (0); 200} 201 202static void 203svm_enable(void *arg __unused) 204{ 205 uint64_t efer; 206 207 efer = rdmsr(MSR_EFER); 208 efer |= EFER_SVM; 209 wrmsr(MSR_EFER, efer); 210 211 wrmsr(MSR_VM_HSAVE_PA, vtophys(hsave[curcpu])); 212} 213 214/* 215 * Return 1 if SVM is enabled on this processor and 0 otherwise. 216 */ 217static int 218svm_available(void) 219{ 220 uint64_t msr; 221 222 /* Section 15.4 Enabling SVM from APM2. */ 223 if ((amd_feature2 & AMDID2_SVM) == 0) { 224 printf("SVM: not available.\n"); 225 return (0); 226 } 227 228 msr = rdmsr(MSR_VM_CR); 229 if ((msr & VM_CR_SVMDIS) != 0) { 230 printf("SVM: disabled by BIOS.\n"); 231 return (0); 232 } 233 234 return (1); 235} 236 237static int 238svm_init(int ipinum) 239{ 240 int error, cpu; 241 242 if (!svm_available()) 243 return (ENXIO); 244 245 error = check_svm_features(); 246 if (error) 247 return (error); 248 249 vmcb_clean &= VMCB_CACHE_DEFAULT; 250 251 for (cpu = 0; cpu < MAXCPU; cpu++) { 252 /* 253 * Initialize the host ASIDs to their "highest" valid values. 254 * 255 * The next ASID allocation will rollover both 'gen' and 'num' 256 * and start off the sequence at {1,1}. 257 */ 258 asid[cpu].gen = ~0UL; 259 asid[cpu].num = nasid - 1; 260 } 261 262 svm_msr_init(); 263 svm_npt_init(ipinum); 264 265 /* Enable SVM on all CPUs */ 266 smp_rendezvous(NULL, svm_enable, NULL, NULL); 267 268 return (0); 269} 270 271static void 272svm_restore(void) 273{ 274 275 svm_enable(NULL); 276} 277 278/* Pentium compatible MSRs */ 279#define MSR_PENTIUM_START 0 280#define MSR_PENTIUM_END 0x1FFF 281/* AMD 6th generation and Intel compatible MSRs */ 282#define MSR_AMD6TH_START 0xC0000000UL 283#define MSR_AMD6TH_END 0xC0001FFFUL 284/* AMD 7th and 8th generation compatible MSRs */ 285#define MSR_AMD7TH_START 0xC0010000UL 286#define MSR_AMD7TH_END 0xC0011FFFUL 287 288/* 289 * Get the index and bit position for a MSR in permission bitmap. 290 * Two bits are used for each MSR: lower bit for read and higher bit for write. 291 */ 292static int 293svm_msr_index(uint64_t msr, int *index, int *bit) 294{ 295 uint32_t base, off; 296 297 *index = -1; 298 *bit = (msr % 4) * 2; 299 base = 0; 300 301 if (msr >= MSR_PENTIUM_START && msr <= MSR_PENTIUM_END) { 302 *index = msr / 4; 303 return (0); 304 } 305 306 base += (MSR_PENTIUM_END - MSR_PENTIUM_START + 1); 307 if (msr >= MSR_AMD6TH_START && msr <= MSR_AMD6TH_END) { 308 off = (msr - MSR_AMD6TH_START); 309 *index = (off + base) / 4; 310 return (0); 311 } 312 313 base += (MSR_AMD6TH_END - MSR_AMD6TH_START + 1); 314 if (msr >= MSR_AMD7TH_START && msr <= MSR_AMD7TH_END) { 315 off = (msr - MSR_AMD7TH_START); 316 *index = (off + base) / 4; 317 return (0); 318 } 319 320 return (EINVAL); 321} 322 323/* 324 * Allow vcpu to read or write the 'msr' without trapping into the hypervisor. 325 */ 326static void 327svm_msr_perm(uint8_t *perm_bitmap, uint64_t msr, bool read, bool write) 328{ 329 int index, bit, error; 330 331 error = svm_msr_index(msr, &index, &bit); 332 KASSERT(error == 0, ("%s: invalid msr %#lx", __func__, msr)); 333 KASSERT(index >= 0 && index < SVM_MSR_BITMAP_SIZE, 334 ("%s: invalid index %d for msr %#lx", __func__, index, msr)); 335 KASSERT(bit >= 0 && bit <= 6, ("%s: invalid bit position %d " 336 "msr %#lx", __func__, bit, msr)); 337 338 if (read) 339 perm_bitmap[index] &= ~(1UL << bit); 340 341 if (write) 342 perm_bitmap[index] &= ~(2UL << bit); 343} 344 345static void 346svm_msr_rw_ok(uint8_t *perm_bitmap, uint64_t msr) 347{ 348 349 svm_msr_perm(perm_bitmap, msr, true, true); 350} 351 352static void 353svm_msr_rd_ok(uint8_t *perm_bitmap, uint64_t msr) 354{ 355 356 svm_msr_perm(perm_bitmap, msr, true, false); 357} 358 359static __inline int 360svm_get_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask) 361{ 362 struct vmcb_ctrl *ctrl; 363 364 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx)); 365 366 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 367 return (ctrl->intercept[idx] & bitmask ? 1 : 0); 368} 369 370static __inline void 371svm_set_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask, 372 int enabled) 373{ 374 struct vmcb_ctrl *ctrl; 375 uint32_t oldval; 376 377 KASSERT(idx >=0 && idx < 5, ("invalid intercept index %d", idx)); 378 379 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 380 oldval = ctrl->intercept[idx]; 381 382 if (enabled) 383 ctrl->intercept[idx] |= bitmask; 384 else 385 ctrl->intercept[idx] &= ~bitmask; 386 387 if (ctrl->intercept[idx] != oldval) { 388 svm_set_dirty(sc, vcpu, VMCB_CACHE_I); 389 VCPU_CTR3(sc->vm, vcpu, "intercept[%d] modified " 390 "from %#x to %#x", idx, oldval, ctrl->intercept[idx]); 391 } 392} 393 394static __inline void 395svm_disable_intercept(struct svm_softc *sc, int vcpu, int off, uint32_t bitmask) 396{ 397 398 svm_set_intercept(sc, vcpu, off, bitmask, 0); 399} 400 401static __inline void 402svm_enable_intercept(struct svm_softc *sc, int vcpu, int off, uint32_t bitmask) 403{ 404 405 svm_set_intercept(sc, vcpu, off, bitmask, 1); 406} 407 408static void 409vmcb_init(struct svm_softc *sc, int vcpu, uint64_t iopm_base_pa, 410 uint64_t msrpm_base_pa, uint64_t np_pml4) 411{ 412 struct vmcb_ctrl *ctrl; 413 struct vmcb_state *state; 414 uint32_t mask; 415 int n; 416 417 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 418 state = svm_get_vmcb_state(sc, vcpu); 419 420 ctrl->iopm_base_pa = iopm_base_pa; 421 ctrl->msrpm_base_pa = msrpm_base_pa; 422 423 /* Enable nested paging */ 424 ctrl->np_enable = 1; 425 ctrl->n_cr3 = np_pml4; 426 427 /* 428 * Intercept accesses to the control registers that are not shadowed 429 * in the VMCB - i.e. all except cr0, cr2, cr3, cr4 and cr8. 430 */ 431 for (n = 0; n < 16; n++) { 432 mask = (BIT(n) << 16) | BIT(n); 433 if (n == 0 || n == 2 || n == 3 || n == 4 || n == 8) 434 svm_disable_intercept(sc, vcpu, VMCB_CR_INTCPT, mask); 435 else 436 svm_enable_intercept(sc, vcpu, VMCB_CR_INTCPT, mask); 437 } 438 439 440 /* 441 * Intercept everything when tracing guest exceptions otherwise 442 * just intercept machine check exception. 443 */ 444 if (vcpu_trace_exceptions(sc->vm, vcpu)) { 445 for (n = 0; n < 32; n++) { 446 /* 447 * Skip unimplemented vectors in the exception bitmap. 448 */ 449 if (n == 2 || n == 9) { 450 continue; 451 } 452 svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(n)); 453 } 454 } else { 455 svm_enable_intercept(sc, vcpu, VMCB_EXC_INTCPT, BIT(IDT_MC)); 456 } 457 458 /* Intercept various events (for e.g. I/O, MSR and CPUID accesses) */ 459 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IO); 460 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_MSR); 461 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_CPUID); 462 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INTR); 463 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_INIT); 464 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_NMI); 465 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_SMI); 466 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_SHUTDOWN); 467 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 468 VMCB_INTCPT_FERR_FREEZE); 469 470 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_MONITOR); 471 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_MWAIT); 472 473 /* 474 * From section "Canonicalization and Consistency Checks" in APMv2 475 * the VMRUN intercept bit must be set to pass the consistency check. 476 */ 477 svm_enable_intercept(sc, vcpu, VMCB_CTRL2_INTCPT, VMCB_INTCPT_VMRUN); 478 479 /* 480 * The ASID will be set to a non-zero value just before VMRUN. 481 */ 482 ctrl->asid = 0; 483 484 /* 485 * Section 15.21.1, Interrupt Masking in EFLAGS 486 * Section 15.21.2, Virtualizing APIC.TPR 487 * 488 * This must be set for %rflag and %cr8 isolation of guest and host. 489 */ 490 ctrl->v_intr_masking = 1; 491 492 /* Enable Last Branch Record aka LBR for debugging */ 493 ctrl->lbr_virt_en = 1; 494 state->dbgctl = BIT(0); 495 496 /* EFER_SVM must always be set when the guest is executing */ 497 state->efer = EFER_SVM; 498 499 /* Set up the PAT to power-on state */ 500 state->g_pat = PAT_VALUE(0, PAT_WRITE_BACK) | 501 PAT_VALUE(1, PAT_WRITE_THROUGH) | 502 PAT_VALUE(2, PAT_UNCACHED) | 503 PAT_VALUE(3, PAT_UNCACHEABLE) | 504 PAT_VALUE(4, PAT_WRITE_BACK) | 505 PAT_VALUE(5, PAT_WRITE_THROUGH) | 506 PAT_VALUE(6, PAT_UNCACHED) | 507 PAT_VALUE(7, PAT_UNCACHEABLE); 508} 509 510/* 511 * Initialize a virtual machine. 512 */ 513static void * 514svm_vminit(struct vm *vm, pmap_t pmap) 515{ 516 struct svm_softc *svm_sc; 517 struct svm_vcpu *vcpu; 518 vm_paddr_t msrpm_pa, iopm_pa, pml4_pa; 519 int i; 520 521 svm_sc = contigmalloc(sizeof (*svm_sc), M_SVM, M_WAITOK | M_ZERO, 522 0, ~(vm_paddr_t)0, PAGE_SIZE, 0); 523 svm_sc->vm = vm; 524 svm_sc->nptp = (vm_offset_t)vtophys(pmap->pm_pml4); 525 526 /* 527 * Intercept read and write accesses to all MSRs. 528 */ 529 memset(svm_sc->msr_bitmap, 0xFF, sizeof(svm_sc->msr_bitmap)); 530 531 /* 532 * Access to the following MSRs is redirected to the VMCB when the 533 * guest is executing. Therefore it is safe to allow the guest to 534 * read/write these MSRs directly without hypervisor involvement. 535 */ 536 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_GSBASE); 537 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_FSBASE); 538 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_KGSBASE); 539 540 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_STAR); 541 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_LSTAR); 542 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_CSTAR); 543 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SF_MASK); 544 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_CS_MSR); 545 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_ESP_MSR); 546 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_SYSENTER_EIP_MSR); 547 svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_PAT); 548 549 svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_TSC); 550 551 /* 552 * Intercept writes to make sure that the EFER_SVM bit is not cleared. 553 */ 554 svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_EFER); 555 556 /* Intercept access to all I/O ports. */ 557 memset(svm_sc->iopm_bitmap, 0xFF, sizeof(svm_sc->iopm_bitmap)); 558 559 iopm_pa = vtophys(svm_sc->iopm_bitmap); 560 msrpm_pa = vtophys(svm_sc->msr_bitmap); 561 pml4_pa = svm_sc->nptp; 562 for (i = 0; i < VM_MAXCPU; i++) { 563 vcpu = svm_get_vcpu(svm_sc, i); 564 vcpu->nextrip = ~0; 565 vcpu->lastcpu = NOCPU; 566 vcpu->vmcb_pa = vtophys(&vcpu->vmcb); 567 vmcb_init(svm_sc, i, iopm_pa, msrpm_pa, pml4_pa); 568 svm_msr_guest_init(svm_sc, i); 569 } 570 return (svm_sc); 571} 572 573/* 574 * Collateral for a generic SVM VM-exit. 575 */ 576static void 577vm_exit_svm(struct vm_exit *vme, uint64_t code, uint64_t info1, uint64_t info2) 578{ 579 580 vme->exitcode = VM_EXITCODE_SVM; 581 vme->u.svm.exitcode = code; 582 vme->u.svm.exitinfo1 = info1; 583 vme->u.svm.exitinfo2 = info2; 584} 585 586static int 587svm_cpl(struct vmcb_state *state) 588{ 589 590 /* 591 * From APMv2: 592 * "Retrieve the CPL from the CPL field in the VMCB, not 593 * from any segment DPL" 594 */ 595 return (state->cpl); 596} 597 598static enum vm_cpu_mode 599svm_vcpu_mode(struct vmcb *vmcb) 600{ 601 struct vmcb_segment seg; 602 struct vmcb_state *state; 603 int error; 604 605 state = &vmcb->state; 606 607 if (state->efer & EFER_LMA) { 608 error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg); 609 KASSERT(error == 0, ("%s: vmcb_seg(cs) error %d", __func__, 610 error)); 611 612 /* 613 * Section 4.8.1 for APM2, check if Code Segment has 614 * Long attribute set in descriptor. 615 */ 616 if (seg.attrib & VMCB_CS_ATTRIB_L) 617 return (CPU_MODE_64BIT); 618 else 619 return (CPU_MODE_COMPATIBILITY); 620 } else if (state->cr0 & CR0_PE) { 621 return (CPU_MODE_PROTECTED); 622 } else { 623 return (CPU_MODE_REAL); 624 } 625} 626 627static enum vm_paging_mode 628svm_paging_mode(uint64_t cr0, uint64_t cr4, uint64_t efer) 629{ 630 631 if ((cr0 & CR0_PG) == 0) 632 return (PAGING_MODE_FLAT); 633 if ((cr4 & CR4_PAE) == 0) 634 return (PAGING_MODE_32); 635 if (efer & EFER_LME) 636 return (PAGING_MODE_64); 637 else 638 return (PAGING_MODE_PAE); 639} 640 641/* 642 * ins/outs utility routines 643 */ 644static uint64_t 645svm_inout_str_index(struct svm_regctx *regs, int in) 646{ 647 uint64_t val; 648 649 val = in ? regs->sctx_rdi : regs->sctx_rsi; 650 651 return (val); 652} 653 654static uint64_t 655svm_inout_str_count(struct svm_regctx *regs, int rep) 656{ 657 uint64_t val; 658 659 val = rep ? regs->sctx_rcx : 1; 660 661 return (val); 662} 663 664static void 665svm_inout_str_seginfo(struct svm_softc *svm_sc, int vcpu, int64_t info1, 666 int in, struct vm_inout_str *vis) 667{ 668 int error, s; 669 670 if (in) { 671 vis->seg_name = VM_REG_GUEST_ES; 672 } else { 673 /* The segment field has standard encoding */ 674 s = (info1 >> 10) & 0x7; 675 vis->seg_name = vm_segment_name(s); 676 } 677 678 error = vmcb_getdesc(svm_sc, vcpu, vis->seg_name, &vis->seg_desc); 679 KASSERT(error == 0, ("%s: svm_getdesc error %d", __func__, error)); 680} 681 682static int 683svm_inout_str_addrsize(uint64_t info1) 684{ 685 uint32_t size; 686 687 size = (info1 >> 7) & 0x7; 688 switch (size) { 689 case 1: 690 return (2); /* 16 bit */ 691 case 2: 692 return (4); /* 32 bit */ 693 case 4: 694 return (8); /* 64 bit */ 695 default: 696 panic("%s: invalid size encoding %d", __func__, size); 697 } 698} 699 700static void 701svm_paging_info(struct vmcb *vmcb, struct vm_guest_paging *paging) 702{ 703 struct vmcb_state *state; 704 705 state = &vmcb->state; 706 paging->cr3 = state->cr3; 707 paging->cpl = svm_cpl(state); 708 paging->cpu_mode = svm_vcpu_mode(vmcb); 709 paging->paging_mode = svm_paging_mode(state->cr0, state->cr4, 710 state->efer); 711} 712 713#define UNHANDLED 0 714 715/* 716 * Handle guest I/O intercept. 717 */ 718static int 719svm_handle_io(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit) 720{ 721 struct vmcb_ctrl *ctrl; 722 struct vmcb_state *state; 723 struct svm_regctx *regs; 724 struct vm_inout_str *vis; 725 uint64_t info1; 726 int inout_string; 727 728 state = svm_get_vmcb_state(svm_sc, vcpu); 729 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu); 730 regs = svm_get_guest_regctx(svm_sc, vcpu); 731 732 info1 = ctrl->exitinfo1; 733 inout_string = info1 & BIT(2) ? 1 : 0; 734 735 /* 736 * The effective segment number in EXITINFO1[12:10] is populated 737 * only if the processor has the DecodeAssist capability. 738 * 739 * XXX this is not specified explicitly in APMv2 but can be verified 740 * empirically. 741 */ 742 if (inout_string && !decode_assist()) 743 return (UNHANDLED); 744 745 vmexit->exitcode = VM_EXITCODE_INOUT; 746 vmexit->u.inout.in = (info1 & BIT(0)) ? 1 : 0; 747 vmexit->u.inout.string = inout_string; 748 vmexit->u.inout.rep = (info1 & BIT(3)) ? 1 : 0; 749 vmexit->u.inout.bytes = (info1 >> 4) & 0x7; 750 vmexit->u.inout.port = (uint16_t)(info1 >> 16); 751 vmexit->u.inout.eax = (uint32_t)(state->rax); 752 753 if (inout_string) { 754 vmexit->exitcode = VM_EXITCODE_INOUT_STR; 755 vis = &vmexit->u.inout_str; 756 svm_paging_info(svm_get_vmcb(svm_sc, vcpu), &vis->paging); 757 vis->rflags = state->rflags; 758 vis->cr0 = state->cr0; 759 vis->index = svm_inout_str_index(regs, vmexit->u.inout.in); 760 vis->count = svm_inout_str_count(regs, vmexit->u.inout.rep); 761 vis->addrsize = svm_inout_str_addrsize(info1); 762 svm_inout_str_seginfo(svm_sc, vcpu, info1, 763 vmexit->u.inout.in, vis); 764 } 765 766 return (UNHANDLED); 767} 768 769static int 770npf_fault_type(uint64_t exitinfo1) 771{ 772 773 if (exitinfo1 & VMCB_NPF_INFO1_W) 774 return (VM_PROT_WRITE); 775 else if (exitinfo1 & VMCB_NPF_INFO1_ID) 776 return (VM_PROT_EXECUTE); 777 else 778 return (VM_PROT_READ); 779} 780 781static bool 782svm_npf_emul_fault(uint64_t exitinfo1) 783{ 784 785 if (exitinfo1 & VMCB_NPF_INFO1_ID) { 786 return (false); 787 } 788 789 if (exitinfo1 & VMCB_NPF_INFO1_GPT) { 790 return (false); 791 } 792 793 if ((exitinfo1 & VMCB_NPF_INFO1_GPA) == 0) { 794 return (false); 795 } 796 797 return (true); 798} 799 800static void 801svm_handle_inst_emul(struct vmcb *vmcb, uint64_t gpa, struct vm_exit *vmexit) 802{ 803 struct vm_guest_paging *paging; 804 struct vmcb_segment seg; 805 struct vmcb_ctrl *ctrl; 806 char *inst_bytes; 807 int error, inst_len; 808 809 ctrl = &vmcb->ctrl; 810 paging = &vmexit->u.inst_emul.paging; 811 812 vmexit->exitcode = VM_EXITCODE_INST_EMUL; 813 vmexit->u.inst_emul.gpa = gpa; 814 vmexit->u.inst_emul.gla = VIE_INVALID_GLA; 815 svm_paging_info(vmcb, paging); 816 817 error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg); 818 KASSERT(error == 0, ("%s: vmcb_seg(CS) error %d", __func__, error)); 819 820 switch(paging->cpu_mode) { 821 case CPU_MODE_REAL: 822 vmexit->u.inst_emul.cs_base = seg.base; 823 vmexit->u.inst_emul.cs_d = 0; 824 break; 825 case CPU_MODE_PROTECTED: 826 case CPU_MODE_COMPATIBILITY: 827 vmexit->u.inst_emul.cs_base = seg.base; 828 829 /* 830 * Section 4.8.1 of APM2, Default Operand Size or D bit. 831 */ 832 vmexit->u.inst_emul.cs_d = (seg.attrib & VMCB_CS_ATTRIB_D) ? 833 1 : 0; 834 break; 835 default: 836 vmexit->u.inst_emul.cs_base = 0; 837 vmexit->u.inst_emul.cs_d = 0; 838 break; 839 } 840 841 /* 842 * Copy the instruction bytes into 'vie' if available. 843 */ 844 if (decode_assist() && !disable_npf_assist) { 845 inst_len = ctrl->inst_len; 846 inst_bytes = ctrl->inst_bytes; 847 } else { 848 inst_len = 0; 849 inst_bytes = NULL; 850 } 851 vie_init(&vmexit->u.inst_emul.vie, inst_bytes, inst_len); 852} 853 854#ifdef KTR 855static const char * 856intrtype_to_str(int intr_type) 857{ 858 switch (intr_type) { 859 case VMCB_EVENTINJ_TYPE_INTR: 860 return ("hwintr"); 861 case VMCB_EVENTINJ_TYPE_NMI: 862 return ("nmi"); 863 case VMCB_EVENTINJ_TYPE_INTn: 864 return ("swintr"); 865 case VMCB_EVENTINJ_TYPE_EXCEPTION: 866 return ("exception"); 867 default: 868 panic("%s: unknown intr_type %d", __func__, intr_type); 869 } 870} 871#endif 872 873/* 874 * Inject an event to vcpu as described in section 15.20, "Event injection". 875 */ 876static void 877svm_eventinject(struct svm_softc *sc, int vcpu, int intr_type, int vector, 878 uint32_t error, bool ec_valid) 879{ 880 struct vmcb_ctrl *ctrl; 881 882 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 883 884 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, 885 ("%s: event already pending %#lx", __func__, ctrl->eventinj)); 886 887 KASSERT(vector >=0 && vector <= 255, ("%s: invalid vector %d", 888 __func__, vector)); 889 890 switch (intr_type) { 891 case VMCB_EVENTINJ_TYPE_INTR: 892 case VMCB_EVENTINJ_TYPE_NMI: 893 case VMCB_EVENTINJ_TYPE_INTn: 894 break; 895 case VMCB_EVENTINJ_TYPE_EXCEPTION: 896 if (vector >= 0 && vector <= 31 && vector != 2) 897 break; 898 /* FALLTHROUGH */ 899 default: 900 panic("%s: invalid intr_type/vector: %d/%d", __func__, 901 intr_type, vector); 902 } 903 ctrl->eventinj = vector | (intr_type << 8) | VMCB_EVENTINJ_VALID; 904 if (ec_valid) { 905 ctrl->eventinj |= VMCB_EVENTINJ_EC_VALID; 906 ctrl->eventinj |= (uint64_t)error << 32; 907 VCPU_CTR3(sc->vm, vcpu, "Injecting %s at vector %d errcode %#x", 908 intrtype_to_str(intr_type), vector, error); 909 } else { 910 VCPU_CTR2(sc->vm, vcpu, "Injecting %s at vector %d", 911 intrtype_to_str(intr_type), vector); 912 } 913} 914 915static void 916svm_update_virqinfo(struct svm_softc *sc, int vcpu) 917{ 918 struct vm *vm; 919 struct vlapic *vlapic; 920 struct vmcb_ctrl *ctrl; 921 int pending; 922 923 vm = sc->vm; 924 vlapic = vm_lapic(vm, vcpu); 925 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 926 927 /* Update %cr8 in the emulated vlapic */ 928 vlapic_set_cr8(vlapic, ctrl->v_tpr); 929 930 /* 931 * If V_IRQ indicates that the interrupt injection attempted on then 932 * last VMRUN was successful then update the vlapic accordingly. 933 */ 934 if (ctrl->v_intr_vector != 0) { 935 pending = ctrl->v_irq; 936 KASSERT(ctrl->v_intr_vector >= 16, ("%s: invalid " 937 "v_intr_vector %d", __func__, ctrl->v_intr_vector)); 938 KASSERT(!ctrl->v_ign_tpr, ("%s: invalid v_ign_tpr", __func__)); 939 VCPU_CTR2(vm, vcpu, "v_intr_vector %d %s", ctrl->v_intr_vector, 940 pending ? "pending" : "accepted"); 941 if (!pending) 942 vlapic_intr_accepted(vlapic, ctrl->v_intr_vector); 943 } 944} 945 946static void 947svm_save_intinfo(struct svm_softc *svm_sc, int vcpu) 948{ 949 struct vmcb_ctrl *ctrl; 950 uint64_t intinfo; 951 952 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu); 953 intinfo = ctrl->exitintinfo; 954 if (!VMCB_EXITINTINFO_VALID(intinfo)) 955 return; 956 957 /* 958 * From APMv2, Section "Intercepts during IDT interrupt delivery" 959 * 960 * If a #VMEXIT happened during event delivery then record the event 961 * that was being delivered. 962 */ 963 VCPU_CTR2(svm_sc->vm, vcpu, "SVM:Pending INTINFO(0x%lx), vector=%d.\n", 964 intinfo, VMCB_EXITINTINFO_VECTOR(intinfo)); 965 vmm_stat_incr(svm_sc->vm, vcpu, VCPU_EXITINTINFO, 1); 966 vm_exit_intinfo(svm_sc->vm, vcpu, intinfo); 967} 968 969static __inline int 970vintr_intercept_enabled(struct svm_softc *sc, int vcpu) 971{ 972 973 return (svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 974 VMCB_INTCPT_VINTR)); 975} 976 977static __inline void 978enable_intr_window_exiting(struct svm_softc *sc, int vcpu) 979{ 980 struct vmcb_ctrl *ctrl; 981 982 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 983 984 if (ctrl->v_irq && ctrl->v_intr_vector == 0) { 985 KASSERT(ctrl->v_ign_tpr, ("%s: invalid v_ign_tpr", __func__)); 986 KASSERT(vintr_intercept_enabled(sc, vcpu), 987 ("%s: vintr intercept should be enabled", __func__)); 988 return; 989 } 990 991 VCPU_CTR0(sc->vm, vcpu, "Enable intr window exiting"); 992 ctrl->v_irq = 1; 993 ctrl->v_ign_tpr = 1; 994 ctrl->v_intr_vector = 0; 995 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 996 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR); 997} 998 999static __inline void 1000disable_intr_window_exiting(struct svm_softc *sc, int vcpu) 1001{ 1002 struct vmcb_ctrl *ctrl; 1003 1004 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 1005 1006 if (!ctrl->v_irq && ctrl->v_intr_vector == 0) { 1007 KASSERT(!vintr_intercept_enabled(sc, vcpu), 1008 ("%s: vintr intercept should be disabled", __func__)); 1009 return; 1010 } 1011 1012#ifdef KTR 1013 if (ctrl->v_intr_vector == 0) 1014 VCPU_CTR0(sc->vm, vcpu, "Disable intr window exiting"); 1015 else 1016 VCPU_CTR0(sc->vm, vcpu, "Clearing V_IRQ interrupt injection"); 1017#endif 1018 ctrl->v_irq = 0; 1019 ctrl->v_intr_vector = 0; 1020 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 1021 svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR); 1022} 1023 1024static int 1025svm_modify_intr_shadow(struct svm_softc *sc, int vcpu, uint64_t val) 1026{ 1027 struct vmcb_ctrl *ctrl; 1028 int oldval, newval; 1029 1030 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 1031 oldval = ctrl->intr_shadow; 1032 newval = val ? 1 : 0; 1033 if (newval != oldval) { 1034 ctrl->intr_shadow = newval; 1035 VCPU_CTR1(sc->vm, vcpu, "Setting intr_shadow to %d", newval); 1036 } 1037 return (0); 1038} 1039 1040static int 1041svm_get_intr_shadow(struct svm_softc *sc, int vcpu, uint64_t *val) 1042{ 1043 struct vmcb_ctrl *ctrl; 1044 1045 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 1046 *val = ctrl->intr_shadow; 1047 return (0); 1048} 1049 1050/* 1051 * Once an NMI is injected it blocks delivery of further NMIs until the handler 1052 * executes an IRET. The IRET intercept is enabled when an NMI is injected to 1053 * to track when the vcpu is done handling the NMI. 1054 */ 1055static int 1056nmi_blocked(struct svm_softc *sc, int vcpu) 1057{ 1058 int blocked; 1059 1060 blocked = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 1061 VMCB_INTCPT_IRET); 1062 return (blocked); 1063} 1064 1065static void 1066enable_nmi_blocking(struct svm_softc *sc, int vcpu) 1067{ 1068 1069 KASSERT(!nmi_blocked(sc, vcpu), ("vNMI already blocked")); 1070 VCPU_CTR0(sc->vm, vcpu, "vNMI blocking enabled"); 1071 svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IRET); 1072} 1073 1074static void 1075clear_nmi_blocking(struct svm_softc *sc, int vcpu) 1076{ 1077 int error; 1078 1079 KASSERT(nmi_blocked(sc, vcpu), ("vNMI already unblocked")); 1080 VCPU_CTR0(sc->vm, vcpu, "vNMI blocking cleared"); 1081 /* 1082 * When the IRET intercept is cleared the vcpu will attempt to execute 1083 * the "iret" when it runs next. However, it is possible to inject 1084 * another NMI into the vcpu before the "iret" has actually executed. 1085 * 1086 * For e.g. if the "iret" encounters a #NPF when accessing the stack 1087 * it will trap back into the hypervisor. If an NMI is pending for 1088 * the vcpu it will be injected into the guest. 1089 * 1090 * XXX this needs to be fixed 1091 */ 1092 svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_IRET); 1093 1094 /* 1095 * Set 'intr_shadow' to prevent an NMI from being injected on the 1096 * immediate VMRUN. 1097 */ 1098 error = svm_modify_intr_shadow(sc, vcpu, 1); 1099 KASSERT(!error, ("%s: error %d setting intr_shadow", __func__, error)); 1100} 1101 1102#define EFER_MBZ_BITS 0xFFFFFFFFFFFF0200UL 1103 1104static int 1105svm_write_efer(struct svm_softc *sc, int vcpu, uint64_t newval, bool *retu) 1106{ 1107 struct vm_exit *vme; 1108 struct vmcb_state *state; 1109 uint64_t changed, lma, oldval; 1110 int error; 1111 1112 state = svm_get_vmcb_state(sc, vcpu); 1113 1114 oldval = state->efer; 1115 VCPU_CTR2(sc->vm, vcpu, "wrmsr(efer) %#lx/%#lx", oldval, newval); 1116 1117 newval &= ~0xFE; /* clear the Read-As-Zero (RAZ) bits */ 1118 changed = oldval ^ newval; 1119 1120 if (newval & EFER_MBZ_BITS) 1121 goto gpf; 1122 1123 /* APMv2 Table 14-5 "Long-Mode Consistency Checks" */ 1124 if (changed & EFER_LME) { 1125 if (state->cr0 & CR0_PG) 1126 goto gpf; 1127 } 1128 1129 /* EFER.LMA = EFER.LME & CR0.PG */ 1130 if ((newval & EFER_LME) != 0 && (state->cr0 & CR0_PG) != 0) 1131 lma = EFER_LMA; 1132 else 1133 lma = 0; 1134 1135 if ((newval & EFER_LMA) != lma) 1136 goto gpf; 1137 1138 if (newval & EFER_NXE) { 1139 if (!vm_cpuid_capability(sc->vm, vcpu, VCC_NO_EXECUTE)) 1140 goto gpf; 1141 } 1142 1143 /* 1144 * XXX bhyve does not enforce segment limits in 64-bit mode. Until 1145 * this is fixed flag guest attempt to set EFER_LMSLE as an error. 1146 */ 1147 if (newval & EFER_LMSLE) { 1148 vme = vm_exitinfo(sc->vm, vcpu); 1149 vm_exit_svm(vme, VMCB_EXIT_MSR, 1, 0); 1150 *retu = true; 1151 return (0); 1152 } 1153 1154 if (newval & EFER_FFXSR) { 1155 if (!vm_cpuid_capability(sc->vm, vcpu, VCC_FFXSR)) 1156 goto gpf; 1157 } 1158 1159 if (newval & EFER_TCE) { 1160 if (!vm_cpuid_capability(sc->vm, vcpu, VCC_TCE)) 1161 goto gpf; 1162 } 1163 1164 error = svm_setreg(sc, vcpu, VM_REG_GUEST_EFER, newval); 1165 KASSERT(error == 0, ("%s: error %d updating efer", __func__, error)); 1166 return (0); 1167gpf: 1168 vm_inject_gp(sc->vm, vcpu); 1169 return (0); 1170} 1171 1172static int 1173emulate_wrmsr(struct svm_softc *sc, int vcpu, u_int num, uint64_t val, 1174 bool *retu) 1175{ 1176 int error; 1177 1178 if (lapic_msr(num)) 1179 error = lapic_wrmsr(sc->vm, vcpu, num, val, retu); 1180 else if (num == MSR_EFER) 1181 error = svm_write_efer(sc, vcpu, val, retu); 1182 else 1183 error = svm_wrmsr(sc, vcpu, num, val, retu); 1184 1185 return (error); 1186} 1187 1188static int 1189emulate_rdmsr(struct svm_softc *sc, int vcpu, u_int num, bool *retu) 1190{ 1191 struct vmcb_state *state; 1192 struct svm_regctx *ctx; 1193 uint64_t result; 1194 int error; 1195 1196 if (lapic_msr(num)) 1197 error = lapic_rdmsr(sc->vm, vcpu, num, &result, retu); 1198 else 1199 error = svm_rdmsr(sc, vcpu, num, &result, retu); 1200 1201 if (error == 0) { 1202 state = svm_get_vmcb_state(sc, vcpu); 1203 ctx = svm_get_guest_regctx(sc, vcpu); 1204 state->rax = result & 0xffffffff; 1205 ctx->sctx_rdx = result >> 32; 1206 } 1207 1208 return (error); 1209} 1210 1211#ifdef KTR 1212static const char * 1213exit_reason_to_str(uint64_t reason) 1214{ 1215 static char reasonbuf[32]; 1216 1217 switch (reason) { 1218 case VMCB_EXIT_INVALID: 1219 return ("invalvmcb"); 1220 case VMCB_EXIT_SHUTDOWN: 1221 return ("shutdown"); 1222 case VMCB_EXIT_NPF: 1223 return ("nptfault"); 1224 case VMCB_EXIT_PAUSE: 1225 return ("pause"); 1226 case VMCB_EXIT_HLT: 1227 return ("hlt"); 1228 case VMCB_EXIT_CPUID: 1229 return ("cpuid"); 1230 case VMCB_EXIT_IO: 1231 return ("inout"); 1232 case VMCB_EXIT_MC: 1233 return ("mchk"); 1234 case VMCB_EXIT_INTR: 1235 return ("extintr"); 1236 case VMCB_EXIT_NMI: 1237 return ("nmi"); 1238 case VMCB_EXIT_VINTR: 1239 return ("vintr"); 1240 case VMCB_EXIT_MSR: 1241 return ("msr"); 1242 case VMCB_EXIT_IRET: 1243 return ("iret"); 1244 case VMCB_EXIT_MONITOR: 1245 return ("monitor"); 1246 case VMCB_EXIT_MWAIT: 1247 return ("mwait"); 1248 default: 1249 snprintf(reasonbuf, sizeof(reasonbuf), "%#lx", reason); 1250 return (reasonbuf); 1251 } 1252} 1253#endif /* KTR */ 1254 1255/* 1256 * From section "State Saved on Exit" in APMv2: nRIP is saved for all #VMEXITs 1257 * that are due to instruction intercepts as well as MSR and IOIO intercepts 1258 * and exceptions caused by INT3, INTO and BOUND instructions. 1259 * 1260 * Return 1 if the nRIP is valid and 0 otherwise. 1261 */ 1262static int 1263nrip_valid(uint64_t exitcode) 1264{ 1265 switch (exitcode) { 1266 case 0x00 ... 0x0F: /* read of CR0 through CR15 */ 1267 case 0x10 ... 0x1F: /* write of CR0 through CR15 */ 1268 case 0x20 ... 0x2F: /* read of DR0 through DR15 */ 1269 case 0x30 ... 0x3F: /* write of DR0 through DR15 */ 1270 case 0x43: /* INT3 */ 1271 case 0x44: /* INTO */ 1272 case 0x45: /* BOUND */ 1273 case 0x65 ... 0x7C: /* VMEXIT_CR0_SEL_WRITE ... VMEXIT_MSR */ 1274 case 0x80 ... 0x8D: /* VMEXIT_VMRUN ... VMEXIT_XSETBV */ 1275 return (1); 1276 default: 1277 return (0); 1278 } 1279} 1280 1281static int 1282svm_vmexit(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit) 1283{ 1284 struct vmcb *vmcb; 1285 struct vmcb_state *state; 1286 struct vmcb_ctrl *ctrl; 1287 struct svm_regctx *ctx; 1288 uint64_t code, info1, info2, val; 1289 uint32_t eax, ecx, edx; 1290 int error, errcode_valid, handled, idtvec, reflect; 1291 bool retu; 1292 1293 ctx = svm_get_guest_regctx(svm_sc, vcpu); 1294 vmcb = svm_get_vmcb(svm_sc, vcpu); 1295 state = &vmcb->state; 1296 ctrl = &vmcb->ctrl; 1297 1298 handled = 0; 1299 code = ctrl->exitcode; 1300 info1 = ctrl->exitinfo1; 1301 info2 = ctrl->exitinfo2; 1302 1303 vmexit->exitcode = VM_EXITCODE_BOGUS; 1304 vmexit->rip = state->rip; 1305 vmexit->inst_length = nrip_valid(code) ? ctrl->nrip - state->rip : 0; 1306 1307 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_COUNT, 1); 1308 1309 /* 1310 * #VMEXIT(INVALID) needs to be handled early because the VMCB is 1311 * in an inconsistent state and can trigger assertions that would 1312 * never happen otherwise. 1313 */ 1314 if (code == VMCB_EXIT_INVALID) { 1315 vm_exit_svm(vmexit, code, info1, info2); 1316 return (0); 1317 } 1318 1319 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) == 0, ("%s: event " 1320 "injection valid bit is set %#lx", __func__, ctrl->eventinj)); 1321 1322 KASSERT(vmexit->inst_length >= 0 && vmexit->inst_length <= 15, 1323 ("invalid inst_length %d: code (%#lx), info1 (%#lx), info2 (%#lx)", 1324 vmexit->inst_length, code, info1, info2)); 1325 1326 svm_update_virqinfo(svm_sc, vcpu); 1327 svm_save_intinfo(svm_sc, vcpu); 1328 1329 switch (code) { 1330 case VMCB_EXIT_IRET: 1331 /* 1332 * Restart execution at "iret" but with the intercept cleared. 1333 */ 1334 vmexit->inst_length = 0; 1335 clear_nmi_blocking(svm_sc, vcpu); 1336 handled = 1; 1337 break; 1338 case VMCB_EXIT_VINTR: /* interrupt window exiting */ 1339 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_VINTR, 1); 1340 handled = 1; 1341 break; 1342 case VMCB_EXIT_INTR: /* external interrupt */ 1343 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_EXTINT, 1); 1344 handled = 1; 1345 break; 1346 case VMCB_EXIT_NMI: /* external NMI */ 1347 handled = 1; 1348 break; 1349 case 0x40 ... 0x5F: 1350 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_EXCEPTION, 1); 1351 reflect = 1; 1352 idtvec = code - 0x40; 1353 switch (idtvec) { 1354 case IDT_MC: 1355 /* 1356 * Call the machine check handler by hand. Also don't 1357 * reflect the machine check back into the guest. 1358 */ 1359 reflect = 0; 1360 VCPU_CTR0(svm_sc->vm, vcpu, "Vectoring to MCE handler"); 1361 __asm __volatile("int $18"); 1362 break; 1363 case IDT_PF: 1364 error = svm_setreg(svm_sc, vcpu, VM_REG_GUEST_CR2, 1365 info2); 1366 KASSERT(error == 0, ("%s: error %d updating cr2", 1367 __func__, error)); 1368 /* fallthru */ 1369 case IDT_NP: 1370 case IDT_SS: 1371 case IDT_GP: 1372 case IDT_AC: 1373 case IDT_TS: 1374 errcode_valid = 1; 1375 break; 1376 1377 case IDT_DF: 1378 errcode_valid = 1; 1379 info1 = 0; 1380 break; 1381 1382 case IDT_BP: 1383 case IDT_OF: 1384 case IDT_BR: 1385 /* 1386 * The 'nrip' field is populated for INT3, INTO and 1387 * BOUND exceptions and this also implies that 1388 * 'inst_length' is non-zero. 1389 * 1390 * Reset 'inst_length' to zero so the guest %rip at 1391 * event injection is identical to what it was when 1392 * the exception originally happened. 1393 */ 1394 VCPU_CTR2(svm_sc->vm, vcpu, "Reset inst_length from %d " 1395 "to zero before injecting exception %d", 1396 vmexit->inst_length, idtvec); 1397 vmexit->inst_length = 0; 1398 /* fallthru */ 1399 default: 1400 errcode_valid = 0; 1401 info1 = 0; 1402 break; 1403 } 1404 KASSERT(vmexit->inst_length == 0, ("invalid inst_length (%d) " 1405 "when reflecting exception %d into guest", 1406 vmexit->inst_length, idtvec)); 1407 1408 if (reflect) { 1409 /* Reflect the exception back into the guest */ 1410 VCPU_CTR2(svm_sc->vm, vcpu, "Reflecting exception " 1411 "%d/%#x into the guest", idtvec, (int)info1); 1412 error = vm_inject_exception(svm_sc->vm, vcpu, idtvec, 1413 errcode_valid, info1, 0); 1414 KASSERT(error == 0, ("%s: vm_inject_exception error %d", 1415 __func__, error)); 1416 } 1417 handled = 1; 1418 break; 1419 case VMCB_EXIT_MSR: /* MSR access. */ 1420 eax = state->rax; 1421 ecx = ctx->sctx_rcx; 1422 edx = ctx->sctx_rdx; 1423 retu = false; 1424 1425 if (info1) { 1426 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_WRMSR, 1); 1427 val = (uint64_t)edx << 32 | eax; 1428 VCPU_CTR2(svm_sc->vm, vcpu, "wrmsr %#x val %#lx", 1429 ecx, val); 1430 if (emulate_wrmsr(svm_sc, vcpu, ecx, val, &retu)) { 1431 vmexit->exitcode = VM_EXITCODE_WRMSR; 1432 vmexit->u.msr.code = ecx; 1433 vmexit->u.msr.wval = val; 1434 } else if (!retu) { 1435 handled = 1; 1436 } else { 1437 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS, 1438 ("emulate_wrmsr retu with bogus exitcode")); 1439 } 1440 } else { 1441 VCPU_CTR1(svm_sc->vm, vcpu, "rdmsr %#x", ecx); 1442 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_RDMSR, 1); 1443 if (emulate_rdmsr(svm_sc, vcpu, ecx, &retu)) { 1444 vmexit->exitcode = VM_EXITCODE_RDMSR; 1445 vmexit->u.msr.code = ecx; 1446 } else if (!retu) { 1447 handled = 1; 1448 } else { 1449 KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS, 1450 ("emulate_rdmsr retu with bogus exitcode")); 1451 } 1452 } 1453 break; 1454 case VMCB_EXIT_IO: 1455 handled = svm_handle_io(svm_sc, vcpu, vmexit); 1456 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_INOUT, 1); 1457 break; 1458 case VMCB_EXIT_CPUID: 1459 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_CPUID, 1); 1460 handled = x86_emulate_cpuid(svm_sc->vm, vcpu, 1461 (uint32_t *)&state->rax, 1462 (uint32_t *)&ctx->sctx_rbx, 1463 (uint32_t *)&ctx->sctx_rcx, 1464 (uint32_t *)&ctx->sctx_rdx); 1465 break; 1466 case VMCB_EXIT_HLT: 1467 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_HLT, 1); 1468 vmexit->exitcode = VM_EXITCODE_HLT; 1469 vmexit->u.hlt.rflags = state->rflags; 1470 break; 1471 case VMCB_EXIT_PAUSE: 1472 vmexit->exitcode = VM_EXITCODE_PAUSE; 1473 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_PAUSE, 1); 1474 break; 1475 case VMCB_EXIT_NPF: 1476 /* EXITINFO2 contains the faulting guest physical address */ 1477 if (info1 & VMCB_NPF_INFO1_RSV) { 1478 VCPU_CTR2(svm_sc->vm, vcpu, "nested page fault with " 1479 "reserved bits set: info1(%#lx) info2(%#lx)", 1480 info1, info2); 1481 } else if (vm_mem_allocated(svm_sc->vm, vcpu, info2)) { 1482 vmexit->exitcode = VM_EXITCODE_PAGING; 1483 vmexit->u.paging.gpa = info2; 1484 vmexit->u.paging.fault_type = npf_fault_type(info1); 1485 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_NESTED_FAULT, 1); 1486 VCPU_CTR3(svm_sc->vm, vcpu, "nested page fault " 1487 "on gpa %#lx/%#lx at rip %#lx", 1488 info2, info1, state->rip); 1489 } else if (svm_npf_emul_fault(info1)) { 1490 svm_handle_inst_emul(vmcb, info2, vmexit); 1491 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_INST_EMUL, 1); 1492 VCPU_CTR3(svm_sc->vm, vcpu, "inst_emul fault " 1493 "for gpa %#lx/%#lx at rip %#lx", 1494 info2, info1, state->rip); 1495 } 1496 break; 1497 case VMCB_EXIT_MONITOR: 1498 vmexit->exitcode = VM_EXITCODE_MONITOR; 1499 break; 1500 case VMCB_EXIT_MWAIT: 1501 vmexit->exitcode = VM_EXITCODE_MWAIT; 1502 break; 1503 default: 1504 vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_UNKNOWN, 1); 1505 break; 1506 } 1507 1508 VCPU_CTR4(svm_sc->vm, vcpu, "%s %s vmexit at %#lx/%d", 1509 handled ? "handled" : "unhandled", exit_reason_to_str(code), 1510 vmexit->rip, vmexit->inst_length); 1511 1512 if (handled) { 1513 vmexit->rip += vmexit->inst_length; 1514 vmexit->inst_length = 0; 1515 state->rip = vmexit->rip; 1516 } else { 1517 if (vmexit->exitcode == VM_EXITCODE_BOGUS) { 1518 /* 1519 * If this VM exit was not claimed by anybody then 1520 * treat it as a generic SVM exit. 1521 */ 1522 vm_exit_svm(vmexit, code, info1, info2); 1523 } else { 1524 /* 1525 * The exitcode and collateral have been populated. 1526 * The VM exit will be processed further in userland. 1527 */ 1528 } 1529 } 1530 return (handled); 1531} 1532 1533static void 1534svm_inj_intinfo(struct svm_softc *svm_sc, int vcpu) 1535{ 1536 uint64_t intinfo; 1537 1538 if (!vm_entry_intinfo(svm_sc->vm, vcpu, &intinfo)) 1539 return; 1540 1541 KASSERT(VMCB_EXITINTINFO_VALID(intinfo), ("%s: entry intinfo is not " 1542 "valid: %#lx", __func__, intinfo)); 1543 1544 svm_eventinject(svm_sc, vcpu, VMCB_EXITINTINFO_TYPE(intinfo), 1545 VMCB_EXITINTINFO_VECTOR(intinfo), 1546 VMCB_EXITINTINFO_EC(intinfo), 1547 VMCB_EXITINTINFO_EC_VALID(intinfo)); 1548 vmm_stat_incr(svm_sc->vm, vcpu, VCPU_INTINFO_INJECTED, 1); 1549 VCPU_CTR1(svm_sc->vm, vcpu, "Injected entry intinfo: %#lx", intinfo); 1550} 1551 1552/* 1553 * Inject event to virtual cpu. 1554 */ 1555static void 1556svm_inj_interrupts(struct svm_softc *sc, int vcpu, struct vlapic *vlapic) 1557{ 1558 struct vmcb_ctrl *ctrl; 1559 struct vmcb_state *state; 1560 struct svm_vcpu *vcpustate; 1561 uint8_t v_tpr; 1562 int vector, need_intr_window, pending_apic_vector; 1563 1564 state = svm_get_vmcb_state(sc, vcpu); 1565 ctrl = svm_get_vmcb_ctrl(sc, vcpu); 1566 vcpustate = svm_get_vcpu(sc, vcpu); 1567 1568 need_intr_window = 0; 1569 pending_apic_vector = 0; 1570 1571 if (vcpustate->nextrip != state->rip) { 1572 ctrl->intr_shadow = 0; 1573 VCPU_CTR2(sc->vm, vcpu, "Guest interrupt blocking " 1574 "cleared due to rip change: %#lx/%#lx", 1575 vcpustate->nextrip, state->rip); 1576 } 1577 1578 /* 1579 * Inject pending events or exceptions for this vcpu. 1580 * 1581 * An event might be pending because the previous #VMEXIT happened 1582 * during event delivery (i.e. ctrl->exitintinfo). 1583 * 1584 * An event might also be pending because an exception was injected 1585 * by the hypervisor (e.g. #PF during instruction emulation). 1586 */ 1587 svm_inj_intinfo(sc, vcpu); 1588 1589 /* NMI event has priority over interrupts. */ 1590 if (vm_nmi_pending(sc->vm, vcpu)) { 1591 if (nmi_blocked(sc, vcpu)) { 1592 /* 1593 * Can't inject another NMI if the guest has not 1594 * yet executed an "iret" after the last NMI. 1595 */ 1596 VCPU_CTR0(sc->vm, vcpu, "Cannot inject NMI due " 1597 "to NMI-blocking"); 1598 } else if (ctrl->intr_shadow) { 1599 /* 1600 * Can't inject an NMI if the vcpu is in an intr_shadow. 1601 */ 1602 VCPU_CTR0(sc->vm, vcpu, "Cannot inject NMI due to " 1603 "interrupt shadow"); 1604 need_intr_window = 1; 1605 goto done; 1606 } else if (ctrl->eventinj & VMCB_EVENTINJ_VALID) { 1607 /* 1608 * If there is already an exception/interrupt pending 1609 * then defer the NMI until after that. 1610 */ 1611 VCPU_CTR1(sc->vm, vcpu, "Cannot inject NMI due to " 1612 "eventinj %#lx", ctrl->eventinj); 1613 1614 /* 1615 * Use self-IPI to trigger a VM-exit as soon as 1616 * possible after the event injection is completed. 1617 * 1618 * This works only if the external interrupt exiting 1619 * is at a lower priority than the event injection. 1620 * 1621 * Although not explicitly specified in APMv2 the 1622 * relative priorities were verified empirically. 1623 */ 1624 ipi_cpu(curcpu, IPI_AST); /* XXX vmm_ipinum? */ 1625 } else { 1626 vm_nmi_clear(sc->vm, vcpu); 1627 1628 /* Inject NMI, vector number is not used */ 1629 svm_eventinject(sc, vcpu, VMCB_EVENTINJ_TYPE_NMI, 1630 IDT_NMI, 0, false); 1631 1632 /* virtual NMI blocking is now in effect */ 1633 enable_nmi_blocking(sc, vcpu); 1634 1635 VCPU_CTR0(sc->vm, vcpu, "Injecting vNMI"); 1636 } 1637 } 1638 1639 if (!vm_extint_pending(sc->vm, vcpu)) { 1640 /* 1641 * APIC interrupts are delivered using the V_IRQ offload. 1642 * 1643 * The primary benefit is that the hypervisor doesn't need to 1644 * deal with the various conditions that inhibit interrupts. 1645 * It also means that TPR changes via CR8 will be handled 1646 * without any hypervisor involvement. 1647 * 1648 * Note that the APIC vector must remain pending in the vIRR 1649 * until it is confirmed that it was delivered to the guest. 1650 * This can be confirmed based on the value of V_IRQ at the 1651 * next #VMEXIT (1 = pending, 0 = delivered). 1652 * 1653 * Also note that it is possible that another higher priority 1654 * vector can become pending before this vector is delivered 1655 * to the guest. This is alright because vcpu_notify_event() 1656 * will send an IPI and force the vcpu to trap back into the 1657 * hypervisor. The higher priority vector will be injected on 1658 * the next VMRUN. 1659 */ 1660 if (vlapic_pending_intr(vlapic, &vector)) { 1661 KASSERT(vector >= 16 && vector <= 255, 1662 ("invalid vector %d from local APIC", vector)); 1663 pending_apic_vector = vector; 1664 } 1665 goto done; 1666 } 1667 1668 /* Ask the legacy pic for a vector to inject */ 1669 vatpic_pending_intr(sc->vm, &vector); 1670 KASSERT(vector >= 0 && vector <= 255, ("invalid vector %d from INTR", 1671 vector)); 1672 1673 /* 1674 * If the guest has disabled interrupts or is in an interrupt shadow 1675 * then we cannot inject the pending interrupt. 1676 */ 1677 if ((state->rflags & PSL_I) == 0) { 1678 VCPU_CTR2(sc->vm, vcpu, "Cannot inject vector %d due to " 1679 "rflags %#lx", vector, state->rflags); 1680 need_intr_window = 1; 1681 goto done; 1682 } 1683 1684 if (ctrl->intr_shadow) { 1685 VCPU_CTR1(sc->vm, vcpu, "Cannot inject vector %d due to " 1686 "interrupt shadow", vector); 1687 need_intr_window = 1; 1688 goto done; 1689 } 1690 1691 if (ctrl->eventinj & VMCB_EVENTINJ_VALID) { 1692 VCPU_CTR2(sc->vm, vcpu, "Cannot inject vector %d due to " 1693 "eventinj %#lx", vector, ctrl->eventinj); 1694 need_intr_window = 1; 1695 goto done; 1696 } 1697 1698 /* 1699 * Legacy PIC interrupts are delivered via the event injection 1700 * mechanism. 1701 */ 1702 svm_eventinject(sc, vcpu, VMCB_EVENTINJ_TYPE_INTR, vector, 0, false); 1703 1704 vm_extint_clear(sc->vm, vcpu); 1705 vatpic_intr_accepted(sc->vm, vector); 1706 1707 /* 1708 * Force a VM-exit as soon as the vcpu is ready to accept another 1709 * interrupt. This is done because the PIC might have another vector 1710 * that it wants to inject. Also, if the APIC has a pending interrupt 1711 * that was preempted by the ExtInt then it allows us to inject the 1712 * APIC vector as soon as possible. 1713 */ 1714 need_intr_window = 1; 1715done: 1716 /* 1717 * The guest can modify the TPR by writing to %CR8. In guest mode 1718 * the processor reflects this write to V_TPR without hypervisor 1719 * intervention. 1720 * 1721 * The guest can also modify the TPR by writing to it via the memory 1722 * mapped APIC page. In this case, the write will be emulated by the 1723 * hypervisor. For this reason V_TPR must be updated before every 1724 * VMRUN. 1725 */ 1726 v_tpr = vlapic_get_cr8(vlapic); 1727 KASSERT(v_tpr <= 15, ("invalid v_tpr %#x", v_tpr)); 1728 if (ctrl->v_tpr != v_tpr) { 1729 VCPU_CTR2(sc->vm, vcpu, "VMCB V_TPR changed from %#x to %#x", 1730 ctrl->v_tpr, v_tpr); 1731 ctrl->v_tpr = v_tpr; 1732 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 1733 } 1734 1735 if (pending_apic_vector) { 1736 /* 1737 * If an APIC vector is being injected then interrupt window 1738 * exiting is not possible on this VMRUN. 1739 */ 1740 KASSERT(!need_intr_window, ("intr_window exiting impossible")); 1741 VCPU_CTR1(sc->vm, vcpu, "Injecting vector %d using V_IRQ", 1742 pending_apic_vector); 1743 1744 ctrl->v_irq = 1; 1745 ctrl->v_ign_tpr = 0; 1746 ctrl->v_intr_vector = pending_apic_vector; 1747 ctrl->v_intr_prio = pending_apic_vector >> 4; 1748 svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR); 1749 } else if (need_intr_window) { 1750 /* 1751 * We use V_IRQ in conjunction with the VINTR intercept to 1752 * trap into the hypervisor as soon as a virtual interrupt 1753 * can be delivered. 1754 * 1755 * Since injected events are not subject to intercept checks 1756 * we need to ensure that the V_IRQ is not actually going to 1757 * be delivered on VM entry. The KASSERT below enforces this. 1758 */ 1759 KASSERT((ctrl->eventinj & VMCB_EVENTINJ_VALID) != 0 || 1760 (state->rflags & PSL_I) == 0 || ctrl->intr_shadow, 1761 ("Bogus intr_window_exiting: eventinj (%#lx), " 1762 "intr_shadow (%u), rflags (%#lx)", 1763 ctrl->eventinj, ctrl->intr_shadow, state->rflags)); 1764 enable_intr_window_exiting(sc, vcpu); 1765 } else { 1766 disable_intr_window_exiting(sc, vcpu); 1767 } 1768} 1769 1770static __inline void 1771restore_host_tss(void) 1772{ 1773 struct system_segment_descriptor *tss_sd; 1774 1775 /* 1776 * The TSS descriptor was in use prior to launching the guest so it 1777 * has been marked busy. 1778 * 1779 * 'ltr' requires the descriptor to be marked available so change the 1780 * type to "64-bit available TSS". 1781 */ 1782 tss_sd = PCPU_GET(tss); 1783 tss_sd->sd_type = SDT_SYSTSS; 1784 ltr(GSEL(GPROC0_SEL, SEL_KPL)); 1785} 1786 1787static void 1788check_asid(struct svm_softc *sc, int vcpuid, pmap_t pmap, u_int thiscpu) 1789{ 1790 struct svm_vcpu *vcpustate; 1791 struct vmcb_ctrl *ctrl; 1792 long eptgen; 1793 bool alloc_asid; 1794 1795 KASSERT(CPU_ISSET(thiscpu, &pmap->pm_active), ("%s: nested pmap not " 1796 "active on cpu %u", __func__, thiscpu)); 1797 1798 vcpustate = svm_get_vcpu(sc, vcpuid); 1799 ctrl = svm_get_vmcb_ctrl(sc, vcpuid); 1800 1801 /* 1802 * The TLB entries associated with the vcpu's ASID are not valid 1803 * if either of the following conditions is true: 1804 * 1805 * 1. The vcpu's ASID generation is different than the host cpu's 1806 * ASID generation. This happens when the vcpu migrates to a new 1807 * host cpu. It can also happen when the number of vcpus executing 1808 * on a host cpu is greater than the number of ASIDs available. 1809 * 1810 * 2. The pmap generation number is different than the value cached in 1811 * the 'vcpustate'. This happens when the host invalidates pages 1812 * belonging to the guest. 1813 * 1814 * asidgen eptgen Action 1815 * mismatch mismatch 1816 * 0 0 (a) 1817 * 0 1 (b1) or (b2) 1818 * 1 0 (c) 1819 * 1 1 (d) 1820 * 1821 * (a) There is no mismatch in eptgen or ASID generation and therefore 1822 * no further action is needed. 1823 * 1824 * (b1) If the cpu supports FlushByAsid then the vcpu's ASID is 1825 * retained and the TLB entries associated with this ASID 1826 * are flushed by VMRUN. 1827 * 1828 * (b2) If the cpu does not support FlushByAsid then a new ASID is 1829 * allocated. 1830 * 1831 * (c) A new ASID is allocated. 1832 * 1833 * (d) A new ASID is allocated. 1834 */ 1835 1836 alloc_asid = false; 1837 eptgen = pmap->pm_eptgen; 1838 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_NOTHING; 1839 1840 if (vcpustate->asid.gen != asid[thiscpu].gen) { 1841 alloc_asid = true; /* (c) and (d) */ 1842 } else if (vcpustate->eptgen != eptgen) { 1843 if (flush_by_asid()) 1844 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST; /* (b1) */ 1845 else 1846 alloc_asid = true; /* (b2) */ 1847 } else { 1848 /* 1849 * This is the common case (a). 1850 */ 1851 KASSERT(!alloc_asid, ("ASID allocation not necessary")); 1852 KASSERT(ctrl->tlb_ctrl == VMCB_TLB_FLUSH_NOTHING, 1853 ("Invalid VMCB tlb_ctrl: %#x", ctrl->tlb_ctrl)); 1854 } 1855 1856 if (alloc_asid) { 1857 if (++asid[thiscpu].num >= nasid) { 1858 asid[thiscpu].num = 1; 1859 if (++asid[thiscpu].gen == 0) 1860 asid[thiscpu].gen = 1; 1861 /* 1862 * If this cpu does not support "flush-by-asid" 1863 * then flush the entire TLB on a generation 1864 * bump. Subsequent ASID allocation in this 1865 * generation can be done without a TLB flush. 1866 */ 1867 if (!flush_by_asid()) 1868 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_ALL; 1869 } 1870 vcpustate->asid.gen = asid[thiscpu].gen; 1871 vcpustate->asid.num = asid[thiscpu].num; 1872 1873 ctrl->asid = vcpustate->asid.num; 1874 svm_set_dirty(sc, vcpuid, VMCB_CACHE_ASID); 1875 /* 1876 * If this cpu supports "flush-by-asid" then the TLB 1877 * was not flushed after the generation bump. The TLB 1878 * is flushed selectively after every new ASID allocation. 1879 */ 1880 if (flush_by_asid()) 1881 ctrl->tlb_ctrl = VMCB_TLB_FLUSH_GUEST; 1882 } 1883 vcpustate->eptgen = eptgen; 1884 1885 KASSERT(ctrl->asid != 0, ("Guest ASID must be non-zero")); 1886 KASSERT(ctrl->asid == vcpustate->asid.num, 1887 ("ASID mismatch: %u/%u", ctrl->asid, vcpustate->asid.num)); 1888} 1889 1890static __inline void 1891disable_gintr(void) 1892{ 1893 1894 __asm __volatile("clgi"); 1895} 1896 1897static __inline void 1898enable_gintr(void) 1899{ 1900 1901 __asm __volatile("stgi"); 1902} 1903 1904/* 1905 * Start vcpu with specified RIP. 1906 */ 1907static int 1908svm_vmrun(void *arg, int vcpu, register_t rip, pmap_t pmap, 1909 struct vm_eventinfo *evinfo) 1910{ 1911 struct svm_regctx *gctx; 1912 struct svm_softc *svm_sc; 1913 struct svm_vcpu *vcpustate; 1914 struct vmcb_state *state; 1915 struct vmcb_ctrl *ctrl; 1916 struct vm_exit *vmexit; 1917 struct vlapic *vlapic; 1918 struct vm *vm; 1919 uint64_t vmcb_pa; 1920 int handled; 1921 1922 svm_sc = arg; 1923 vm = svm_sc->vm; 1924 1925 vcpustate = svm_get_vcpu(svm_sc, vcpu); 1926 state = svm_get_vmcb_state(svm_sc, vcpu); 1927 ctrl = svm_get_vmcb_ctrl(svm_sc, vcpu); 1928 vmexit = vm_exitinfo(vm, vcpu); 1929 vlapic = vm_lapic(vm, vcpu); 1930 1931 gctx = svm_get_guest_regctx(svm_sc, vcpu); 1932 vmcb_pa = svm_sc->vcpu[vcpu].vmcb_pa; 1933 1934 if (vcpustate->lastcpu != curcpu) { 1935 /* 1936 * Force new ASID allocation by invalidating the generation. 1937 */ 1938 vcpustate->asid.gen = 0; 1939 1940 /* 1941 * Invalidate the VMCB state cache by marking all fields dirty. 1942 */ 1943 svm_set_dirty(svm_sc, vcpu, 0xffffffff); 1944 1945 /* 1946 * XXX 1947 * Setting 'vcpustate->lastcpu' here is bit premature because 1948 * we may return from this function without actually executing 1949 * the VMRUN instruction. This could happen if a rendezvous 1950 * or an AST is pending on the first time through the loop. 1951 * 1952 * This works for now but any new side-effects of vcpu 1953 * migration should take this case into account. 1954 */ 1955 vcpustate->lastcpu = curcpu; 1956 vmm_stat_incr(vm, vcpu, VCPU_MIGRATIONS, 1); 1957 } 1958 1959 svm_msr_guest_enter(svm_sc, vcpu); 1960 1961 /* Update Guest RIP */ 1962 state->rip = rip; 1963 1964 do { 1965 /* 1966 * Disable global interrupts to guarantee atomicity during 1967 * loading of guest state. This includes not only the state 1968 * loaded by the "vmrun" instruction but also software state 1969 * maintained by the hypervisor: suspended and rendezvous 1970 * state, NPT generation number, vlapic interrupts etc. 1971 */ 1972 disable_gintr(); 1973 1974 if (vcpu_suspended(evinfo)) { 1975 enable_gintr(); 1976 vm_exit_suspended(vm, vcpu, state->rip); 1977 break; 1978 } 1979 1980 if (vcpu_rendezvous_pending(evinfo)) { 1981 enable_gintr(); 1982 vm_exit_rendezvous(vm, vcpu, state->rip); 1983 break; 1984 } 1985 1986 if (vcpu_reqidle(evinfo)) { 1987 enable_gintr(); 1988 vm_exit_reqidle(vm, vcpu, state->rip); 1989 break; 1990 } 1991 1992 /* We are asked to give the cpu by scheduler. */ 1993 if (vcpu_should_yield(vm, vcpu)) { 1994 enable_gintr(); 1995 vm_exit_astpending(vm, vcpu, state->rip); 1996 break; 1997 } 1998 1999 svm_inj_interrupts(svm_sc, vcpu, vlapic); 2000 2001 /* Activate the nested pmap on 'curcpu' */ 2002 CPU_SET_ATOMIC_ACQ(curcpu, &pmap->pm_active); 2003 2004 /* 2005 * Check the pmap generation and the ASID generation to 2006 * ensure that the vcpu does not use stale TLB mappings. 2007 */ 2008 check_asid(svm_sc, vcpu, pmap, curcpu); 2009 2010 ctrl->vmcb_clean = vmcb_clean & ~vcpustate->dirty; 2011 vcpustate->dirty = 0; 2012 VCPU_CTR1(vm, vcpu, "vmcb clean %#x", ctrl->vmcb_clean); 2013 2014 /* Launch Virtual Machine. */ 2015 VCPU_CTR1(vm, vcpu, "Resume execution at %#lx", state->rip); 2016 svm_launch(vmcb_pa, gctx, &__pcpu[curcpu]); 2017 2018 CPU_CLR_ATOMIC(curcpu, &pmap->pm_active); 2019 2020 /* 2021 * The host GDTR and IDTR is saved by VMRUN and restored 2022 * automatically on #VMEXIT. However, the host TSS needs 2023 * to be restored explicitly. 2024 */ 2025 restore_host_tss(); 2026 2027 /* #VMEXIT disables interrupts so re-enable them here. */ 2028 enable_gintr(); 2029 2030 /* Update 'nextrip' */ 2031 vcpustate->nextrip = state->rip; 2032 2033 /* Handle #VMEXIT and if required return to user space. */ 2034 handled = svm_vmexit(svm_sc, vcpu, vmexit); 2035 } while (handled); 2036 2037 svm_msr_guest_exit(svm_sc, vcpu); 2038 2039 return (0); 2040} 2041 2042static void 2043svm_vmcleanup(void *arg) 2044{ 2045 struct svm_softc *sc = arg; 2046 2047 contigfree(sc, sizeof (*sc), M_SVM); 2048} 2049 2050static register_t * 2051swctx_regptr(struct svm_regctx *regctx, int reg) 2052{ 2053 2054 switch (reg) { 2055 case VM_REG_GUEST_RBX: 2056 return (®ctx->sctx_rbx); 2057 case VM_REG_GUEST_RCX: 2058 return (®ctx->sctx_rcx); 2059 case VM_REG_GUEST_RDX: 2060 return (®ctx->sctx_rdx); 2061 case VM_REG_GUEST_RDI: 2062 return (®ctx->sctx_rdi); 2063 case VM_REG_GUEST_RSI: 2064 return (®ctx->sctx_rsi); 2065 case VM_REG_GUEST_RBP: 2066 return (®ctx->sctx_rbp); 2067 case VM_REG_GUEST_R8: 2068 return (®ctx->sctx_r8); 2069 case VM_REG_GUEST_R9: 2070 return (®ctx->sctx_r9); 2071 case VM_REG_GUEST_R10: 2072 return (®ctx->sctx_r10); 2073 case VM_REG_GUEST_R11: 2074 return (®ctx->sctx_r11); 2075 case VM_REG_GUEST_R12: 2076 return (®ctx->sctx_r12); 2077 case VM_REG_GUEST_R13: 2078 return (®ctx->sctx_r13); 2079 case VM_REG_GUEST_R14: 2080 return (®ctx->sctx_r14); 2081 case VM_REG_GUEST_R15: 2082 return (®ctx->sctx_r15); 2083 default: 2084 return (NULL); 2085 } 2086} 2087 2088static int 2089svm_getreg(void *arg, int vcpu, int ident, uint64_t *val) 2090{ 2091 struct svm_softc *svm_sc; 2092 register_t *reg; 2093 2094 svm_sc = arg; 2095 2096 if (ident == VM_REG_GUEST_INTR_SHADOW) { 2097 return (svm_get_intr_shadow(svm_sc, vcpu, val)); 2098 } 2099 2100 if (vmcb_read(svm_sc, vcpu, ident, val) == 0) { 2101 return (0); 2102 } 2103 2104 reg = swctx_regptr(svm_get_guest_regctx(svm_sc, vcpu), ident); 2105 2106 if (reg != NULL) { 2107 *val = *reg; 2108 return (0); 2109 } 2110 2111 VCPU_CTR1(svm_sc->vm, vcpu, "svm_getreg: unknown register %#x", ident); 2112 return (EINVAL); 2113} 2114 2115static int 2116svm_setreg(void *arg, int vcpu, int ident, uint64_t val) 2117{ 2118 struct svm_softc *svm_sc; 2119 register_t *reg; 2120 2121 svm_sc = arg; 2122 2123 if (ident == VM_REG_GUEST_INTR_SHADOW) { 2124 return (svm_modify_intr_shadow(svm_sc, vcpu, val)); 2125 } 2126 2127 if (vmcb_write(svm_sc, vcpu, ident, val) == 0) { 2128 return (0); 2129 } 2130 2131 reg = swctx_regptr(svm_get_guest_regctx(svm_sc, vcpu), ident); 2132 2133 if (reg != NULL) { 2134 *reg = val; 2135 return (0); 2136 } 2137 2138 /* 2139 * XXX deal with CR3 and invalidate TLB entries tagged with the 2140 * vcpu's ASID. This needs to be treated differently depending on 2141 * whether 'running' is true/false. 2142 */ 2143 2144 VCPU_CTR1(svm_sc->vm, vcpu, "svm_setreg: unknown register %#x", ident); 2145 return (EINVAL); 2146} 2147 2148static int 2149svm_setcap(void *arg, int vcpu, int type, int val) 2150{ 2151 struct svm_softc *sc; 2152 int error; 2153 2154 sc = arg; 2155 error = 0; 2156 switch (type) { 2157 case VM_CAP_HALT_EXIT: 2158 svm_set_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2159 VMCB_INTCPT_HLT, val); 2160 break; 2161 case VM_CAP_PAUSE_EXIT: 2162 svm_set_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2163 VMCB_INTCPT_PAUSE, val); 2164 break; 2165 case VM_CAP_UNRESTRICTED_GUEST: 2166 /* Unrestricted guest execution cannot be disabled in SVM */ 2167 if (val == 0) 2168 error = EINVAL; 2169 break; 2170 default: 2171 error = ENOENT; 2172 break; 2173 } 2174 return (error); 2175} 2176 2177static int 2178svm_getcap(void *arg, int vcpu, int type, int *retval) 2179{ 2180 struct svm_softc *sc; 2181 int error; 2182 2183 sc = arg; 2184 error = 0; 2185 2186 switch (type) { 2187 case VM_CAP_HALT_EXIT: 2188 *retval = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2189 VMCB_INTCPT_HLT); 2190 break; 2191 case VM_CAP_PAUSE_EXIT: 2192 *retval = svm_get_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, 2193 VMCB_INTCPT_PAUSE); 2194 break; 2195 case VM_CAP_UNRESTRICTED_GUEST: 2196 *retval = 1; /* unrestricted guest is always enabled */ 2197 break; 2198 default: 2199 error = ENOENT; 2200 break; 2201 } 2202 return (error); 2203} 2204 2205static struct vlapic * 2206svm_vlapic_init(void *arg, int vcpuid) 2207{ 2208 struct svm_softc *svm_sc; 2209 struct vlapic *vlapic; 2210 2211 svm_sc = arg; 2212 vlapic = malloc(sizeof(struct vlapic), M_SVM_VLAPIC, M_WAITOK | M_ZERO); 2213 vlapic->vm = svm_sc->vm; 2214 vlapic->vcpuid = vcpuid; 2215 vlapic->apic_page = (struct LAPIC *)&svm_sc->apic_page[vcpuid]; 2216 2217 vlapic_init(vlapic); 2218 2219 return (vlapic); 2220} 2221 2222static void 2223svm_vlapic_cleanup(void *arg, struct vlapic *vlapic) 2224{ 2225 2226 vlapic_cleanup(vlapic); 2227 free(vlapic, M_SVM_VLAPIC); 2228} 2229 2230struct vmm_ops vmm_ops_amd = { 2231 svm_init, 2232 svm_cleanup, 2233 svm_restore, 2234 svm_vminit, 2235 svm_vmrun, 2236 svm_vmcleanup, 2237 svm_getreg, 2238 svm_setreg, 2239 vmcb_getdesc, 2240 vmcb_setdesc, 2241 svm_getcap, 2242 svm_setcap, 2243 svm_npt_alloc, 2244 svm_npt_free, 2245 svm_vlapic_init, 2246 svm_vlapic_cleanup 2247}; 2248