1/* 2 * Chelsio Terminator 4 (T4) Firmware interface header file. 3 * 4 * Copyright (C) 2009-2014 Chelsio Communications. All rights reserved. 5 * 6 * Written by felix marti (felix@chelsio.com) 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 11 * release for licensing terms and conditions. 12 */ 13 14#ifndef _T4FW_INTERFACE_H_ 15#define _T4FW_INTERFACE_H_ 16 17/****************************************************************************** 18 * R E T U R N V A L U E S 19 ********************************/ 20 21enum fw_retval { 22 FW_SUCCESS = 0, /* completed sucessfully */ 23 FW_EPERM = 1, /* operation not permitted */ 24 FW_ENOENT = 2, /* no such file or directory */ 25 FW_EIO = 5, /* input/output error; hw bad */ 26 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 27 FW_EAGAIN = 11, /* try again */ 28 FW_ENOMEM = 12, /* out of memory */ 29 FW_EFAULT = 14, /* bad address; fw bad */ 30 FW_EBUSY = 16, /* resource busy */ 31 FW_EEXIST = 17, /* file exists */ 32 FW_ENODEV = 19, /* no such device */ 33 FW_EINVAL = 22, /* invalid argument */ 34 FW_ENOSPC = 28, /* no space left on device */ 35 FW_ENOSYS = 38, /* functionality not implemented */ 36 FW_ENODATA = 61, /* no data available */ 37 FW_EPROTO = 71, /* protocol error */ 38 FW_EADDRINUSE = 98, /* address already in use */ 39 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 40 FW_ENETDOWN = 100, /* network is down */ 41 FW_ENETUNREACH = 101, /* network is unreachable */ 42 FW_ENOBUFS = 105, /* no buffer space available */ 43 FW_ETIMEDOUT = 110, /* timeout */ 44 FW_EINPROGRESS = 115, /* fw internal */ 45 FW_SCSI_ABORT_REQUESTED = 128, /* */ 46 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 47 FW_SCSI_ABORTED = 130, /* */ 48 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 49 FW_ERR_LINK_DOWN = 132, /* */ 50 FW_RDEV_NOT_READY = 133, /* */ 51 FW_ERR_RDEV_LOST = 134, /* */ 52 FW_ERR_RDEV_LOGO = 135, /* */ 53 FW_FCOE_NO_XCHG = 136, /* */ 54 FW_SCSI_RSP_ERR = 137, /* */ 55 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 56 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 57 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 58 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 59 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 60}; 61 62/****************************************************************************** 63 * M E M O R Y T Y P E s 64 ******************************/ 65 66enum fw_memtype { 67 FW_MEMTYPE_EDC0 = 0x0, 68 FW_MEMTYPE_EDC1 = 0x1, 69 FW_MEMTYPE_EXTMEM = 0x2, 70 FW_MEMTYPE_FLASH = 0x4, 71 FW_MEMTYPE_INTERNAL = 0x5, 72 FW_MEMTYPE_EXTMEM1 = 0x6, 73}; 74 75/****************************************************************************** 76 * W O R K R E Q U E S T s 77 ********************************/ 78 79enum fw_wr_opcodes { 80 FW_FRAG_WR = 0x1d, 81 FW_FILTER_WR = 0x02, 82 FW_ULPTX_WR = 0x04, 83 FW_TP_WR = 0x05, 84 FW_ETH_TX_PKT_WR = 0x08, 85 FW_ETH_TX_PKT2_WR = 0x44, 86 FW_ETH_TX_PKTS_WR = 0x09, 87 FW_ETH_TX_UO_WR = 0x1c, 88 FW_EQ_FLUSH_WR = 0x1b, 89 FW_OFLD_CONNECTION_WR = 0x2f, 90 FW_FLOWC_WR = 0x0a, 91 FW_OFLD_TX_DATA_WR = 0x0b, 92 FW_CMD_WR = 0x10, 93 FW_ETH_TX_PKT_VM_WR = 0x11, 94 FW_RI_RES_WR = 0x0c, 95 FW_RI_RDMA_WRITE_WR = 0x14, 96 FW_RI_SEND_WR = 0x15, 97 FW_RI_RDMA_READ_WR = 0x16, 98 FW_RI_RECV_WR = 0x17, 99 FW_RI_BIND_MW_WR = 0x18, 100 FW_RI_FR_NSMR_WR = 0x19, 101 FW_RI_INV_LSTAG_WR = 0x1a, 102 FW_RI_SEND_IMMEDIATE_WR = 0x15, 103 FW_RI_ATOMIC_WR = 0x16, 104 FW_RI_WR = 0x0d, 105 FW_CHNET_IFCONF_WR = 0x6b, 106 FW_RDEV_WR = 0x38, 107 FW_FOISCSI_NODE_WR = 0x60, 108 FW_FOISCSI_CTRL_WR = 0x6a, 109 FW_FOISCSI_CHAP_WR = 0x6c, 110 FW_FCOE_ELS_CT_WR = 0x30, 111 FW_SCSI_WRITE_WR = 0x31, 112 FW_SCSI_READ_WR = 0x32, 113 FW_SCSI_CMD_WR = 0x33, 114 FW_SCSI_ABRT_CLS_WR = 0x34, 115 FW_SCSI_TGT_ACC_WR = 0x35, 116 FW_SCSI_TGT_XMIT_WR = 0x36, 117 FW_SCSI_TGT_RSP_WR = 0x37, 118 FW_POFCOE_TCB_WR = 0x42, 119 FW_POFCOE_ULPTX_WR = 0x43, 120 FW_LASTC2E_WR = 0x70 121}; 122 123/* 124 * Generic work request header flit0 125 */ 126struct fw_wr_hdr { 127 __be32 hi; 128 __be32 lo; 129}; 130 131/* work request opcode (hi) 132 */ 133#define S_FW_WR_OP 24 134#define M_FW_WR_OP 0xff 135#define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 136#define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 137 138/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 139 */ 140#define S_FW_WR_ATOMIC 23 141#define M_FW_WR_ATOMIC 0x1 142#define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 143#define G_FW_WR_ATOMIC(x) \ 144 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 145#define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 146 147/* flush flag (hi) - firmware flushes flushable work request buffered 148 * in the flow context. 149 */ 150#define S_FW_WR_FLUSH 22 151#define M_FW_WR_FLUSH 0x1 152#define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 153#define G_FW_WR_FLUSH(x) \ 154 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 155#define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 156 157/* completion flag (hi) - firmware generates a cpl_fw6_ack 158 */ 159#define S_FW_WR_COMPL 21 160#define M_FW_WR_COMPL 0x1 161#define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 162#define G_FW_WR_COMPL(x) \ 163 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 164#define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 165 166 167/* work request immediate data lengh (hi) 168 */ 169#define S_FW_WR_IMMDLEN 0 170#define M_FW_WR_IMMDLEN 0xff 171#define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 172#define G_FW_WR_IMMDLEN(x) \ 173 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 174 175/* egress queue status update to associated ingress queue entry (lo) 176 */ 177#define S_FW_WR_EQUIQ 31 178#define M_FW_WR_EQUIQ 0x1 179#define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 180#define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 181#define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 182 183/* egress queue status update to egress queue status entry (lo) 184 */ 185#define S_FW_WR_EQUEQ 30 186#define M_FW_WR_EQUEQ 0x1 187#define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 188#define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 189#define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 190 191/* flow context identifier (lo) 192 */ 193#define S_FW_WR_FLOWID 8 194#define M_FW_WR_FLOWID 0xfffff 195#define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 196#define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 197 198/* length in units of 16-bytes (lo) 199 */ 200#define S_FW_WR_LEN16 0 201#define M_FW_WR_LEN16 0xff 202#define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 203#define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 204 205struct fw_frag_wr { 206 __be32 op_to_fragoff16; 207 __be32 flowid_len16; 208 __be64 r4; 209}; 210 211#define S_FW_FRAG_WR_EOF 15 212#define M_FW_FRAG_WR_EOF 0x1 213#define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 214#define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 215#define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 216 217#define S_FW_FRAG_WR_FRAGOFF16 8 218#define M_FW_FRAG_WR_FRAGOFF16 0x7f 219#define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 220#define G_FW_FRAG_WR_FRAGOFF16(x) \ 221 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 222 223/* valid filter configurations for compressed tuple 224 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 225 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 226 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 227 * OV - Outer VLAN/VNIC_ID, 228*/ 229#define HW_TPL_FR_MT_M_E_P_FC 0x3C3 230#define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 231#define HW_TPL_FR_MT_M_IV_P_FC 0x38B 232#define HW_TPL_FR_MT_M_OV_P_FC 0x387 233#define HW_TPL_FR_MT_E_PR_T 0x370 234#define HW_TPL_FR_MT_E_PR_P_FC 0X363 235#define HW_TPL_FR_MT_E_T_P_FC 0X353 236#define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 237#define HW_TPL_FR_MT_PR_OV_P_FC 0X327 238#define HW_TPL_FR_MT_T_IV_P_FC 0X31B 239#define HW_TPL_FR_MT_T_OV_P_FC 0X317 240#define HW_TPL_FR_M_E_PR_FC 0X2E1 241#define HW_TPL_FR_M_E_T_FC 0X2D1 242#define HW_TPL_FR_M_PR_IV_FC 0X2A9 243#define HW_TPL_FR_M_PR_OV_FC 0X2A5 244#define HW_TPL_FR_M_T_IV_FC 0X299 245#define HW_TPL_FR_M_T_OV_FC 0X295 246#define HW_TPL_FR_E_PR_T_P 0X272 247#define HW_TPL_FR_E_PR_T_FC 0X271 248#define HW_TPL_FR_E_IV_FC 0X249 249#define HW_TPL_FR_E_OV_FC 0X245 250#define HW_TPL_FR_PR_T_IV_FC 0X239 251#define HW_TPL_FR_PR_T_OV_FC 0X235 252#define HW_TPL_FR_IV_OV_FC 0X20D 253#define HW_TPL_MT_M_E_PR 0X1E0 254#define HW_TPL_MT_M_E_T 0X1D0 255#define HW_TPL_MT_E_PR_T_FC 0X171 256#define HW_TPL_MT_E_IV 0X148 257#define HW_TPL_MT_E_OV 0X144 258#define HW_TPL_MT_PR_T_IV 0X138 259#define HW_TPL_MT_PR_T_OV 0X134 260#define HW_TPL_M_E_PR_P 0X0E2 261#define HW_TPL_M_E_T_P 0X0D2 262#define HW_TPL_E_PR_T_P_FC 0X073 263#define HW_TPL_E_IV_P 0X04A 264#define HW_TPL_E_OV_P 0X046 265#define HW_TPL_PR_T_IV_P 0X03A 266#define HW_TPL_PR_T_OV_P 0X036 267 268/* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 269enum fw_filter_wr_cookie { 270 FW_FILTER_WR_SUCCESS, 271 FW_FILTER_WR_FLT_ADDED, 272 FW_FILTER_WR_FLT_DELETED, 273 FW_FILTER_WR_SMT_TBL_FULL, 274 FW_FILTER_WR_EINVAL, 275}; 276 277struct fw_filter_wr { 278 __be32 op_pkd; 279 __be32 len16_pkd; 280 __be64 r3; 281 __be32 tid_to_iq; 282 __be32 del_filter_to_l2tix; 283 __be16 ethtype; 284 __be16 ethtypem; 285 __u8 frag_to_ovlan_vldm; 286 __u8 smac_sel; 287 __be16 rx_chan_rx_rpl_iq; 288 __be32 maci_to_matchtypem; 289 __u8 ptcl; 290 __u8 ptclm; 291 __u8 ttyp; 292 __u8 ttypm; 293 __be16 ivlan; 294 __be16 ivlanm; 295 __be16 ovlan; 296 __be16 ovlanm; 297 __u8 lip[16]; 298 __u8 lipm[16]; 299 __u8 fip[16]; 300 __u8 fipm[16]; 301 __be16 lp; 302 __be16 lpm; 303 __be16 fp; 304 __be16 fpm; 305 __be16 r7; 306 __u8 sma[6]; 307}; 308 309#define S_FW_FILTER_WR_TID 12 310#define M_FW_FILTER_WR_TID 0xfffff 311#define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 312#define G_FW_FILTER_WR_TID(x) \ 313 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 314 315#define S_FW_FILTER_WR_RQTYPE 11 316#define M_FW_FILTER_WR_RQTYPE 0x1 317#define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 318#define G_FW_FILTER_WR_RQTYPE(x) \ 319 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 320#define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 321 322#define S_FW_FILTER_WR_NOREPLY 10 323#define M_FW_FILTER_WR_NOREPLY 0x1 324#define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 325#define G_FW_FILTER_WR_NOREPLY(x) \ 326 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 327#define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 328 329#define S_FW_FILTER_WR_IQ 0 330#define M_FW_FILTER_WR_IQ 0x3ff 331#define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 332#define G_FW_FILTER_WR_IQ(x) \ 333 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 334 335#define S_FW_FILTER_WR_DEL_FILTER 31 336#define M_FW_FILTER_WR_DEL_FILTER 0x1 337#define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 338#define G_FW_FILTER_WR_DEL_FILTER(x) \ 339 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 340#define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 341 342#define S_FW_FILTER_WR_RPTTID 25 343#define M_FW_FILTER_WR_RPTTID 0x1 344#define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 345#define G_FW_FILTER_WR_RPTTID(x) \ 346 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 347#define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 348 349#define S_FW_FILTER_WR_DROP 24 350#define M_FW_FILTER_WR_DROP 0x1 351#define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 352#define G_FW_FILTER_WR_DROP(x) \ 353 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 354#define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 355 356#define S_FW_FILTER_WR_DIRSTEER 23 357#define M_FW_FILTER_WR_DIRSTEER 0x1 358#define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 359#define G_FW_FILTER_WR_DIRSTEER(x) \ 360 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 361#define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 362 363#define S_FW_FILTER_WR_MASKHASH 22 364#define M_FW_FILTER_WR_MASKHASH 0x1 365#define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 366#define G_FW_FILTER_WR_MASKHASH(x) \ 367 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 368#define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 369 370#define S_FW_FILTER_WR_DIRSTEERHASH 21 371#define M_FW_FILTER_WR_DIRSTEERHASH 0x1 372#define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 373#define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 374 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 375#define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 376 377#define S_FW_FILTER_WR_LPBK 20 378#define M_FW_FILTER_WR_LPBK 0x1 379#define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 380#define G_FW_FILTER_WR_LPBK(x) \ 381 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 382#define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 383 384#define S_FW_FILTER_WR_DMAC 19 385#define M_FW_FILTER_WR_DMAC 0x1 386#define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 387#define G_FW_FILTER_WR_DMAC(x) \ 388 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 389#define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 390 391#define S_FW_FILTER_WR_SMAC 18 392#define M_FW_FILTER_WR_SMAC 0x1 393#define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 394#define G_FW_FILTER_WR_SMAC(x) \ 395 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 396#define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 397 398#define S_FW_FILTER_WR_INSVLAN 17 399#define M_FW_FILTER_WR_INSVLAN 0x1 400#define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 401#define G_FW_FILTER_WR_INSVLAN(x) \ 402 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 403#define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 404 405#define S_FW_FILTER_WR_RMVLAN 16 406#define M_FW_FILTER_WR_RMVLAN 0x1 407#define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 408#define G_FW_FILTER_WR_RMVLAN(x) \ 409 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 410#define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 411 412#define S_FW_FILTER_WR_HITCNTS 15 413#define M_FW_FILTER_WR_HITCNTS 0x1 414#define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 415#define G_FW_FILTER_WR_HITCNTS(x) \ 416 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 417#define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 418 419#define S_FW_FILTER_WR_TXCHAN 13 420#define M_FW_FILTER_WR_TXCHAN 0x3 421#define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 422#define G_FW_FILTER_WR_TXCHAN(x) \ 423 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 424 425#define S_FW_FILTER_WR_PRIO 12 426#define M_FW_FILTER_WR_PRIO 0x1 427#define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 428#define G_FW_FILTER_WR_PRIO(x) \ 429 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 430#define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 431 432#define S_FW_FILTER_WR_L2TIX 0 433#define M_FW_FILTER_WR_L2TIX 0xfff 434#define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 435#define G_FW_FILTER_WR_L2TIX(x) \ 436 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 437 438#define S_FW_FILTER_WR_FRAG 7 439#define M_FW_FILTER_WR_FRAG 0x1 440#define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 441#define G_FW_FILTER_WR_FRAG(x) \ 442 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 443#define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 444 445#define S_FW_FILTER_WR_FRAGM 6 446#define M_FW_FILTER_WR_FRAGM 0x1 447#define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 448#define G_FW_FILTER_WR_FRAGM(x) \ 449 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 450#define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 451 452#define S_FW_FILTER_WR_IVLAN_VLD 5 453#define M_FW_FILTER_WR_IVLAN_VLD 0x1 454#define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 455#define G_FW_FILTER_WR_IVLAN_VLD(x) \ 456 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 457#define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 458 459#define S_FW_FILTER_WR_OVLAN_VLD 4 460#define M_FW_FILTER_WR_OVLAN_VLD 0x1 461#define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 462#define G_FW_FILTER_WR_OVLAN_VLD(x) \ 463 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 464#define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 465 466#define S_FW_FILTER_WR_IVLAN_VLDM 3 467#define M_FW_FILTER_WR_IVLAN_VLDM 0x1 468#define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 469#define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 470 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 471#define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 472 473#define S_FW_FILTER_WR_OVLAN_VLDM 2 474#define M_FW_FILTER_WR_OVLAN_VLDM 0x1 475#define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 476#define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 477 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 478#define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 479 480#define S_FW_FILTER_WR_RX_CHAN 15 481#define M_FW_FILTER_WR_RX_CHAN 0x1 482#define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 483#define G_FW_FILTER_WR_RX_CHAN(x) \ 484 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 485#define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 486 487#define S_FW_FILTER_WR_RX_RPL_IQ 0 488#define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 489#define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 490#define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 491 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 492 493#define S_FW_FILTER_WR_MACI 23 494#define M_FW_FILTER_WR_MACI 0x1ff 495#define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 496#define G_FW_FILTER_WR_MACI(x) \ 497 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 498 499#define S_FW_FILTER_WR_MACIM 14 500#define M_FW_FILTER_WR_MACIM 0x1ff 501#define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 502#define G_FW_FILTER_WR_MACIM(x) \ 503 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 504 505#define S_FW_FILTER_WR_FCOE 13 506#define M_FW_FILTER_WR_FCOE 0x1 507#define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 508#define G_FW_FILTER_WR_FCOE(x) \ 509 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 510#define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 511 512#define S_FW_FILTER_WR_FCOEM 12 513#define M_FW_FILTER_WR_FCOEM 0x1 514#define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 515#define G_FW_FILTER_WR_FCOEM(x) \ 516 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 517#define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 518 519#define S_FW_FILTER_WR_PORT 9 520#define M_FW_FILTER_WR_PORT 0x7 521#define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 522#define G_FW_FILTER_WR_PORT(x) \ 523 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 524 525#define S_FW_FILTER_WR_PORTM 6 526#define M_FW_FILTER_WR_PORTM 0x7 527#define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 528#define G_FW_FILTER_WR_PORTM(x) \ 529 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 530 531#define S_FW_FILTER_WR_MATCHTYPE 3 532#define M_FW_FILTER_WR_MATCHTYPE 0x7 533#define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 534#define G_FW_FILTER_WR_MATCHTYPE(x) \ 535 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 536 537#define S_FW_FILTER_WR_MATCHTYPEM 0 538#define M_FW_FILTER_WR_MATCHTYPEM 0x7 539#define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 540#define G_FW_FILTER_WR_MATCHTYPEM(x) \ 541 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 542 543struct fw_ulptx_wr { 544 __be32 op_to_compl; 545 __be32 flowid_len16; 546 __u64 cookie; 547}; 548 549struct fw_tp_wr { 550 __be32 op_to_immdlen; 551 __be32 flowid_len16; 552 __u64 cookie; 553}; 554 555struct fw_eth_tx_pkt_wr { 556 __be32 op_immdlen; 557 __be32 equiq_to_len16; 558 __be64 r3; 559}; 560 561#define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 562#define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 563#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 564#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 565 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 566 567struct fw_eth_tx_pkt2_wr { 568 __be32 op_immdlen; 569 __be32 equiq_to_len16; 570 __be32 r3; 571 __be32 L4ChkDisable_to_IpHdrLen; 572}; 573 574#define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 575#define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 576#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 577#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 578 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 579 580#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 581#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 582#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 583 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 584#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 585 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 586 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 587#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 588 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 589 590#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 591#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 592#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 593 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 594#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 595 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 596 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 597#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 598 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 599 600#define S_FW_ETH_TX_PKT2_WR_IVLAN 28 601#define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 602#define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 603#define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 604 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 605#define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 606 607#define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 608#define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 609#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 610#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 611 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 612 613#define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 614#define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 615#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 616#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 617 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 618 619#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 620#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 621#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 622#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 623 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 624 625struct fw_eth_tx_pkts_wr { 626 __be32 op_pkd; 627 __be32 equiq_to_len16; 628 __be32 r3; 629 __be16 plen; 630 __u8 npkt; 631 __u8 type; 632}; 633 634struct fw_eth_tx_uo_wr { 635 __be32 op_immdlen; 636 __be32 equiq_to_len16; 637 __be64 r3; 638 __u8 r4; 639 __u8 ethlen; 640 __be16 iplen; 641 __u8 udplen; 642 __u8 rtplen; 643 __be16 r5; 644 __be16 mss; 645 __be16 schedpktsize; 646 __be32 length; 647}; 648 649struct fw_eq_flush_wr { 650 __u8 opcode; 651 __u8 r1[3]; 652 __be32 equiq_to_len16; 653 __be64 r3; 654}; 655 656struct fw_ofld_connection_wr { 657 __be32 op_compl; 658 __be32 len16_pkd; 659 __u64 cookie; 660 __be64 r2; 661 __be64 r3; 662 struct fw_ofld_connection_le { 663 __be32 version_cpl; 664 __be32 filter; 665 __be32 r1; 666 __be16 lport; 667 __be16 pport; 668 union fw_ofld_connection_leip { 669 struct fw_ofld_connection_le_ipv4 { 670 __be32 pip; 671 __be32 lip; 672 __be64 r0; 673 __be64 r1; 674 __be64 r2; 675 } ipv4; 676 struct fw_ofld_connection_le_ipv6 { 677 __be64 pip_hi; 678 __be64 pip_lo; 679 __be64 lip_hi; 680 __be64 lip_lo; 681 } ipv6; 682 } u; 683 } le; 684 struct fw_ofld_connection_tcb { 685 __be32 t_state_to_astid; 686 __be16 cplrxdataack_cplpassacceptrpl; 687 __be16 rcv_adv; 688 __be32 rcv_nxt; 689 __be32 tx_max; 690 __be64 opt0; 691 __be32 opt2; 692 __be32 r1; 693 __be64 r2; 694 __be64 r3; 695 } tcb; 696}; 697 698#define S_FW_OFLD_CONNECTION_WR_VERSION 31 699#define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 700#define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 701 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 702#define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 703 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 704 M_FW_OFLD_CONNECTION_WR_VERSION) 705#define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 706 707#define S_FW_OFLD_CONNECTION_WR_CPL 30 708#define M_FW_OFLD_CONNECTION_WR_CPL 0x1 709#define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 710#define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 711 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 712#define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 713 714#define S_FW_OFLD_CONNECTION_WR_T_STATE 28 715#define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 716#define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 717 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 718#define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 719 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 720 M_FW_OFLD_CONNECTION_WR_T_STATE) 721 722#define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 723#define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 724#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 725 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 726#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 727 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 728 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 729 730#define S_FW_OFLD_CONNECTION_WR_ASTID 0 731#define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 732#define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 733 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 734#define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 735 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 736 737#define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 738#define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 739#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 740 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 741#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 742 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 743 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 744#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 745 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 746 747#define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 748#define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 749#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 750 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 751#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 752 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 753 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 754#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 755 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 756 757enum fw_flowc_mnem_tcpstate { 758 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 759 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 760 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 761 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 762 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 763 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 764 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 765 * will resend FIN - equiv ESTAB 766 */ 767 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 768 * will resend FIN but have 769 * received FIN 770 */ 771 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 772 * will resend FIN but have 773 * received FIN 774 */ 775 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 776 * waiting for FIN 777 */ 778 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 779}; 780 781enum fw_flowc_mnem_uostate { 782 FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */ 783 FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */ 784 FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, /* graceful close, after sending 785 * outstanding payload 786 */ 787 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after 788 * discarding outstanding payload 789 */ 790}; 791 792enum fw_flowc_mnem { 793 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 794 FW_FLOWC_MNEM_CH = 1, 795 FW_FLOWC_MNEM_PORT = 2, 796 FW_FLOWC_MNEM_IQID = 3, 797 FW_FLOWC_MNEM_SNDNXT = 4, 798 FW_FLOWC_MNEM_RCVNXT = 5, 799 FW_FLOWC_MNEM_SNDBUF = 6, 800 FW_FLOWC_MNEM_MSS = 7, 801 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 802 FW_FLOWC_MNEM_TCPSTATE = 9, 803 FW_FLOWC_MNEM_UOSTATE = 10, 804 FW_FLOWC_MNEM_SCHEDCLASS = 11, 805 FW_FLOWC_MNEM_DCBPRIO = 12, 806}; 807 808struct fw_flowc_mnemval { 809 __u8 mnemonic; 810 __u8 r4[3]; 811 __be32 val; 812}; 813 814struct fw_flowc_wr { 815 __be32 op_to_nparams; 816 __be32 flowid_len16; 817#ifndef C99_NOT_SUPPORTED 818 struct fw_flowc_mnemval mnemval[0]; 819#endif 820}; 821 822#define S_FW_FLOWC_WR_NPARAMS 0 823#define M_FW_FLOWC_WR_NPARAMS 0xff 824#define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 825#define G_FW_FLOWC_WR_NPARAMS(x) \ 826 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 827 828struct fw_ofld_tx_data_wr { 829 __be32 op_to_immdlen; 830 __be32 flowid_len16; 831 __be32 plen; 832 __be32 lsodisable_to_proxy; 833}; 834 835#define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 836#define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 837#define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 838 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 839#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 840 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 841 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 842#define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 843 844#define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 845#define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 846#define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 847 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 848#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 849 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 850#define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 851 852#define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 853#define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 854#define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 855 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 856#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 857 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 858 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 859#define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 860 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 861 862#define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 863#define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 864#define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 865#define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 866 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 867#define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 868 869#define S_FW_OFLD_TX_DATA_WR_SAVE 18 870#define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 871#define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) 872#define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ 873 (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) 874#define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) 875 876#define S_FW_OFLD_TX_DATA_WR_FLUSH 17 877#define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 878#define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) 879#define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ 880 (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) 881#define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) 882 883#define S_FW_OFLD_TX_DATA_WR_URGENT 16 884#define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 885#define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) 886#define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ 887 (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) 888#define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) 889 890#define S_FW_OFLD_TX_DATA_WR_MORE 15 891#define M_FW_OFLD_TX_DATA_WR_MORE 0x1 892#define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) 893#define G_FW_OFLD_TX_DATA_WR_MORE(x) \ 894 (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) 895#define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) 896 897#define S_FW_OFLD_TX_DATA_WR_SHOVE 14 898#define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 899#define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) 900#define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ 901 (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) 902#define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) 903 904#define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 905#define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf 906#define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) 907#define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ 908 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) 909 910#define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 911#define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf 912#define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 913 ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 914#define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 915 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ 916 M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 917 918#define S_FW_OFLD_TX_DATA_WR_PROXY 5 919#define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 920#define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) 921#define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ 922 (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) 923#define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) 924 925struct fw_cmd_wr { 926 __be32 op_dma; 927 __be32 len16_pkd; 928 __be64 cookie_daddr; 929}; 930 931#define S_FW_CMD_WR_DMA 17 932#define M_FW_CMD_WR_DMA 0x1 933#define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 934#define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 935#define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 936 937struct fw_eth_tx_pkt_vm_wr { 938 __be32 op_immdlen; 939 __be32 equiq_to_len16; 940 __be32 r3[2]; 941 __u8 ethmacdst[6]; 942 __u8 ethmacsrc[6]; 943 __be16 ethtype; 944 __be16 vlantci; 945}; 946 947/****************************************************************************** 948 * R I W O R K R E Q U E S T s 949 **************************************/ 950 951enum fw_ri_wr_opcode { 952 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 953 FW_RI_READ_REQ = 0x1, 954 FW_RI_READ_RESP = 0x2, 955 FW_RI_SEND = 0x3, 956 FW_RI_SEND_WITH_INV = 0x4, 957 FW_RI_SEND_WITH_SE = 0x5, 958 FW_RI_SEND_WITH_SE_INV = 0x6, 959 FW_RI_TERMINATE = 0x7, 960 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 961 FW_RI_BIND_MW = 0x9, 962 FW_RI_FAST_REGISTER = 0xa, 963 FW_RI_LOCAL_INV = 0xb, 964 FW_RI_QP_MODIFY = 0xc, 965 FW_RI_BYPASS = 0xd, 966 FW_RI_RECEIVE = 0xe, 967#if 0 968 FW_RI_SEND_IMMEDIATE = 0x8, 969 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 970 FW_RI_ATOMIC_REQUEST = 0xa, 971 FW_RI_ATOMIC_RESPONSE = 0xb, 972 973 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 974 FW_RI_FAST_REGISTER = 0xd, 975 FW_RI_LOCAL_INV = 0xe, 976#endif 977 FW_RI_SGE_EC_CR_RETURN = 0xf 978}; 979 980enum fw_ri_wr_flags { 981 FW_RI_COMPLETION_FLAG = 0x01, 982 FW_RI_NOTIFICATION_FLAG = 0x02, 983 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 984 FW_RI_READ_FENCE_FLAG = 0x08, 985 FW_RI_LOCAL_FENCE_FLAG = 0x10, 986 FW_RI_RDMA_READ_INVALIDATE = 0x20 987}; 988 989enum fw_ri_mpa_attrs { 990 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 991 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 992 FW_RI_MPA_CRC_ENABLE = 0x04, 993 FW_RI_MPA_IETF_ENABLE = 0x08 994}; 995 996enum fw_ri_qp_caps { 997 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 998 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 999 FW_RI_QP_BIND_ENABLE = 0x04, 1000 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1001 FW_RI_QP_STAG0_ENABLE = 0x10, 1002 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1003}; 1004 1005enum fw_ri_addr_type { 1006 FW_RI_ZERO_BASED_TO = 0x00, 1007 FW_RI_VA_BASED_TO = 0x01 1008}; 1009 1010enum fw_ri_mem_perms { 1011 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1012 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1013 FW_RI_MEM_ACCESS_REM = 0x03, 1014 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1015 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1016 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1017}; 1018 1019enum fw_ri_stag_type { 1020 FW_RI_STAG_NSMR = 0x00, 1021 FW_RI_STAG_SMR = 0x01, 1022 FW_RI_STAG_MW = 0x02, 1023 FW_RI_STAG_MW_RELAXED = 0x03 1024}; 1025 1026enum fw_ri_data_op { 1027 FW_RI_DATA_IMMD = 0x81, 1028 FW_RI_DATA_DSGL = 0x82, 1029 FW_RI_DATA_ISGL = 0x83 1030}; 1031 1032enum fw_ri_sgl_depth { 1033 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1034 FW_RI_SGL_DEPTH_MAX_RQ = 4 1035}; 1036 1037enum fw_ri_cqe_err { 1038 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1039 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1040 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1041 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1042 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1043 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1044 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1045 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1046 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1047 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1048 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1049 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1050 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1051 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1052 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1053 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1054 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1055 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1056 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1057 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1058 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1059 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1060 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1061 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1062 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1063 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1064 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1065 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1066 1067}; 1068 1069struct fw_ri_dsge_pair { 1070 __be32 len[2]; 1071 __be64 addr[2]; 1072}; 1073 1074struct fw_ri_dsgl { 1075 __u8 op; 1076 __u8 r1; 1077 __be16 nsge; 1078 __be32 len0; 1079 __be64 addr0; 1080#ifndef C99_NOT_SUPPORTED 1081 struct fw_ri_dsge_pair sge[0]; 1082#endif 1083}; 1084 1085struct fw_ri_sge { 1086 __be32 stag; 1087 __be32 len; 1088 __be64 to; 1089}; 1090 1091struct fw_ri_isgl { 1092 __u8 op; 1093 __u8 r1; 1094 __be16 nsge; 1095 __be32 r2; 1096#ifndef C99_NOT_SUPPORTED 1097 struct fw_ri_sge sge[0]; 1098#endif 1099}; 1100 1101struct fw_ri_immd { 1102 __u8 op; 1103 __u8 r1; 1104 __be16 r2; 1105 __be32 immdlen; 1106#ifndef C99_NOT_SUPPORTED 1107 __u8 data[0]; 1108#endif 1109}; 1110 1111struct fw_ri_tpte { 1112 __be32 valid_to_pdid; 1113 __be32 locread_to_qpid; 1114 __be32 nosnoop_pbladdr; 1115 __be32 len_lo; 1116 __be32 va_hi; 1117 __be32 va_lo_fbo; 1118 __be32 dca_mwbcnt_pstag; 1119 __be32 len_hi; 1120}; 1121 1122#define S_FW_RI_TPTE_VALID 31 1123#define M_FW_RI_TPTE_VALID 0x1 1124#define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1125#define G_FW_RI_TPTE_VALID(x) \ 1126 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1127#define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1128 1129#define S_FW_RI_TPTE_STAGKEY 23 1130#define M_FW_RI_TPTE_STAGKEY 0xff 1131#define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1132#define G_FW_RI_TPTE_STAGKEY(x) \ 1133 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1134 1135#define S_FW_RI_TPTE_STAGSTATE 22 1136#define M_FW_RI_TPTE_STAGSTATE 0x1 1137#define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1138#define G_FW_RI_TPTE_STAGSTATE(x) \ 1139 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1140#define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1141 1142#define S_FW_RI_TPTE_STAGTYPE 20 1143#define M_FW_RI_TPTE_STAGTYPE 0x3 1144#define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1145#define G_FW_RI_TPTE_STAGTYPE(x) \ 1146 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1147 1148#define S_FW_RI_TPTE_PDID 0 1149#define M_FW_RI_TPTE_PDID 0xfffff 1150#define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1151#define G_FW_RI_TPTE_PDID(x) \ 1152 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1153 1154#define S_FW_RI_TPTE_PERM 28 1155#define M_FW_RI_TPTE_PERM 0xf 1156#define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1157#define G_FW_RI_TPTE_PERM(x) \ 1158 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1159 1160#define S_FW_RI_TPTE_REMINVDIS 27 1161#define M_FW_RI_TPTE_REMINVDIS 0x1 1162#define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1163#define G_FW_RI_TPTE_REMINVDIS(x) \ 1164 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1165#define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1166 1167#define S_FW_RI_TPTE_ADDRTYPE 26 1168#define M_FW_RI_TPTE_ADDRTYPE 1 1169#define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1170#define G_FW_RI_TPTE_ADDRTYPE(x) \ 1171 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1172#define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1173 1174#define S_FW_RI_TPTE_MWBINDEN 25 1175#define M_FW_RI_TPTE_MWBINDEN 0x1 1176#define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1177#define G_FW_RI_TPTE_MWBINDEN(x) \ 1178 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1179#define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1180 1181#define S_FW_RI_TPTE_PS 20 1182#define M_FW_RI_TPTE_PS 0x1f 1183#define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1184#define G_FW_RI_TPTE_PS(x) \ 1185 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1186 1187#define S_FW_RI_TPTE_QPID 0 1188#define M_FW_RI_TPTE_QPID 0xfffff 1189#define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1190#define G_FW_RI_TPTE_QPID(x) \ 1191 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1192 1193#define S_FW_RI_TPTE_NOSNOOP 31 1194#define M_FW_RI_TPTE_NOSNOOP 0x1 1195#define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1196#define G_FW_RI_TPTE_NOSNOOP(x) \ 1197 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1198#define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1199 1200#define S_FW_RI_TPTE_PBLADDR 0 1201#define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1202#define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1203#define G_FW_RI_TPTE_PBLADDR(x) \ 1204 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1205 1206#define S_FW_RI_TPTE_DCA 24 1207#define M_FW_RI_TPTE_DCA 0x1f 1208#define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1209#define G_FW_RI_TPTE_DCA(x) \ 1210 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1211 1212#define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1213#define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1214#define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1215 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1216#define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1217 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1218 1219enum fw_ri_cqe_rxtx { 1220 FW_RI_CQE_RXTX_RX = 0x0, 1221 FW_RI_CQE_RXTX_TX = 0x1, 1222}; 1223 1224struct fw_ri_cqe { 1225 union fw_ri_rxtx { 1226 struct fw_ri_scqe { 1227 __be32 qpid_n_stat_rxtx_type; 1228 __be32 plen; 1229 __be32 reserved; 1230 __be32 wrid; 1231 } scqe; 1232 struct fw_ri_rcqe { 1233 __be32 qpid_n_stat_rxtx_type; 1234 __be32 plen; 1235 __be32 stag; 1236 __be32 msn; 1237 } rcqe; 1238 } u; 1239}; 1240 1241#define S_FW_RI_CQE_QPID 12 1242#define M_FW_RI_CQE_QPID 0xfffff 1243#define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1244#define G_FW_RI_CQE_QPID(x) \ 1245 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1246 1247#define S_FW_RI_CQE_NOTIFY 10 1248#define M_FW_RI_CQE_NOTIFY 0x1 1249#define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1250#define G_FW_RI_CQE_NOTIFY(x) \ 1251 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1252 1253#define S_FW_RI_CQE_STATUS 5 1254#define M_FW_RI_CQE_STATUS 0x1f 1255#define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1256#define G_FW_RI_CQE_STATUS(x) \ 1257 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1258 1259 1260#define S_FW_RI_CQE_RXTX 4 1261#define M_FW_RI_CQE_RXTX 0x1 1262#define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1263#define G_FW_RI_CQE_RXTX(x) \ 1264 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1265 1266#define S_FW_RI_CQE_TYPE 0 1267#define M_FW_RI_CQE_TYPE 0xf 1268#define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1269#define G_FW_RI_CQE_TYPE(x) \ 1270 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1271 1272enum fw_ri_res_type { 1273 FW_RI_RES_TYPE_SQ, 1274 FW_RI_RES_TYPE_RQ, 1275 FW_RI_RES_TYPE_CQ, 1276}; 1277 1278enum fw_ri_res_op { 1279 FW_RI_RES_OP_WRITE, 1280 FW_RI_RES_OP_RESET, 1281}; 1282 1283struct fw_ri_res { 1284 union fw_ri_restype { 1285 struct fw_ri_res_sqrq { 1286 __u8 restype; 1287 __u8 op; 1288 __be16 r3; 1289 __be32 eqid; 1290 __be32 r4[2]; 1291 __be32 fetchszm_to_iqid; 1292 __be32 dcaen_to_eqsize; 1293 __be64 eqaddr; 1294 } sqrq; 1295 struct fw_ri_res_cq { 1296 __u8 restype; 1297 __u8 op; 1298 __be16 r3; 1299 __be32 iqid; 1300 __be32 r4[2]; 1301 __be32 iqandst_to_iqandstindex; 1302 __be16 iqdroprss_to_iqesize; 1303 __be16 iqsize; 1304 __be64 iqaddr; 1305 __be32 iqns_iqro; 1306 __be32 r6_lo; 1307 __be64 r7; 1308 } cq; 1309 } u; 1310}; 1311 1312struct fw_ri_res_wr { 1313 __be32 op_nres; 1314 __be32 len16_pkd; 1315 __u64 cookie; 1316#ifndef C99_NOT_SUPPORTED 1317 struct fw_ri_res res[0]; 1318#endif 1319}; 1320 1321#define S_FW_RI_RES_WR_NRES 0 1322#define M_FW_RI_RES_WR_NRES 0xff 1323#define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1324#define G_FW_RI_RES_WR_NRES(x) \ 1325 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1326 1327#define S_FW_RI_RES_WR_FETCHSZM 26 1328#define M_FW_RI_RES_WR_FETCHSZM 0x1 1329#define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1330#define G_FW_RI_RES_WR_FETCHSZM(x) \ 1331 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1332#define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1333 1334#define S_FW_RI_RES_WR_STATUSPGNS 25 1335#define M_FW_RI_RES_WR_STATUSPGNS 0x1 1336#define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1337#define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1338 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1339#define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1340 1341#define S_FW_RI_RES_WR_STATUSPGRO 24 1342#define M_FW_RI_RES_WR_STATUSPGRO 0x1 1343#define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1344#define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1345 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1346#define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1347 1348#define S_FW_RI_RES_WR_FETCHNS 23 1349#define M_FW_RI_RES_WR_FETCHNS 0x1 1350#define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1351#define G_FW_RI_RES_WR_FETCHNS(x) \ 1352 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1353#define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1354 1355#define S_FW_RI_RES_WR_FETCHRO 22 1356#define M_FW_RI_RES_WR_FETCHRO 0x1 1357#define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1358#define G_FW_RI_RES_WR_FETCHRO(x) \ 1359 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1360#define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1361 1362#define S_FW_RI_RES_WR_HOSTFCMODE 20 1363#define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1364#define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1365#define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1366 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1367 1368#define S_FW_RI_RES_WR_CPRIO 19 1369#define M_FW_RI_RES_WR_CPRIO 0x1 1370#define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1371#define G_FW_RI_RES_WR_CPRIO(x) \ 1372 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1373#define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1374 1375#define S_FW_RI_RES_WR_ONCHIP 18 1376#define M_FW_RI_RES_WR_ONCHIP 0x1 1377#define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1378#define G_FW_RI_RES_WR_ONCHIP(x) \ 1379 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1380#define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1381 1382#define S_FW_RI_RES_WR_PCIECHN 16 1383#define M_FW_RI_RES_WR_PCIECHN 0x3 1384#define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1385#define G_FW_RI_RES_WR_PCIECHN(x) \ 1386 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1387 1388#define S_FW_RI_RES_WR_IQID 0 1389#define M_FW_RI_RES_WR_IQID 0xffff 1390#define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1391#define G_FW_RI_RES_WR_IQID(x) \ 1392 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1393 1394#define S_FW_RI_RES_WR_DCAEN 31 1395#define M_FW_RI_RES_WR_DCAEN 0x1 1396#define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1397#define G_FW_RI_RES_WR_DCAEN(x) \ 1398 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1399#define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1400 1401#define S_FW_RI_RES_WR_DCACPU 26 1402#define M_FW_RI_RES_WR_DCACPU 0x1f 1403#define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1404#define G_FW_RI_RES_WR_DCACPU(x) \ 1405 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1406 1407#define S_FW_RI_RES_WR_FBMIN 23 1408#define M_FW_RI_RES_WR_FBMIN 0x7 1409#define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1410#define G_FW_RI_RES_WR_FBMIN(x) \ 1411 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1412 1413#define S_FW_RI_RES_WR_FBMAX 20 1414#define M_FW_RI_RES_WR_FBMAX 0x7 1415#define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1416#define G_FW_RI_RES_WR_FBMAX(x) \ 1417 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1418 1419#define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1420#define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1421#define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1422#define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1423 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1424#define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1425 1426#define S_FW_RI_RES_WR_CIDXFTHRESH 16 1427#define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1428#define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1429#define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1430 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1431 1432#define S_FW_RI_RES_WR_EQSIZE 0 1433#define M_FW_RI_RES_WR_EQSIZE 0xffff 1434#define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1435#define G_FW_RI_RES_WR_EQSIZE(x) \ 1436 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1437 1438#define S_FW_RI_RES_WR_IQANDST 15 1439#define M_FW_RI_RES_WR_IQANDST 0x1 1440#define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1441#define G_FW_RI_RES_WR_IQANDST(x) \ 1442 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1443#define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1444 1445#define S_FW_RI_RES_WR_IQANUS 14 1446#define M_FW_RI_RES_WR_IQANUS 0x1 1447#define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1448#define G_FW_RI_RES_WR_IQANUS(x) \ 1449 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1450#define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1451 1452#define S_FW_RI_RES_WR_IQANUD 12 1453#define M_FW_RI_RES_WR_IQANUD 0x3 1454#define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1455#define G_FW_RI_RES_WR_IQANUD(x) \ 1456 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1457 1458#define S_FW_RI_RES_WR_IQANDSTINDEX 0 1459#define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1460#define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1461#define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1462 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1463 1464#define S_FW_RI_RES_WR_IQDROPRSS 15 1465#define M_FW_RI_RES_WR_IQDROPRSS 0x1 1466#define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1467#define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1468 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1469#define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1470 1471#define S_FW_RI_RES_WR_IQGTSMODE 14 1472#define M_FW_RI_RES_WR_IQGTSMODE 0x1 1473#define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1474#define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1475 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1476#define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1477 1478#define S_FW_RI_RES_WR_IQPCIECH 12 1479#define M_FW_RI_RES_WR_IQPCIECH 0x3 1480#define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1481#define G_FW_RI_RES_WR_IQPCIECH(x) \ 1482 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1483 1484#define S_FW_RI_RES_WR_IQDCAEN 11 1485#define M_FW_RI_RES_WR_IQDCAEN 0x1 1486#define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1487#define G_FW_RI_RES_WR_IQDCAEN(x) \ 1488 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1489#define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1490 1491#define S_FW_RI_RES_WR_IQDCACPU 6 1492#define M_FW_RI_RES_WR_IQDCACPU 0x1f 1493#define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1494#define G_FW_RI_RES_WR_IQDCACPU(x) \ 1495 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1496 1497#define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1498#define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1499#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1500 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1501#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1502 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1503 1504#define S_FW_RI_RES_WR_IQO 3 1505#define M_FW_RI_RES_WR_IQO 0x1 1506#define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1507#define G_FW_RI_RES_WR_IQO(x) \ 1508 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1509#define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1510 1511#define S_FW_RI_RES_WR_IQCPRIO 2 1512#define M_FW_RI_RES_WR_IQCPRIO 0x1 1513#define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1514#define G_FW_RI_RES_WR_IQCPRIO(x) \ 1515 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1516#define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1517 1518#define S_FW_RI_RES_WR_IQESIZE 0 1519#define M_FW_RI_RES_WR_IQESIZE 0x3 1520#define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1521#define G_FW_RI_RES_WR_IQESIZE(x) \ 1522 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1523 1524#define S_FW_RI_RES_WR_IQNS 31 1525#define M_FW_RI_RES_WR_IQNS 0x1 1526#define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1527#define G_FW_RI_RES_WR_IQNS(x) \ 1528 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1529#define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1530 1531#define S_FW_RI_RES_WR_IQRO 30 1532#define M_FW_RI_RES_WR_IQRO 0x1 1533#define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1534#define G_FW_RI_RES_WR_IQRO(x) \ 1535 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1536#define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1537 1538struct fw_ri_rdma_write_wr { 1539 __u8 opcode; 1540 __u8 flags; 1541 __u16 wrid; 1542 __u8 r1[3]; 1543 __u8 len16; 1544 __be64 r2; 1545 __be32 plen; 1546 __be32 stag_sink; 1547 __be64 to_sink; 1548#ifndef C99_NOT_SUPPORTED 1549 union { 1550 struct fw_ri_immd immd_src[0]; 1551 struct fw_ri_isgl isgl_src[0]; 1552 } u; 1553#endif 1554}; 1555 1556struct fw_ri_send_wr { 1557 __u8 opcode; 1558 __u8 flags; 1559 __u16 wrid; 1560 __u8 r1[3]; 1561 __u8 len16; 1562 __be32 sendop_pkd; 1563 __be32 stag_inv; 1564 __be32 plen; 1565 __be32 r3; 1566 __be64 r4; 1567#ifndef C99_NOT_SUPPORTED 1568 union { 1569 struct fw_ri_immd immd_src[0]; 1570 struct fw_ri_isgl isgl_src[0]; 1571 } u; 1572#endif 1573}; 1574 1575#define S_FW_RI_SEND_WR_SENDOP 0 1576#define M_FW_RI_SEND_WR_SENDOP 0xf 1577#define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1578#define G_FW_RI_SEND_WR_SENDOP(x) \ 1579 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1580 1581struct fw_ri_rdma_read_wr { 1582 __u8 opcode; 1583 __u8 flags; 1584 __u16 wrid; 1585 __u8 r1[3]; 1586 __u8 len16; 1587 __be64 r2; 1588 __be32 stag_sink; 1589 __be32 to_sink_hi; 1590 __be32 to_sink_lo; 1591 __be32 plen; 1592 __be32 stag_src; 1593 __be32 to_src_hi; 1594 __be32 to_src_lo; 1595 __be32 r5; 1596}; 1597 1598struct fw_ri_recv_wr { 1599 __u8 opcode; 1600 __u8 r1; 1601 __u16 wrid; 1602 __u8 r2[3]; 1603 __u8 len16; 1604 struct fw_ri_isgl isgl; 1605}; 1606 1607struct fw_ri_bind_mw_wr { 1608 __u8 opcode; 1609 __u8 flags; 1610 __u16 wrid; 1611 __u8 r1[3]; 1612 __u8 len16; 1613 __u8 qpbinde_to_dcacpu; 1614 __u8 pgsz_shift; 1615 __u8 addr_type; 1616 __u8 mem_perms; 1617 __be32 stag_mr; 1618 __be32 stag_mw; 1619 __be32 r3; 1620 __be64 len_mw; 1621 __be64 va_fbo; 1622 __be64 r4; 1623}; 1624 1625#define S_FW_RI_BIND_MW_WR_QPBINDE 6 1626#define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1627#define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1628#define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1629 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1630#define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1631 1632#define S_FW_RI_BIND_MW_WR_NS 5 1633#define M_FW_RI_BIND_MW_WR_NS 0x1 1634#define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1635#define G_FW_RI_BIND_MW_WR_NS(x) \ 1636 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1637#define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1638 1639#define S_FW_RI_BIND_MW_WR_DCACPU 0 1640#define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1641#define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1642#define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1643 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1644 1645struct fw_ri_fr_nsmr_wr { 1646 __u8 opcode; 1647 __u8 flags; 1648 __u16 wrid; 1649 __u8 r1[3]; 1650 __u8 len16; 1651 __u8 qpbinde_to_dcacpu; 1652 __u8 pgsz_shift; 1653 __u8 addr_type; 1654 __u8 mem_perms; 1655 __be32 stag; 1656 __be32 len_hi; 1657 __be32 len_lo; 1658 __be32 va_hi; 1659 __be32 va_lo_fbo; 1660}; 1661 1662#define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1663#define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1664#define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1665#define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1666 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1667#define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1668 1669#define S_FW_RI_FR_NSMR_WR_NS 5 1670#define M_FW_RI_FR_NSMR_WR_NS 0x1 1671#define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1672#define G_FW_RI_FR_NSMR_WR_NS(x) \ 1673 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1674#define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1675 1676#define S_FW_RI_FR_NSMR_WR_DCACPU 0 1677#define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1678#define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1679#define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1680 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1681 1682struct fw_ri_inv_lstag_wr { 1683 __u8 opcode; 1684 __u8 flags; 1685 __u16 wrid; 1686 __u8 r1[3]; 1687 __u8 len16; 1688 __be32 r2; 1689 __be32 stag_inv; 1690}; 1691 1692struct fw_ri_send_immediate_wr { 1693 __u8 opcode; 1694 __u8 flags; 1695 __u16 wrid; 1696 __u8 r1[3]; 1697 __u8 len16; 1698 __be32 sendimmop_pkd; 1699 __be32 r3; 1700 __be32 plen; 1701 __be32 r4; 1702 __be64 r5; 1703#ifndef C99_NOT_SUPPORTED 1704 struct fw_ri_immd immd_src[0]; 1705#endif 1706}; 1707 1708#define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1709#define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1710#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1711 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1712#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1713 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1714 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1715 1716enum fw_ri_atomic_op { 1717 FW_RI_ATOMIC_OP_FETCHADD, 1718 FW_RI_ATOMIC_OP_SWAP, 1719 FW_RI_ATOMIC_OP_CMDSWAP, 1720}; 1721 1722struct fw_ri_atomic_wr { 1723 __u8 opcode; 1724 __u8 flags; 1725 __u16 wrid; 1726 __u8 r1[3]; 1727 __u8 len16; 1728 __be32 atomicop_pkd; 1729 __be64 r3; 1730 __be32 aopcode_pkd; 1731 __be32 reqid; 1732 __be32 stag; 1733 __be32 to_hi; 1734 __be32 to_lo; 1735 __be32 addswap_data_hi; 1736 __be32 addswap_data_lo; 1737 __be32 addswap_mask_hi; 1738 __be32 addswap_mask_lo; 1739 __be32 compare_data_hi; 1740 __be32 compare_data_lo; 1741 __be32 compare_mask_hi; 1742 __be32 compare_mask_lo; 1743 __be32 r5; 1744}; 1745 1746#define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1747#define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1748#define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1749#define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1750 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1751 1752#define S_FW_RI_ATOMIC_WR_AOPCODE 0 1753#define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1754#define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1755#define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1756 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1757 1758enum fw_ri_type { 1759 FW_RI_TYPE_INIT, 1760 FW_RI_TYPE_FINI, 1761 FW_RI_TYPE_TERMINATE 1762}; 1763 1764enum fw_ri_init_p2ptype { 1765 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1766 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1767 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1768 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1769 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1770 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1771 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1772}; 1773 1774struct fw_ri_wr { 1775 __be32 op_compl; 1776 __be32 flowid_len16; 1777 __u64 cookie; 1778 union fw_ri { 1779 struct fw_ri_init { 1780 __u8 type; 1781 __u8 mpareqbit_p2ptype; 1782 __u8 r4[2]; 1783 __u8 mpa_attrs; 1784 __u8 qp_caps; 1785 __be16 nrqe; 1786 __be32 pdid; 1787 __be32 qpid; 1788 __be32 sq_eqid; 1789 __be32 rq_eqid; 1790 __be32 scqid; 1791 __be32 rcqid; 1792 __be32 ord_max; 1793 __be32 ird_max; 1794 __be32 iss; 1795 __be32 irs; 1796 __be32 hwrqsize; 1797 __be32 hwrqaddr; 1798 __be64 r5; 1799 union fw_ri_init_p2p { 1800 struct fw_ri_rdma_write_wr write; 1801 struct fw_ri_rdma_read_wr read; 1802 struct fw_ri_send_wr send; 1803 } u; 1804 } init; 1805 struct fw_ri_fini { 1806 __u8 type; 1807 __u8 r3[7]; 1808 __be64 r4; 1809 } fini; 1810 struct fw_ri_terminate { 1811 __u8 type; 1812 __u8 r3[3]; 1813 __be32 immdlen; 1814 __u8 termmsg[40]; 1815 } terminate; 1816 } u; 1817}; 1818 1819#define S_FW_RI_WR_MPAREQBIT 7 1820#define M_FW_RI_WR_MPAREQBIT 0x1 1821#define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1822#define G_FW_RI_WR_MPAREQBIT(x) \ 1823 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1824#define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1825 1826#define S_FW_RI_WR_0BRRBIT 6 1827#define M_FW_RI_WR_0BRRBIT 0x1 1828#define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1829#define G_FW_RI_WR_0BRRBIT(x) \ 1830 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1831#define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1832 1833#define S_FW_RI_WR_P2PTYPE 0 1834#define M_FW_RI_WR_P2PTYPE 0xf 1835#define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1836#define G_FW_RI_WR_P2PTYPE(x) \ 1837 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1838 1839/****************************************************************************** 1840 * F O i S C S I W O R K R E Q U E S T s 1841 *********************************************/ 1842 1843#define FW_FOISCSI_NAME_MAX_LEN 224 1844#define FW_FOISCSI_ALIAS_MAX_LEN 224 1845#define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 1846#define FW_FOISCSI_INIT_NODE_MAX 8 1847 1848enum fw_chnet_ifconf_wr_subop { 1849 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1850 1851 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1852 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1853 1854 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1855 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1856 1857 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1858 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1859 1860 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1861 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1862 1863 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1864 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1865 1866 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1867 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1868 1869 FW_CHNET_IFCONF_WR_SUBOP_MAX, 1870}; 1871 1872struct fw_chnet_ifconf_wr { 1873 __be32 op_compl; 1874 __be32 flowid_len16; 1875 __be64 cookie; 1876 __be32 if_flowid; 1877 __u8 idx; 1878 __u8 subop; 1879 __u8 retval; 1880 __u8 r2; 1881 __be64 r3; 1882 struct fw_chnet_ifconf_params { 1883 __be32 r0; 1884 __be16 vlanid; 1885 __be16 mtu; 1886 union fw_chnet_ifconf_addr_type { 1887 struct fw_chnet_ifconf_ipv4 { 1888 __be32 addr; 1889 __be32 mask; 1890 __be32 router; 1891 __be32 r0; 1892 __be64 r1; 1893 } ipv4; 1894 struct fw_chnet_ifconf_ipv6 { 1895 __be64 linklocal_lo; 1896 __be64 linklocal_hi; 1897 __be64 router_hi; 1898 __be64 router_lo; 1899 __be64 aconf_hi; 1900 __be64 aconf_lo; 1901 __be64 linklocal_aconf_hi; 1902 __be64 linklocal_aconf_lo; 1903 __be64 router_aconf_hi; 1904 __be64 router_aconf_lo; 1905 __be64 r0; 1906 } ipv6; 1907 } in_attr; 1908 } param; 1909}; 1910 1911enum fw_foiscsi_node_type { 1912 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 1913 FW_FOISCSI_NODE_TYPE_TARGET, 1914}; 1915 1916enum fw_foiscsi_session_type { 1917 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 1918 FW_FOISCSI_SESSION_TYPE_NORMAL, 1919}; 1920 1921enum fw_foiscsi_auth_policy { 1922 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 1923 FW_FOISCSI_AUTH_POLICY_MUTUAL, 1924}; 1925 1926enum fw_foiscsi_auth_method { 1927 FW_FOISCSI_AUTH_METHOD_NONE = 0, 1928 FW_FOISCSI_AUTH_METHOD_CHAP, 1929 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 1930 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 1931}; 1932 1933enum fw_foiscsi_digest_type { 1934 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 1935 FW_FOISCSI_DIGEST_TYPE_CRC32, 1936 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 1937 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 1938}; 1939 1940enum fw_foiscsi_wr_subop { 1941 FW_FOISCSI_WR_SUBOP_ADD = 1, 1942 FW_FOISCSI_WR_SUBOP_DEL = 2, 1943 FW_FOISCSI_WR_SUBOP_MOD = 4, 1944}; 1945 1946enum fw_foiscsi_ctrl_state { 1947 FW_FOISCSI_CTRL_STATE_FREE = 0, 1948 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 1949 FW_FOISCSI_CTRL_STATE_FAILED, 1950 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 1951 FW_FOISCSI_CTRL_STATE_REDIRECT, 1952}; 1953 1954struct fw_rdev_wr { 1955 __be32 op_to_immdlen; 1956 __be32 alloc_to_len16; 1957 __be64 cookie; 1958 __u8 protocol; 1959 __u8 event_cause; 1960 __u8 cur_state; 1961 __u8 prev_state; 1962 __be32 flags_to_assoc_flowid; 1963 union rdev_entry { 1964 struct fcoe_rdev_entry { 1965 __be32 flowid; 1966 __u8 protocol; 1967 __u8 event_cause; 1968 __u8 flags; 1969 __u8 rjt_reason; 1970 __u8 cur_login_st; 1971 __u8 prev_login_st; 1972 __be16 rcv_fr_sz; 1973 __u8 rd_xfer_rdy_to_rport_type; 1974 __u8 vft_to_qos; 1975 __u8 org_proc_assoc_to_acc_rsp_code; 1976 __u8 enh_disc_to_tgt; 1977 __u8 wwnn[8]; 1978 __u8 wwpn[8]; 1979 __be16 iqid; 1980 __u8 fc_oui[3]; 1981 __u8 r_id[3]; 1982 } fcoe_rdev; 1983 struct iscsi_rdev_entry { 1984 __be32 flowid; 1985 __u8 protocol; 1986 __u8 event_cause; 1987 __u8 flags; 1988 __u8 r3; 1989 __be16 iscsi_opts; 1990 __be16 tcp_opts; 1991 __be16 ip_opts; 1992 __be16 max_rcv_len; 1993 __be16 max_snd_len; 1994 __be16 first_brst_len; 1995 __be16 max_brst_len; 1996 __be16 r4; 1997 __be16 def_time2wait; 1998 __be16 def_time2ret; 1999 __be16 nop_out_intrvl; 2000 __be16 non_scsi_to; 2001 __be16 isid; 2002 __be16 tsid; 2003 __be16 port; 2004 __be16 tpgt; 2005 __u8 r5[6]; 2006 __be16 iqid; 2007 } iscsi_rdev; 2008 } u; 2009}; 2010 2011#define S_FW_RDEV_WR_IMMDLEN 0 2012#define M_FW_RDEV_WR_IMMDLEN 0xff 2013#define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2014#define G_FW_RDEV_WR_IMMDLEN(x) \ 2015 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2016 2017#define S_FW_RDEV_WR_ALLOC 31 2018#define M_FW_RDEV_WR_ALLOC 0x1 2019#define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2020#define G_FW_RDEV_WR_ALLOC(x) \ 2021 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2022#define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2023 2024#define S_FW_RDEV_WR_FREE 30 2025#define M_FW_RDEV_WR_FREE 0x1 2026#define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2027#define G_FW_RDEV_WR_FREE(x) \ 2028 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2029#define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2030 2031#define S_FW_RDEV_WR_MODIFY 29 2032#define M_FW_RDEV_WR_MODIFY 0x1 2033#define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2034#define G_FW_RDEV_WR_MODIFY(x) \ 2035 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2036#define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2037 2038#define S_FW_RDEV_WR_FLOWID 8 2039#define M_FW_RDEV_WR_FLOWID 0xfffff 2040#define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2041#define G_FW_RDEV_WR_FLOWID(x) \ 2042 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2043 2044#define S_FW_RDEV_WR_LEN16 0 2045#define M_FW_RDEV_WR_LEN16 0xff 2046#define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2047#define G_FW_RDEV_WR_LEN16(x) \ 2048 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2049 2050#define S_FW_RDEV_WR_FLAGS 24 2051#define M_FW_RDEV_WR_FLAGS 0xff 2052#define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2053#define G_FW_RDEV_WR_FLAGS(x) \ 2054 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2055 2056#define S_FW_RDEV_WR_GET_NEXT 20 2057#define M_FW_RDEV_WR_GET_NEXT 0xf 2058#define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2059#define G_FW_RDEV_WR_GET_NEXT(x) \ 2060 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2061 2062#define S_FW_RDEV_WR_ASSOC_FLOWID 0 2063#define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2064#define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2065#define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2066 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2067 2068#define S_FW_RDEV_WR_RJT 7 2069#define M_FW_RDEV_WR_RJT 0x1 2070#define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2071#define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2072#define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2073 2074#define S_FW_RDEV_WR_REASON 0 2075#define M_FW_RDEV_WR_REASON 0x7f 2076#define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2077#define G_FW_RDEV_WR_REASON(x) \ 2078 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2079 2080#define S_FW_RDEV_WR_RD_XFER_RDY 7 2081#define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2082#define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2083#define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2084 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2085#define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2086 2087#define S_FW_RDEV_WR_WR_XFER_RDY 6 2088#define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2089#define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2090#define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2091 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2092#define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2093 2094#define S_FW_RDEV_WR_FC_SP 5 2095#define M_FW_RDEV_WR_FC_SP 0x1 2096#define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2097#define G_FW_RDEV_WR_FC_SP(x) \ 2098 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2099#define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2100 2101#define S_FW_RDEV_WR_RPORT_TYPE 0 2102#define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2103#define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2104#define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2105 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2106 2107#define S_FW_RDEV_WR_VFT 7 2108#define M_FW_RDEV_WR_VFT 0x1 2109#define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2110#define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2111#define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2112 2113#define S_FW_RDEV_WR_NPIV 6 2114#define M_FW_RDEV_WR_NPIV 0x1 2115#define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2116#define G_FW_RDEV_WR_NPIV(x) \ 2117 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2118#define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2119 2120#define S_FW_RDEV_WR_CLASS 4 2121#define M_FW_RDEV_WR_CLASS 0x3 2122#define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2123#define G_FW_RDEV_WR_CLASS(x) \ 2124 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2125 2126#define S_FW_RDEV_WR_SEQ_DEL 3 2127#define M_FW_RDEV_WR_SEQ_DEL 0x1 2128#define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2129#define G_FW_RDEV_WR_SEQ_DEL(x) \ 2130 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2131#define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2132 2133#define S_FW_RDEV_WR_PRIO_PREEMP 2 2134#define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2135#define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2136#define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2137 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2138#define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2139 2140#define S_FW_RDEV_WR_PREF 1 2141#define M_FW_RDEV_WR_PREF 0x1 2142#define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2143#define G_FW_RDEV_WR_PREF(x) \ 2144 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2145#define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2146 2147#define S_FW_RDEV_WR_QOS 0 2148#define M_FW_RDEV_WR_QOS 0x1 2149#define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2150#define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2151#define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2152 2153#define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2154#define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2155#define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2156#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2157 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2158#define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2159 2160#define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2161#define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2162#define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2163#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2164 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2165#define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2166 2167#define S_FW_RDEV_WR_IMAGE_PAIR 5 2168#define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2169#define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2170#define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2171 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2172#define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2173 2174#define S_FW_RDEV_WR_ACC_RSP_CODE 0 2175#define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2176#define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2177#define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2178 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2179 2180#define S_FW_RDEV_WR_ENH_DISC 7 2181#define M_FW_RDEV_WR_ENH_DISC 0x1 2182#define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2183#define G_FW_RDEV_WR_ENH_DISC(x) \ 2184 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2185#define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2186 2187#define S_FW_RDEV_WR_REC 6 2188#define M_FW_RDEV_WR_REC 0x1 2189#define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2190#define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2191#define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2192 2193#define S_FW_RDEV_WR_TASK_RETRY_ID 5 2194#define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2195#define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2196#define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2197 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2198#define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2199 2200#define S_FW_RDEV_WR_RETRY 4 2201#define M_FW_RDEV_WR_RETRY 0x1 2202#define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2203#define G_FW_RDEV_WR_RETRY(x) \ 2204 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2205#define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2206 2207#define S_FW_RDEV_WR_CONF_CMPL 3 2208#define M_FW_RDEV_WR_CONF_CMPL 0x1 2209#define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2210#define G_FW_RDEV_WR_CONF_CMPL(x) \ 2211 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2212#define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2213 2214#define S_FW_RDEV_WR_DATA_OVLY 2 2215#define M_FW_RDEV_WR_DATA_OVLY 0x1 2216#define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2217#define G_FW_RDEV_WR_DATA_OVLY(x) \ 2218 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2219#define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2220 2221#define S_FW_RDEV_WR_INI 1 2222#define M_FW_RDEV_WR_INI 0x1 2223#define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2224#define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2225#define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2226 2227#define S_FW_RDEV_WR_TGT 0 2228#define M_FW_RDEV_WR_TGT 0x1 2229#define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2230#define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2231#define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2232 2233struct fw_foiscsi_node_wr { 2234 __be32 op_to_immdlen; 2235 __be32 flowid_len16; 2236 __u64 cookie; 2237 __u8 subop; 2238 __u8 status; 2239 __u8 alias_len; 2240 __u8 iqn_len; 2241 __be32 node_flowid; 2242 __be16 nodeid; 2243 __be16 login_retry; 2244 __be16 retry_timeout; 2245 __be16 r3; 2246 __u8 iqn[224]; 2247 __u8 alias[224]; 2248}; 2249 2250#define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2251#define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2252#define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2253#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2254 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2255 2256struct fw_foiscsi_ctrl_wr { 2257 __be32 op_compl; 2258 __be32 flowid_len16; 2259 __u64 cookie; 2260 __u8 subop; 2261 __u8 status; 2262 __u8 ctrl_state; 2263 __u8 io_state; 2264 __be32 node_id; 2265 __be32 ctrl_id; 2266 __be32 io_id; 2267 struct fw_foiscsi_sess_attr { 2268 __be32 sess_type_to_erl; 2269 __be16 max_conn; 2270 __be16 max_r2t; 2271 __be16 time2wait; 2272 __be16 time2retain; 2273 __be32 max_burst; 2274 __be32 first_burst; 2275 __be32 r1; 2276 } sess_attr; 2277 struct fw_foiscsi_conn_attr { 2278 __be32 hdigest_to_ddp_pgsz; 2279 __be32 max_rcv_dsl; 2280 __be32 ping_tmo; 2281 __be16 dst_port; 2282 __be16 src_port; 2283 union fw_foiscsi_conn_attr_addr { 2284 struct fw_foiscsi_conn_attr_ipv6 { 2285 __be64 dst_addr[2]; 2286 __be64 src_addr[2]; 2287 } ipv6_addr; 2288 struct fw_foiscsi_conn_attr_ipv4 { 2289 __be32 dst_addr; 2290 __be32 src_addr; 2291 } ipv4_addr; 2292 } u; 2293 } conn_attr; 2294 __u8 tgt_name_len; 2295 __u8 r3[7]; 2296 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2297}; 2298 2299#define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2300#define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2301#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2302 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2303#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2304 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2305 2306#define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2307#define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2308#define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2309 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2310#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2311 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2312 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2313#define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2314 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2315 2316#define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2317#define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2318#define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2319 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2320#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2321 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2322 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2323#define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2324 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2325 2326#define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2327#define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2328#define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2329 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2330#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2331 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2332 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2333#define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2334 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2335 2336#define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2337#define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2338#define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2339 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2340#define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2341 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2342 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2343#define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2344 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2345 2346#define S_FW_FOISCSI_CTRL_WR_ERL 24 2347#define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2348#define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2349#define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2350 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2351 2352#define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2353#define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2354#define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2355#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2356 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2357 2358#define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2359#define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2360#define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2361#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2362 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2363 2364#define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2365#define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2366#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2367 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2368#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2369 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2370 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2371 2372#define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2373#define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2374#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2375 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2376#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2377 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2378 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2379 2380#define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2381#define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2382#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2383 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2384#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2385 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2386 2387struct fw_foiscsi_chap_wr { 2388 __be32 op_compl; 2389 __be32 flowid_len16; 2390 __u64 cookie; 2391 __u8 status; 2392 __u8 id_len; 2393 __u8 sec_len; 2394 __u8 node_type; 2395 __be16 node_id; 2396 __u8 r3[2]; 2397 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2398 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2399}; 2400 2401/****************************************************************************** 2402 * F O F C O E W O R K R E Q U E S T s 2403 *******************************************/ 2404 2405struct fw_fcoe_els_ct_wr { 2406 __be32 op_immdlen; 2407 __be32 flowid_len16; 2408 __be64 cookie; 2409 __be16 iqid; 2410 __u8 tmo_val; 2411 __u8 els_ct_type; 2412 __u8 ctl_pri; 2413 __u8 cp_en_class; 2414 __be16 xfer_cnt; 2415 __u8 fl_to_sp; 2416 __u8 l_id[3]; 2417 __u8 r5; 2418 __u8 r_id[3]; 2419 __be64 rsp_dmaaddr; 2420 __be32 rsp_dmalen; 2421 __be32 r6; 2422}; 2423 2424#define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2425#define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2426#define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2427#define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2428 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2429 2430#define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2431#define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2432#define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2433#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2434 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2435 2436#define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2437#define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2438#define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2439#define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2440 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2441 2442#define S_FW_FCOE_ELS_CT_WR_LEN16 0 2443#define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2444#define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2445#define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2446 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2447 2448#define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2449#define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2450#define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2451#define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2452 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2453 2454#define S_FW_FCOE_ELS_CT_WR_CLASS 4 2455#define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2456#define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2457#define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2458 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2459 2460#define S_FW_FCOE_ELS_CT_WR_FL 2 2461#define M_FW_FCOE_ELS_CT_WR_FL 0x1 2462#define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2463#define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2464 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2465#define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2466 2467#define S_FW_FCOE_ELS_CT_WR_NPIV 1 2468#define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2469#define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2470#define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2471 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2472#define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2473 2474#define S_FW_FCOE_ELS_CT_WR_SP 0 2475#define M_FW_FCOE_ELS_CT_WR_SP 0x1 2476#define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2477#define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2478 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2479#define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2480 2481/****************************************************************************** 2482 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2483 *****************************************************************************/ 2484 2485struct fw_scsi_write_wr { 2486 __be32 op_immdlen; 2487 __be32 flowid_len16; 2488 __be64 cookie; 2489 __be16 iqid; 2490 __u8 tmo_val; 2491 __u8 use_xfer_cnt; 2492 union fw_scsi_write_priv { 2493 struct fcoe_write_priv { 2494 __u8 ctl_pri; 2495 __u8 cp_en_class; 2496 __u8 r3_lo[2]; 2497 } fcoe; 2498 struct iscsi_write_priv { 2499 __u8 r3[4]; 2500 } iscsi; 2501 } u; 2502 __be32 xfer_cnt; 2503 __be32 ini_xfer_cnt; 2504 __be64 rsp_dmaaddr; 2505 __be32 rsp_dmalen; 2506 __be32 r4; 2507}; 2508 2509#define S_FW_SCSI_WRITE_WR_OPCODE 24 2510#define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2511#define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2512#define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2513 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2514 2515#define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2516#define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2517#define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2518#define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2519 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2520 2521#define S_FW_SCSI_WRITE_WR_FLOWID 8 2522#define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2523#define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2524#define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2525 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2526 2527#define S_FW_SCSI_WRITE_WR_LEN16 0 2528#define M_FW_SCSI_WRITE_WR_LEN16 0xff 2529#define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2530#define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2531 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2532 2533#define S_FW_SCSI_WRITE_WR_CP_EN 6 2534#define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2535#define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2536#define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2537 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2538 2539#define S_FW_SCSI_WRITE_WR_CLASS 4 2540#define M_FW_SCSI_WRITE_WR_CLASS 0x3 2541#define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2542#define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2543 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2544 2545struct fw_scsi_read_wr { 2546 __be32 op_immdlen; 2547 __be32 flowid_len16; 2548 __be64 cookie; 2549 __be16 iqid; 2550 __u8 tmo_val; 2551 __u8 use_xfer_cnt; 2552 union fw_scsi_read_priv { 2553 struct fcoe_read_priv { 2554 __u8 ctl_pri; 2555 __u8 cp_en_class; 2556 __u8 r3_lo[2]; 2557 } fcoe; 2558 struct iscsi_read_priv { 2559 __u8 r3[4]; 2560 } iscsi; 2561 } u; 2562 __be32 xfer_cnt; 2563 __be32 ini_xfer_cnt; 2564 __be64 rsp_dmaaddr; 2565 __be32 rsp_dmalen; 2566 __be32 r4; 2567}; 2568 2569#define S_FW_SCSI_READ_WR_OPCODE 24 2570#define M_FW_SCSI_READ_WR_OPCODE 0xff 2571#define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2572#define G_FW_SCSI_READ_WR_OPCODE(x) \ 2573 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2574 2575#define S_FW_SCSI_READ_WR_IMMDLEN 0 2576#define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2577#define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2578#define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2579 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2580 2581#define S_FW_SCSI_READ_WR_FLOWID 8 2582#define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2583#define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2584#define G_FW_SCSI_READ_WR_FLOWID(x) \ 2585 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2586 2587#define S_FW_SCSI_READ_WR_LEN16 0 2588#define M_FW_SCSI_READ_WR_LEN16 0xff 2589#define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2590#define G_FW_SCSI_READ_WR_LEN16(x) \ 2591 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2592 2593#define S_FW_SCSI_READ_WR_CP_EN 6 2594#define M_FW_SCSI_READ_WR_CP_EN 0x3 2595#define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2596#define G_FW_SCSI_READ_WR_CP_EN(x) \ 2597 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2598 2599#define S_FW_SCSI_READ_WR_CLASS 4 2600#define M_FW_SCSI_READ_WR_CLASS 0x3 2601#define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2602#define G_FW_SCSI_READ_WR_CLASS(x) \ 2603 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2604 2605struct fw_scsi_cmd_wr { 2606 __be32 op_immdlen; 2607 __be32 flowid_len16; 2608 __be64 cookie; 2609 __be16 iqid; 2610 __u8 tmo_val; 2611 __u8 r3; 2612 union fw_scsi_cmd_priv { 2613 struct fcoe_cmd_priv { 2614 __u8 ctl_pri; 2615 __u8 cp_en_class; 2616 __u8 r4_lo[2]; 2617 } fcoe; 2618 struct iscsi_cmd_priv { 2619 __u8 r4[4]; 2620 } iscsi; 2621 } u; 2622 __u8 r5[8]; 2623 __be64 rsp_dmaaddr; 2624 __be32 rsp_dmalen; 2625 __be32 r6; 2626}; 2627 2628#define S_FW_SCSI_CMD_WR_OPCODE 24 2629#define M_FW_SCSI_CMD_WR_OPCODE 0xff 2630#define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2631#define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2632 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2633 2634#define S_FW_SCSI_CMD_WR_IMMDLEN 0 2635#define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2636#define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2637#define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2638 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2639 2640#define S_FW_SCSI_CMD_WR_FLOWID 8 2641#define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2642#define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2643#define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2644 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2645 2646#define S_FW_SCSI_CMD_WR_LEN16 0 2647#define M_FW_SCSI_CMD_WR_LEN16 0xff 2648#define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2649#define G_FW_SCSI_CMD_WR_LEN16(x) \ 2650 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2651 2652#define S_FW_SCSI_CMD_WR_CP_EN 6 2653#define M_FW_SCSI_CMD_WR_CP_EN 0x3 2654#define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2655#define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2656 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2657 2658#define S_FW_SCSI_CMD_WR_CLASS 4 2659#define M_FW_SCSI_CMD_WR_CLASS 0x3 2660#define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2661#define G_FW_SCSI_CMD_WR_CLASS(x) \ 2662 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2663 2664struct fw_scsi_abrt_cls_wr { 2665 __be32 op_immdlen; 2666 __be32 flowid_len16; 2667 __be64 cookie; 2668 __be16 iqid; 2669 __u8 tmo_val; 2670 __u8 sub_opcode_to_chk_all_io; 2671 __u8 r3[4]; 2672 __be64 t_cookie; 2673}; 2674 2675#define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2676#define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2677#define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2678#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2679 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2680 2681#define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2682#define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2683#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2684 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2685#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2686 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2687 2688#define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2689#define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2690#define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2691#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2692 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2693 2694#define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2695#define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2696#define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2697#define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2698 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2699 2700#define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2701#define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2702#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2703 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2704#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2705 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 2706 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2707 2708#define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 2709#define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 2710#define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 2711#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 2712 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 2713#define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 2714 2715#define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 2716#define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 2717#define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2718 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2719#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2720 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 2721 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2722#define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 2723 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 2724 2725struct fw_scsi_tgt_acc_wr { 2726 __be32 op_immdlen; 2727 __be32 flowid_len16; 2728 __be64 cookie; 2729 __be16 iqid; 2730 __u8 r3; 2731 __u8 use_burst_len; 2732 union fw_scsi_tgt_acc_priv { 2733 struct fcoe_tgt_acc_priv { 2734 __u8 ctl_pri; 2735 __u8 cp_en_class; 2736 __u8 r4_lo[2]; 2737 } fcoe; 2738 struct iscsi_tgt_acc_priv { 2739 __u8 r4[4]; 2740 } iscsi; 2741 } u; 2742 __be32 burst_len; 2743 __be32 rel_off; 2744 __be64 r5; 2745 __be32 r6; 2746 __be32 tot_xfer_len; 2747}; 2748 2749#define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 2750#define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 2751#define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 2752#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 2753 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 2754 2755#define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 2756#define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 2757#define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2758#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 2759 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2760 2761#define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 2762#define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 2763#define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 2764#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 2765 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 2766 2767#define S_FW_SCSI_TGT_ACC_WR_LEN16 0 2768#define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 2769#define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 2770#define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 2771 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 2772 2773#define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 2774#define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 2775#define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 2776#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 2777 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 2778 2779#define S_FW_SCSI_TGT_ACC_WR_CLASS 4 2780#define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 2781#define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 2782#define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 2783 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 2784 2785struct fw_scsi_tgt_xmit_wr { 2786 __be32 op_immdlen; 2787 __be32 flowid_len16; 2788 __be64 cookie; 2789 __be16 iqid; 2790 __u8 auto_rsp; 2791 __u8 use_xfer_cnt; 2792 union fw_scsi_tgt_xmit_priv { 2793 struct fcoe_tgt_xmit_priv { 2794 __u8 ctl_pri; 2795 __u8 cp_en_class; 2796 __u8 r3_lo[2]; 2797 } fcoe; 2798 struct iscsi_tgt_xmit_priv { 2799 __u8 r3[4]; 2800 } iscsi; 2801 } u; 2802 __be32 xfer_cnt; 2803 __be32 r4; 2804 __be64 r5; 2805 __be32 r6; 2806 __be32 tot_xfer_len; 2807}; 2808 2809#define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 2810#define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 2811#define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 2812#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 2813 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 2814 2815#define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 2816#define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 2817#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2818 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2819#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2820 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2821 2822#define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 2823#define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 2824#define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 2825#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 2826 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 2827 2828#define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 2829#define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 2830#define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 2831#define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 2832 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 2833 2834#define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 2835#define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 2836#define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 2837#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 2838 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 2839 2840#define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 2841#define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 2842#define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 2843#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 2844 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 2845 2846struct fw_scsi_tgt_rsp_wr { 2847 __be32 op_immdlen; 2848 __be32 flowid_len16; 2849 __be64 cookie; 2850 __be16 iqid; 2851 __u8 r3[2]; 2852 union fw_scsi_tgt_rsp_priv { 2853 struct fcoe_tgt_rsp_priv { 2854 __u8 ctl_pri; 2855 __u8 cp_en_class; 2856 __u8 r4_lo[2]; 2857 } fcoe; 2858 struct iscsi_tgt_rsp_priv { 2859 __u8 r4[4]; 2860 } iscsi; 2861 } u; 2862 __u8 r5[8]; 2863}; 2864 2865#define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 2866#define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 2867#define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 2868#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 2869 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 2870 2871#define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 2872#define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 2873#define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2874#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 2875 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2876 2877#define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 2878#define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 2879#define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 2880#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 2881 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 2882 2883#define S_FW_SCSI_TGT_RSP_WR_LEN16 0 2884#define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 2885#define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 2886#define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 2887 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 2888 2889#define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 2890#define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 2891#define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 2892#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 2893 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2894 2895#define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2896#define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2897#define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2898#define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2899 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2900 2901struct fw_pofcoe_tcb_wr { 2902 __be32 op_compl; 2903 __be32 equiq_to_len16; 2904 __be64 cookie; 2905 __be32 tid_to_port; 2906 __be16 x_id; 2907 __be16 vlan_id; 2908 __be32 s_id; 2909 __be32 d_id; 2910 __be32 tag; 2911 __be32 xfer_len; 2912 __be32 r4; 2913 __be16 r5; 2914 __be16 iqid; 2915}; 2916 2917#define S_FW_POFCOE_TCB_WR_TID 12 2918#define M_FW_POFCOE_TCB_WR_TID 0xfffff 2919#define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 2920#define G_FW_POFCOE_TCB_WR_TID(x) \ 2921 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 2922 2923#define S_FW_POFCOE_TCB_WR_ALLOC 4 2924#define M_FW_POFCOE_TCB_WR_ALLOC 0x1 2925#define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 2926#define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 2927 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 2928#define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 2929 2930#define S_FW_POFCOE_TCB_WR_FREE 3 2931#define M_FW_POFCOE_TCB_WR_FREE 0x1 2932#define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 2933#define G_FW_POFCOE_TCB_WR_FREE(x) \ 2934 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 2935#define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 2936 2937#define S_FW_POFCOE_TCB_WR_PORT 0 2938#define M_FW_POFCOE_TCB_WR_PORT 0x7 2939#define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 2940#define G_FW_POFCOE_TCB_WR_PORT(x) \ 2941 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 2942 2943struct fw_pofcoe_ulptx_wr { 2944 __be32 op_pkd; 2945 __be32 equiq_to_len16; 2946 __u64 cookie; 2947}; 2948 2949 2950/****************************************************************************** 2951 * C O M M A N D s 2952 *********************/ 2953 2954/* 2955 * The maximum length of time, in miliseconds, that we expect any firmware 2956 * command to take to execute and return a reply to the host. The RESET 2957 * and INITIALIZE commands can take a fair amount of time to execute but 2958 * most execute in far less time than this maximum. This constant is used 2959 * by host software to determine how long to wait for a firmware command 2960 * reply before declaring the firmware as dead/unreachable ... 2961 */ 2962#define FW_CMD_MAX_TIMEOUT 10000 2963 2964/* 2965 * If a host driver does a HELLO and discovers that there's already a MASTER 2966 * selected, we may have to wait for that MASTER to finish issuing RESET, 2967 * configuration and INITIALIZE commands. Also, there's a possibility that 2968 * our own HELLO may get lost if it happens right as the MASTER is issuign a 2969 * RESET command, so we need to be willing to make a few retries of our HELLO. 2970 */ 2971#define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 2972#define FW_CMD_HELLO_RETRIES 3 2973 2974enum fw_cmd_opcodes { 2975 FW_LDST_CMD = 0x01, 2976 FW_RESET_CMD = 0x03, 2977 FW_HELLO_CMD = 0x04, 2978 FW_BYE_CMD = 0x05, 2979 FW_INITIALIZE_CMD = 0x06, 2980 FW_CAPS_CONFIG_CMD = 0x07, 2981 FW_PARAMS_CMD = 0x08, 2982 FW_PFVF_CMD = 0x09, 2983 FW_IQ_CMD = 0x10, 2984 FW_EQ_MNGT_CMD = 0x11, 2985 FW_EQ_ETH_CMD = 0x12, 2986 FW_EQ_CTRL_CMD = 0x13, 2987 FW_EQ_OFLD_CMD = 0x21, 2988 FW_VI_CMD = 0x14, 2989 FW_VI_MAC_CMD = 0x15, 2990 FW_VI_RXMODE_CMD = 0x16, 2991 FW_VI_ENABLE_CMD = 0x17, 2992 FW_VI_STATS_CMD = 0x1a, 2993 FW_ACL_MAC_CMD = 0x18, 2994 FW_ACL_VLAN_CMD = 0x19, 2995 FW_PORT_CMD = 0x1b, 2996 FW_PORT_STATS_CMD = 0x1c, 2997 FW_PORT_LB_STATS_CMD = 0x1d, 2998 FW_PORT_TRACE_CMD = 0x1e, 2999 FW_PORT_TRACE_MMAP_CMD = 0x1f, 3000 FW_RSS_IND_TBL_CMD = 0x20, 3001 FW_RSS_GLB_CONFIG_CMD = 0x22, 3002 FW_RSS_VI_CONFIG_CMD = 0x23, 3003 FW_SCHED_CMD = 0x24, 3004 FW_DEVLOG_CMD = 0x25, 3005 FW_WATCHDOG_CMD = 0x27, 3006 FW_CLIP_CMD = 0x28, 3007 FW_CHNET_IFACE_CMD = 0x26, 3008 FW_FCOE_RES_INFO_CMD = 0x31, 3009 FW_FCOE_LINK_CMD = 0x32, 3010 FW_FCOE_VNP_CMD = 0x33, 3011 FW_FCOE_SPARAMS_CMD = 0x35, 3012 FW_FCOE_STATS_CMD = 0x37, 3013 FW_FCOE_FCF_CMD = 0x38, 3014 FW_LASTC2E_CMD = 0x40, 3015 FW_ERROR_CMD = 0x80, 3016 FW_DEBUG_CMD = 0x81, 3017}; 3018 3019enum fw_cmd_cap { 3020 FW_CMD_CAP_PF = 0x01, 3021 FW_CMD_CAP_DMAQ = 0x02, 3022 FW_CMD_CAP_PORT = 0x04, 3023 FW_CMD_CAP_PORTPROMISC = 0x08, 3024 FW_CMD_CAP_PORTSTATS = 0x10, 3025 FW_CMD_CAP_VF = 0x80, 3026}; 3027 3028/* 3029 * Generic command header flit0 3030 */ 3031struct fw_cmd_hdr { 3032 __be32 hi; 3033 __be32 lo; 3034}; 3035 3036#define S_FW_CMD_OP 24 3037#define M_FW_CMD_OP 0xff 3038#define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 3039#define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 3040 3041#define S_FW_CMD_REQUEST 23 3042#define M_FW_CMD_REQUEST 0x1 3043#define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 3044#define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 3045#define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 3046 3047#define S_FW_CMD_READ 22 3048#define M_FW_CMD_READ 0x1 3049#define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 3050#define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 3051#define F_FW_CMD_READ V_FW_CMD_READ(1U) 3052 3053#define S_FW_CMD_WRITE 21 3054#define M_FW_CMD_WRITE 0x1 3055#define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 3056#define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 3057#define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 3058 3059#define S_FW_CMD_EXEC 20 3060#define M_FW_CMD_EXEC 0x1 3061#define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 3062#define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 3063#define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 3064 3065#define S_FW_CMD_RAMASK 20 3066#define M_FW_CMD_RAMASK 0xf 3067#define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 3068#define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 3069 3070#define S_FW_CMD_RETVAL 8 3071#define M_FW_CMD_RETVAL 0xff 3072#define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 3073#define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 3074 3075#define S_FW_CMD_LEN16 0 3076#define M_FW_CMD_LEN16 0xff 3077#define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 3078#define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 3079 3080#define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 3081 3082/* 3083 * address spaces 3084 */ 3085enum fw_ldst_addrspc { 3086 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 3087 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 3088 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 3089 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 3090 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 3091 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 3092 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 3093 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 3094 FW_LDST_ADDRSPC_MDIO = 0x0018, 3095 FW_LDST_ADDRSPC_MPS = 0x0020, 3096 FW_LDST_ADDRSPC_FUNC = 0x0028, 3097 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 3098 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 3099 FW_LDST_ADDRSPC_LE = 0x0030, 3100 FW_LDST_ADDRSPC_I2C = 0x0038, 3101 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 3102 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 3103 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 3104}; 3105 3106/* 3107 * MDIO VSC8634 register access control field 3108 */ 3109enum fw_ldst_mdio_vsc8634_aid { 3110 FW_LDST_MDIO_VS_STANDARD, 3111 FW_LDST_MDIO_VS_EXTENDED, 3112 FW_LDST_MDIO_VS_GPIO 3113}; 3114 3115enum fw_ldst_mps_fid { 3116 FW_LDST_MPS_ATRB, 3117 FW_LDST_MPS_RPLC 3118}; 3119 3120enum fw_ldst_func_access_ctl { 3121 FW_LDST_FUNC_ACC_CTL_VIID, 3122 FW_LDST_FUNC_ACC_CTL_FID 3123}; 3124 3125enum fw_ldst_func_mod_index { 3126 FW_LDST_FUNC_MPS 3127}; 3128 3129struct fw_ldst_cmd { 3130 __be32 op_to_addrspace; 3131 __be32 cycles_to_len16; 3132 union fw_ldst { 3133 struct fw_ldst_addrval { 3134 __be32 addr; 3135 __be32 val; 3136 } addrval; 3137 struct fw_ldst_idctxt { 3138 __be32 physid; 3139 __be32 msg_ctxtflush; 3140 __be32 ctxt_data7; 3141 __be32 ctxt_data6; 3142 __be32 ctxt_data5; 3143 __be32 ctxt_data4; 3144 __be32 ctxt_data3; 3145 __be32 ctxt_data2; 3146 __be32 ctxt_data1; 3147 __be32 ctxt_data0; 3148 } idctxt; 3149 struct fw_ldst_mdio { 3150 __be16 paddr_mmd; 3151 __be16 raddr; 3152 __be16 vctl; 3153 __be16 rval; 3154 } mdio; 3155 struct fw_ldst_mps { 3156 __be16 fid_ctl; 3157 __be16 rplcpf_pkd; 3158 __be32 rplc127_96; 3159 __be32 rplc95_64; 3160 __be32 rplc63_32; 3161 __be32 rplc31_0; 3162 __be32 atrb; 3163 __be16 vlan[16]; 3164 } mps; 3165 struct fw_ldst_func { 3166 __u8 access_ctl; 3167 __u8 mod_index; 3168 __be16 ctl_id; 3169 __be32 offset; 3170 __be64 data0; 3171 __be64 data1; 3172 } func; 3173 struct fw_ldst_pcie { 3174 __u8 ctrl_to_fn; 3175 __u8 bnum; 3176 __u8 r; 3177 __u8 ext_r; 3178 __u8 select_naccess; 3179 __u8 pcie_fn; 3180 __be16 nset_pkd; 3181 __be32 data[12]; 3182 } pcie; 3183 struct fw_ldst_i2c_deprecated { 3184 __u8 pid_pkd; 3185 __u8 base; 3186 __u8 boffset; 3187 __u8 data; 3188 __be32 r9; 3189 } i2c_deprecated; 3190 struct fw_ldst_i2c { 3191 __u8 pid; 3192 __u8 did; 3193 __u8 boffset; 3194 __u8 blen; 3195 __be32 r9; 3196 __u8 data[48]; 3197 } i2c; 3198 struct fw_ldst_le { 3199 __be32 index; 3200 __be32 r9; 3201 __u8 val[33]; 3202 __u8 r11[7]; 3203 } le; 3204 } u; 3205}; 3206 3207#define S_FW_LDST_CMD_ADDRSPACE 0 3208#define M_FW_LDST_CMD_ADDRSPACE 0xff 3209#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3210#define G_FW_LDST_CMD_ADDRSPACE(x) \ 3211 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3212 3213#define S_FW_LDST_CMD_CYCLES 16 3214#define M_FW_LDST_CMD_CYCLES 0xffff 3215#define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3216#define G_FW_LDST_CMD_CYCLES(x) \ 3217 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3218 3219#define S_FW_LDST_CMD_MSG 31 3220#define M_FW_LDST_CMD_MSG 0x1 3221#define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3222#define G_FW_LDST_CMD_MSG(x) \ 3223 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3224#define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3225 3226#define S_FW_LDST_CMD_CTXTFLUSH 30 3227#define M_FW_LDST_CMD_CTXTFLUSH 0x1 3228#define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3229#define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3230 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3231#define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3232 3233#define S_FW_LDST_CMD_PADDR 8 3234#define M_FW_LDST_CMD_PADDR 0x1f 3235#define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3236#define G_FW_LDST_CMD_PADDR(x) \ 3237 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3238 3239#define S_FW_LDST_CMD_MMD 0 3240#define M_FW_LDST_CMD_MMD 0x1f 3241#define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3242#define G_FW_LDST_CMD_MMD(x) \ 3243 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3244 3245#define S_FW_LDST_CMD_FID 15 3246#define M_FW_LDST_CMD_FID 0x1 3247#define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3248#define G_FW_LDST_CMD_FID(x) \ 3249 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3250#define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3251 3252#define S_FW_LDST_CMD_CTL 0 3253#define M_FW_LDST_CMD_CTL 0x7fff 3254#define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) 3255#define G_FW_LDST_CMD_CTL(x) \ 3256 (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) 3257 3258#define S_FW_LDST_CMD_RPLCPF 0 3259#define M_FW_LDST_CMD_RPLCPF 0xff 3260#define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3261#define G_FW_LDST_CMD_RPLCPF(x) \ 3262 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3263 3264#define S_FW_LDST_CMD_CTRL 7 3265#define M_FW_LDST_CMD_CTRL 0x1 3266#define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3267#define G_FW_LDST_CMD_CTRL(x) \ 3268 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3269#define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3270 3271#define S_FW_LDST_CMD_LC 4 3272#define M_FW_LDST_CMD_LC 0x1 3273#define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3274#define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3275#define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3276 3277#define S_FW_LDST_CMD_AI 3 3278#define M_FW_LDST_CMD_AI 0x1 3279#define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 3280#define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 3281#define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 3282 3283#define S_FW_LDST_CMD_FN 0 3284#define M_FW_LDST_CMD_FN 0x7 3285#define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 3286#define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 3287 3288#define S_FW_LDST_CMD_SELECT 4 3289#define M_FW_LDST_CMD_SELECT 0xf 3290#define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 3291#define G_FW_LDST_CMD_SELECT(x) \ 3292 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 3293 3294#define S_FW_LDST_CMD_NACCESS 0 3295#define M_FW_LDST_CMD_NACCESS 0xf 3296#define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 3297#define G_FW_LDST_CMD_NACCESS(x) \ 3298 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 3299 3300#define S_FW_LDST_CMD_NSET 14 3301#define M_FW_LDST_CMD_NSET 0x3 3302#define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 3303#define G_FW_LDST_CMD_NSET(x) \ 3304 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 3305 3306#define S_FW_LDST_CMD_PID 6 3307#define M_FW_LDST_CMD_PID 0x3 3308#define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 3309#define G_FW_LDST_CMD_PID(x) \ 3310 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 3311 3312struct fw_reset_cmd { 3313 __be32 op_to_write; 3314 __be32 retval_len16; 3315 __be32 val; 3316 __be32 halt_pkd; 3317}; 3318 3319#define S_FW_RESET_CMD_HALT 31 3320#define M_FW_RESET_CMD_HALT 0x1 3321#define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 3322#define G_FW_RESET_CMD_HALT(x) \ 3323 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 3324#define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 3325 3326enum { 3327 FW_HELLO_CMD_STAGE_OS = 0, 3328 FW_HELLO_CMD_STAGE_PREOS0 = 1, 3329 FW_HELLO_CMD_STAGE_PREOS1 = 2, 3330 FW_HELLO_CMD_STAGE_POSTOS = 3, 3331}; 3332 3333struct fw_hello_cmd { 3334 __be32 op_to_write; 3335 __be32 retval_len16; 3336 __be32 err_to_clearinit; 3337 __be32 fwrev; 3338}; 3339 3340#define S_FW_HELLO_CMD_ERR 31 3341#define M_FW_HELLO_CMD_ERR 0x1 3342#define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 3343#define G_FW_HELLO_CMD_ERR(x) \ 3344 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 3345#define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 3346 3347#define S_FW_HELLO_CMD_INIT 30 3348#define M_FW_HELLO_CMD_INIT 0x1 3349#define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 3350#define G_FW_HELLO_CMD_INIT(x) \ 3351 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 3352#define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 3353 3354#define S_FW_HELLO_CMD_MASTERDIS 29 3355#define M_FW_HELLO_CMD_MASTERDIS 0x1 3356#define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 3357#define G_FW_HELLO_CMD_MASTERDIS(x) \ 3358 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 3359#define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 3360 3361#define S_FW_HELLO_CMD_MASTERFORCE 28 3362#define M_FW_HELLO_CMD_MASTERFORCE 0x1 3363#define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 3364#define G_FW_HELLO_CMD_MASTERFORCE(x) \ 3365 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 3366#define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 3367 3368#define S_FW_HELLO_CMD_MBMASTER 24 3369#define M_FW_HELLO_CMD_MBMASTER 0xf 3370#define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 3371#define G_FW_HELLO_CMD_MBMASTER(x) \ 3372 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 3373 3374#define S_FW_HELLO_CMD_MBASYNCNOTINT 23 3375#define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 3376#define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 3377#define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 3378 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 3379#define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 3380 3381#define S_FW_HELLO_CMD_MBASYNCNOT 20 3382#define M_FW_HELLO_CMD_MBASYNCNOT 0x7 3383#define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 3384#define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 3385 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 3386 3387#define S_FW_HELLO_CMD_STAGE 17 3388#define M_FW_HELLO_CMD_STAGE 0x7 3389#define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 3390#define G_FW_HELLO_CMD_STAGE(x) \ 3391 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 3392 3393#define S_FW_HELLO_CMD_CLEARINIT 16 3394#define M_FW_HELLO_CMD_CLEARINIT 0x1 3395#define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 3396#define G_FW_HELLO_CMD_CLEARINIT(x) \ 3397 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 3398#define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 3399 3400struct fw_bye_cmd { 3401 __be32 op_to_write; 3402 __be32 retval_len16; 3403 __be64 r3; 3404}; 3405 3406struct fw_initialize_cmd { 3407 __be32 op_to_write; 3408 __be32 retval_len16; 3409 __be64 r3; 3410}; 3411 3412enum fw_caps_config_hm { 3413 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 3414 FW_CAPS_CONFIG_HM_PL = 0x00000002, 3415 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 3416 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 3417 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 3418 FW_CAPS_CONFIG_HM_TP = 0x00000020, 3419 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 3420 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 3421 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 3422 FW_CAPS_CONFIG_HM_MC = 0x00000200, 3423 FW_CAPS_CONFIG_HM_LE = 0x00000400, 3424 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 3425 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 3426 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 3427 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 3428 FW_CAPS_CONFIG_HM_MI = 0x00008000, 3429 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 3430 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 3431 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 3432 FW_CAPS_CONFIG_HM_MA = 0x00080000, 3433 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 3434 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 3435 FW_CAPS_CONFIG_HM_UART = 0x00400000, 3436 FW_CAPS_CONFIG_HM_SF = 0x00800000, 3437}; 3438 3439/* 3440 * The VF Register Map. 3441 * 3442 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 3443 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 3444 * the Slice to Module Map Table (see below) in the Physical Function Register 3445 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 3446 * and Offset registers in the PF Register Map. The MBDATA base address is 3447 * quite constrained as it determines the Mailbox Data addresses for both PFs 3448 * and VFs, and therefore must fit in both the VF and PF Register Maps without 3449 * overlapping other registers. 3450 */ 3451#define FW_T4VF_SGE_BASE_ADDR 0x0000 3452#define FW_T4VF_MPS_BASE_ADDR 0x0100 3453#define FW_T4VF_PL_BASE_ADDR 0x0200 3454#define FW_T4VF_MBDATA_BASE_ADDR 0x0240 3455#define FW_T4VF_CIM_BASE_ADDR 0x0300 3456 3457#define FW_T4VF_REGMAP_START 0x0000 3458#define FW_T4VF_REGMAP_SIZE 0x0400 3459 3460enum fw_caps_config_nbm { 3461 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 3462 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 3463}; 3464 3465enum fw_caps_config_link { 3466 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 3467 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 3468 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 3469}; 3470 3471enum fw_caps_config_switch { 3472 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 3473 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 3474}; 3475 3476enum fw_caps_config_nic { 3477 FW_CAPS_CONFIG_NIC = 0x00000001, 3478 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 3479 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 3480 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 3481 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 3482 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 3483 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 3484}; 3485 3486enum fw_caps_config_toe { 3487 FW_CAPS_CONFIG_TOE = 0x00000001, 3488}; 3489 3490enum fw_caps_config_rdma { 3491 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 3492 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 3493}; 3494 3495enum fw_caps_config_iscsi { 3496 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 3497 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 3498 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 3499 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 3500 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 3501 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 3502}; 3503 3504enum fw_caps_config_fcoe { 3505 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3506 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3507 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3508 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 3509 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 3510}; 3511 3512enum fw_memtype_cf { 3513 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 3514 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 3515 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 3516 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 3517 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 3518 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 3519}; 3520 3521struct fw_caps_config_cmd { 3522 __be32 op_to_write; 3523 __be32 cfvalid_to_len16; 3524 __be32 r2; 3525 __be32 hwmbitmap; 3526 __be16 nbmcaps; 3527 __be16 linkcaps; 3528 __be16 switchcaps; 3529 __be16 r3; 3530 __be16 niccaps; 3531 __be16 toecaps; 3532 __be16 rdmacaps; 3533 __be16 r4; 3534 __be16 iscsicaps; 3535 __be16 fcoecaps; 3536 __be32 cfcsum; 3537 __be32 finiver; 3538 __be32 finicsum; 3539}; 3540 3541#define S_FW_CAPS_CONFIG_CMD_CFVALID 27 3542#define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 3543#define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 3544#define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 3545 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 3546#define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 3547 3548#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 3549#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 3550#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3551 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3552#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3553 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 3554 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3555 3556#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 3557#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 3558#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3559 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3560#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3561 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 3562 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3563 3564/* 3565 * params command mnemonics 3566 */ 3567enum fw_params_mnem { 3568 FW_PARAMS_MNEM_DEV = 1, /* device params */ 3569 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 3570 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 3571 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 3572 FW_PARAMS_MNEM_LAST 3573}; 3574 3575/* 3576 * device parameters 3577 */ 3578enum fw_params_param_dev { 3579 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 3580 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 3581 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 3582 * allocated by the device's 3583 * Lookup Engine 3584 */ 3585 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 3586 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 3587 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 3588 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 3589 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 3590 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 3591 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 3592 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 3593 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 3594 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 3595 FW_PARAMS_PARAM_DEV_CF = 0x0D, 3596 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 3597 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 3598 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 3599 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 3600 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 3601 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 3602 */ 3603 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 3604 */ 3605 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 3606 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 3607 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 3608}; 3609 3610/* 3611 * physical and virtual function parameters 3612 */ 3613enum fw_params_param_pfvf { 3614 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 3615 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 3616 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 3617 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 3618 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 3619 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 3620 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 3621 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 3622 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 3623 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 3624 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 3625 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 3626 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 3627 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 3628 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 3629 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 3630 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 3631 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 3632 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 3633 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 3634 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 3635 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 3636 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 3637 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 3638 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 3639 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 3640 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 3641 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 3642 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 3643 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 3644 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3645 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3646 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3647 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 3648 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3649 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3650 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3651 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 3652 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 3653 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 3654}; 3655 3656/* 3657 * dma queue parameters 3658 */ 3659enum fw_params_param_dmaq { 3660 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3661 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 3662 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 3663 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3664 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3665 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3666 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 3667 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 3668}; 3669 3670/* 3671 * dev bypass parameters; actions and modes 3672 */ 3673enum fw_params_param_dev_bypass { 3674 3675 /* actions 3676 */ 3677 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 3678 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 3679 3680 /* modes 3681 */ 3682 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 3683 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 3684 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 3685}; 3686 3687enum fw_params_phyfw_actions { 3688 FW_PARAMS_PARAM_PHYFW_DOWNLOAD = 0x00, 3689 FW_PARAMS_PARAM_PHYFW_VERSION = 0x01, 3690}; 3691 3692enum fw_params_param_dev_diag { 3693 FW_PARAM_DEV_DIAG_TMP = 0x00, 3694 FW_PARAM_DEV_DIAG_VDD = 0x01, 3695}; 3696 3697#define S_FW_PARAMS_MNEM 24 3698#define M_FW_PARAMS_MNEM 0xff 3699#define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 3700#define G_FW_PARAMS_MNEM(x) \ 3701 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 3702 3703#define S_FW_PARAMS_PARAM_X 16 3704#define M_FW_PARAMS_PARAM_X 0xff 3705#define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 3706#define G_FW_PARAMS_PARAM_X(x) \ 3707 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 3708 3709#define S_FW_PARAMS_PARAM_Y 8 3710#define M_FW_PARAMS_PARAM_Y 0xff 3711#define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 3712#define G_FW_PARAMS_PARAM_Y(x) \ 3713 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 3714 3715#define S_FW_PARAMS_PARAM_Z 0 3716#define M_FW_PARAMS_PARAM_Z 0xff 3717#define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 3718#define G_FW_PARAMS_PARAM_Z(x) \ 3719 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 3720 3721#define S_FW_PARAMS_PARAM_XYZ 0 3722#define M_FW_PARAMS_PARAM_XYZ 0xffffff 3723#define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 3724#define G_FW_PARAMS_PARAM_XYZ(x) \ 3725 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 3726 3727#define S_FW_PARAMS_PARAM_YZ 0 3728#define M_FW_PARAMS_PARAM_YZ 0xffff 3729#define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 3730#define G_FW_PARAMS_PARAM_YZ(x) \ 3731 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 3732 3733struct fw_params_cmd { 3734 __be32 op_to_vfn; 3735 __be32 retval_len16; 3736 struct fw_params_param { 3737 __be32 mnem; 3738 __be32 val; 3739 } param[7]; 3740}; 3741 3742#define S_FW_PARAMS_CMD_PFN 8 3743#define M_FW_PARAMS_CMD_PFN 0x7 3744#define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 3745#define G_FW_PARAMS_CMD_PFN(x) \ 3746 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 3747 3748#define S_FW_PARAMS_CMD_VFN 0 3749#define M_FW_PARAMS_CMD_VFN 0xff 3750#define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 3751#define G_FW_PARAMS_CMD_VFN(x) \ 3752 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 3753 3754struct fw_pfvf_cmd { 3755 __be32 op_to_vfn; 3756 __be32 retval_len16; 3757 __be32 niqflint_niq; 3758 __be32 type_to_neq; 3759 __be32 tc_to_nexactf; 3760 __be32 r_caps_to_nethctrl; 3761 __be16 nricq; 3762 __be16 nriqp; 3763 __be32 r4; 3764}; 3765 3766#define S_FW_PFVF_CMD_PFN 8 3767#define M_FW_PFVF_CMD_PFN 0x7 3768#define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 3769#define G_FW_PFVF_CMD_PFN(x) \ 3770 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 3771 3772#define S_FW_PFVF_CMD_VFN 0 3773#define M_FW_PFVF_CMD_VFN 0xff 3774#define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 3775#define G_FW_PFVF_CMD_VFN(x) \ 3776 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 3777 3778#define S_FW_PFVF_CMD_NIQFLINT 20 3779#define M_FW_PFVF_CMD_NIQFLINT 0xfff 3780#define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 3781#define G_FW_PFVF_CMD_NIQFLINT(x) \ 3782 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 3783 3784#define S_FW_PFVF_CMD_NIQ 0 3785#define M_FW_PFVF_CMD_NIQ 0xfffff 3786#define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 3787#define G_FW_PFVF_CMD_NIQ(x) \ 3788 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 3789 3790#define S_FW_PFVF_CMD_TYPE 31 3791#define M_FW_PFVF_CMD_TYPE 0x1 3792#define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 3793#define G_FW_PFVF_CMD_TYPE(x) \ 3794 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 3795#define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 3796 3797#define S_FW_PFVF_CMD_CMASK 24 3798#define M_FW_PFVF_CMD_CMASK 0xf 3799#define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 3800#define G_FW_PFVF_CMD_CMASK(x) \ 3801 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 3802 3803#define S_FW_PFVF_CMD_PMASK 20 3804#define M_FW_PFVF_CMD_PMASK 0xf 3805#define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 3806#define G_FW_PFVF_CMD_PMASK(x) \ 3807 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 3808 3809#define S_FW_PFVF_CMD_NEQ 0 3810#define M_FW_PFVF_CMD_NEQ 0xfffff 3811#define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 3812#define G_FW_PFVF_CMD_NEQ(x) \ 3813 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 3814 3815#define S_FW_PFVF_CMD_TC 24 3816#define M_FW_PFVF_CMD_TC 0xff 3817#define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 3818#define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 3819 3820#define S_FW_PFVF_CMD_NVI 16 3821#define M_FW_PFVF_CMD_NVI 0xff 3822#define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 3823#define G_FW_PFVF_CMD_NVI(x) \ 3824 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 3825 3826#define S_FW_PFVF_CMD_NEXACTF 0 3827#define M_FW_PFVF_CMD_NEXACTF 0xffff 3828#define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 3829#define G_FW_PFVF_CMD_NEXACTF(x) \ 3830 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 3831 3832#define S_FW_PFVF_CMD_R_CAPS 24 3833#define M_FW_PFVF_CMD_R_CAPS 0xff 3834#define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 3835#define G_FW_PFVF_CMD_R_CAPS(x) \ 3836 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 3837 3838#define S_FW_PFVF_CMD_WX_CAPS 16 3839#define M_FW_PFVF_CMD_WX_CAPS 0xff 3840#define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 3841#define G_FW_PFVF_CMD_WX_CAPS(x) \ 3842 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 3843 3844#define S_FW_PFVF_CMD_NETHCTRL 0 3845#define M_FW_PFVF_CMD_NETHCTRL 0xffff 3846#define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 3847#define G_FW_PFVF_CMD_NETHCTRL(x) \ 3848 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 3849 3850/* 3851 * ingress queue type; the first 1K ingress queues can have associated 0, 3852 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 3853 * capabilities 3854 */ 3855enum fw_iq_type { 3856 FW_IQ_TYPE_FL_INT_CAP, 3857 FW_IQ_TYPE_NO_FL_INT_CAP 3858}; 3859 3860struct fw_iq_cmd { 3861 __be32 op_to_vfn; 3862 __be32 alloc_to_len16; 3863 __be16 physiqid; 3864 __be16 iqid; 3865 __be16 fl0id; 3866 __be16 fl1id; 3867 __be32 type_to_iqandstindex; 3868 __be16 iqdroprss_to_iqesize; 3869 __be16 iqsize; 3870 __be64 iqaddr; 3871 __be32 iqns_to_fl0congen; 3872 __be16 fl0dcaen_to_fl0cidxfthresh; 3873 __be16 fl0size; 3874 __be64 fl0addr; 3875 __be32 fl1cngchmap_to_fl1congen; 3876 __be16 fl1dcaen_to_fl1cidxfthresh; 3877 __be16 fl1size; 3878 __be64 fl1addr; 3879}; 3880 3881#define S_FW_IQ_CMD_PFN 8 3882#define M_FW_IQ_CMD_PFN 0x7 3883#define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 3884#define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 3885 3886#define S_FW_IQ_CMD_VFN 0 3887#define M_FW_IQ_CMD_VFN 0xff 3888#define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 3889#define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 3890 3891#define S_FW_IQ_CMD_ALLOC 31 3892#define M_FW_IQ_CMD_ALLOC 0x1 3893#define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 3894#define G_FW_IQ_CMD_ALLOC(x) \ 3895 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 3896#define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 3897 3898#define S_FW_IQ_CMD_FREE 30 3899#define M_FW_IQ_CMD_FREE 0x1 3900#define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 3901#define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 3902#define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 3903 3904#define S_FW_IQ_CMD_MODIFY 29 3905#define M_FW_IQ_CMD_MODIFY 0x1 3906#define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 3907#define G_FW_IQ_CMD_MODIFY(x) \ 3908 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 3909#define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 3910 3911#define S_FW_IQ_CMD_IQSTART 28 3912#define M_FW_IQ_CMD_IQSTART 0x1 3913#define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 3914#define G_FW_IQ_CMD_IQSTART(x) \ 3915 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 3916#define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 3917 3918#define S_FW_IQ_CMD_IQSTOP 27 3919#define M_FW_IQ_CMD_IQSTOP 0x1 3920#define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 3921#define G_FW_IQ_CMD_IQSTOP(x) \ 3922 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 3923#define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 3924 3925#define S_FW_IQ_CMD_TYPE 29 3926#define M_FW_IQ_CMD_TYPE 0x7 3927#define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 3928#define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 3929 3930#define S_FW_IQ_CMD_IQASYNCH 28 3931#define M_FW_IQ_CMD_IQASYNCH 0x1 3932#define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 3933#define G_FW_IQ_CMD_IQASYNCH(x) \ 3934 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 3935#define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 3936 3937#define S_FW_IQ_CMD_VIID 16 3938#define M_FW_IQ_CMD_VIID 0xfff 3939#define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 3940#define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 3941 3942#define S_FW_IQ_CMD_IQANDST 15 3943#define M_FW_IQ_CMD_IQANDST 0x1 3944#define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 3945#define G_FW_IQ_CMD_IQANDST(x) \ 3946 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 3947#define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 3948 3949#define S_FW_IQ_CMD_IQANUS 14 3950#define M_FW_IQ_CMD_IQANUS 0x1 3951#define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 3952#define G_FW_IQ_CMD_IQANUS(x) \ 3953 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 3954#define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 3955 3956#define S_FW_IQ_CMD_IQANUD 12 3957#define M_FW_IQ_CMD_IQANUD 0x3 3958#define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 3959#define G_FW_IQ_CMD_IQANUD(x) \ 3960 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 3961 3962#define S_FW_IQ_CMD_IQANDSTINDEX 0 3963#define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 3964#define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 3965#define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 3966 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 3967 3968#define S_FW_IQ_CMD_IQDROPRSS 15 3969#define M_FW_IQ_CMD_IQDROPRSS 0x1 3970#define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 3971#define G_FW_IQ_CMD_IQDROPRSS(x) \ 3972 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 3973#define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 3974 3975#define S_FW_IQ_CMD_IQGTSMODE 14 3976#define M_FW_IQ_CMD_IQGTSMODE 0x1 3977#define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 3978#define G_FW_IQ_CMD_IQGTSMODE(x) \ 3979 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 3980#define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 3981 3982#define S_FW_IQ_CMD_IQPCIECH 12 3983#define M_FW_IQ_CMD_IQPCIECH 0x3 3984#define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 3985#define G_FW_IQ_CMD_IQPCIECH(x) \ 3986 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 3987 3988#define S_FW_IQ_CMD_IQDCAEN 11 3989#define M_FW_IQ_CMD_IQDCAEN 0x1 3990#define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 3991#define G_FW_IQ_CMD_IQDCAEN(x) \ 3992 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 3993#define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 3994 3995#define S_FW_IQ_CMD_IQDCACPU 6 3996#define M_FW_IQ_CMD_IQDCACPU 0x1f 3997#define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 3998#define G_FW_IQ_CMD_IQDCACPU(x) \ 3999 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 4000 4001#define S_FW_IQ_CMD_IQINTCNTTHRESH 4 4002#define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 4003#define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 4004#define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 4005 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 4006 4007#define S_FW_IQ_CMD_IQO 3 4008#define M_FW_IQ_CMD_IQO 0x1 4009#define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 4010#define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 4011#define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 4012 4013#define S_FW_IQ_CMD_IQCPRIO 2 4014#define M_FW_IQ_CMD_IQCPRIO 0x1 4015#define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 4016#define G_FW_IQ_CMD_IQCPRIO(x) \ 4017 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 4018#define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 4019 4020#define S_FW_IQ_CMD_IQESIZE 0 4021#define M_FW_IQ_CMD_IQESIZE 0x3 4022#define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 4023#define G_FW_IQ_CMD_IQESIZE(x) \ 4024 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 4025 4026#define S_FW_IQ_CMD_IQNS 31 4027#define M_FW_IQ_CMD_IQNS 0x1 4028#define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 4029#define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 4030#define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 4031 4032#define S_FW_IQ_CMD_IQRO 30 4033#define M_FW_IQ_CMD_IQRO 0x1 4034#define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 4035#define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 4036#define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 4037 4038#define S_FW_IQ_CMD_IQFLINTIQHSEN 28 4039#define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 4040#define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 4041#define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 4042 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 4043 4044#define S_FW_IQ_CMD_IQFLINTCONGEN 27 4045#define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 4046#define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 4047#define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 4048 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 4049#define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 4050 4051#define S_FW_IQ_CMD_IQFLINTISCSIC 26 4052#define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 4053#define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 4054#define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 4055 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 4056#define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 4057 4058#define S_FW_IQ_CMD_FL0CNGCHMAP 20 4059#define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 4060#define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 4061#define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 4062 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 4063 4064#define S_FW_IQ_CMD_FL0CACHELOCK 15 4065#define M_FW_IQ_CMD_FL0CACHELOCK 0x1 4066#define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 4067#define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 4068 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 4069#define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 4070 4071#define S_FW_IQ_CMD_FL0DBP 14 4072#define M_FW_IQ_CMD_FL0DBP 0x1 4073#define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 4074#define G_FW_IQ_CMD_FL0DBP(x) \ 4075 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 4076#define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 4077 4078#define S_FW_IQ_CMD_FL0DATANS 13 4079#define M_FW_IQ_CMD_FL0DATANS 0x1 4080#define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 4081#define G_FW_IQ_CMD_FL0DATANS(x) \ 4082 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 4083#define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 4084 4085#define S_FW_IQ_CMD_FL0DATARO 12 4086#define M_FW_IQ_CMD_FL0DATARO 0x1 4087#define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 4088#define G_FW_IQ_CMD_FL0DATARO(x) \ 4089 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 4090#define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 4091 4092#define S_FW_IQ_CMD_FL0CONGCIF 11 4093#define M_FW_IQ_CMD_FL0CONGCIF 0x1 4094#define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 4095#define G_FW_IQ_CMD_FL0CONGCIF(x) \ 4096 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 4097#define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 4098 4099#define S_FW_IQ_CMD_FL0ONCHIP 10 4100#define M_FW_IQ_CMD_FL0ONCHIP 0x1 4101#define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 4102#define G_FW_IQ_CMD_FL0ONCHIP(x) \ 4103 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 4104#define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 4105 4106#define S_FW_IQ_CMD_FL0STATUSPGNS 9 4107#define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 4108#define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 4109#define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 4110 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 4111#define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 4112 4113#define S_FW_IQ_CMD_FL0STATUSPGRO 8 4114#define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 4115#define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 4116#define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 4117 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 4118#define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 4119 4120#define S_FW_IQ_CMD_FL0FETCHNS 7 4121#define M_FW_IQ_CMD_FL0FETCHNS 0x1 4122#define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 4123#define G_FW_IQ_CMD_FL0FETCHNS(x) \ 4124 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 4125#define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 4126 4127#define S_FW_IQ_CMD_FL0FETCHRO 6 4128#define M_FW_IQ_CMD_FL0FETCHRO 0x1 4129#define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 4130#define G_FW_IQ_CMD_FL0FETCHRO(x) \ 4131 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 4132#define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 4133 4134#define S_FW_IQ_CMD_FL0HOSTFCMODE 4 4135#define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 4136#define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 4137#define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 4138 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 4139 4140#define S_FW_IQ_CMD_FL0CPRIO 3 4141#define M_FW_IQ_CMD_FL0CPRIO 0x1 4142#define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 4143#define G_FW_IQ_CMD_FL0CPRIO(x) \ 4144 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 4145#define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 4146 4147#define S_FW_IQ_CMD_FL0PADEN 2 4148#define M_FW_IQ_CMD_FL0PADEN 0x1 4149#define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 4150#define G_FW_IQ_CMD_FL0PADEN(x) \ 4151 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 4152#define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 4153 4154#define S_FW_IQ_CMD_FL0PACKEN 1 4155#define M_FW_IQ_CMD_FL0PACKEN 0x1 4156#define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 4157#define G_FW_IQ_CMD_FL0PACKEN(x) \ 4158 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 4159#define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 4160 4161#define S_FW_IQ_CMD_FL0CONGEN 0 4162#define M_FW_IQ_CMD_FL0CONGEN 0x1 4163#define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 4164#define G_FW_IQ_CMD_FL0CONGEN(x) \ 4165 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 4166#define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 4167 4168#define S_FW_IQ_CMD_FL0DCAEN 15 4169#define M_FW_IQ_CMD_FL0DCAEN 0x1 4170#define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 4171#define G_FW_IQ_CMD_FL0DCAEN(x) \ 4172 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 4173#define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 4174 4175#define S_FW_IQ_CMD_FL0DCACPU 10 4176#define M_FW_IQ_CMD_FL0DCACPU 0x1f 4177#define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 4178#define G_FW_IQ_CMD_FL0DCACPU(x) \ 4179 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 4180 4181#define S_FW_IQ_CMD_FL0FBMIN 7 4182#define M_FW_IQ_CMD_FL0FBMIN 0x7 4183#define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 4184#define G_FW_IQ_CMD_FL0FBMIN(x) \ 4185 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 4186 4187#define S_FW_IQ_CMD_FL0FBMAX 4 4188#define M_FW_IQ_CMD_FL0FBMAX 0x7 4189#define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 4190#define G_FW_IQ_CMD_FL0FBMAX(x) \ 4191 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 4192 4193#define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 4194#define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 4195#define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 4196#define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 4197 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 4198#define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 4199 4200#define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 4201#define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 4202#define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 4203#define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 4204 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 4205 4206#define S_FW_IQ_CMD_FL1CNGCHMAP 20 4207#define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 4208#define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 4209#define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 4210 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 4211 4212#define S_FW_IQ_CMD_FL1CACHELOCK 15 4213#define M_FW_IQ_CMD_FL1CACHELOCK 0x1 4214#define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 4215#define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 4216 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 4217#define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 4218 4219#define S_FW_IQ_CMD_FL1DBP 14 4220#define M_FW_IQ_CMD_FL1DBP 0x1 4221#define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 4222#define G_FW_IQ_CMD_FL1DBP(x) \ 4223 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 4224#define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 4225 4226#define S_FW_IQ_CMD_FL1DATANS 13 4227#define M_FW_IQ_CMD_FL1DATANS 0x1 4228#define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 4229#define G_FW_IQ_CMD_FL1DATANS(x) \ 4230 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 4231#define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 4232 4233#define S_FW_IQ_CMD_FL1DATARO 12 4234#define M_FW_IQ_CMD_FL1DATARO 0x1 4235#define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 4236#define G_FW_IQ_CMD_FL1DATARO(x) \ 4237 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 4238#define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 4239 4240#define S_FW_IQ_CMD_FL1CONGCIF 11 4241#define M_FW_IQ_CMD_FL1CONGCIF 0x1 4242#define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 4243#define G_FW_IQ_CMD_FL1CONGCIF(x) \ 4244 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 4245#define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 4246 4247#define S_FW_IQ_CMD_FL1ONCHIP 10 4248#define M_FW_IQ_CMD_FL1ONCHIP 0x1 4249#define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 4250#define G_FW_IQ_CMD_FL1ONCHIP(x) \ 4251 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 4252#define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 4253 4254#define S_FW_IQ_CMD_FL1STATUSPGNS 9 4255#define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 4256#define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 4257#define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 4258 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 4259#define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 4260 4261#define S_FW_IQ_CMD_FL1STATUSPGRO 8 4262#define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 4263#define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 4264#define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 4265 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 4266#define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 4267 4268#define S_FW_IQ_CMD_FL1FETCHNS 7 4269#define M_FW_IQ_CMD_FL1FETCHNS 0x1 4270#define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 4271#define G_FW_IQ_CMD_FL1FETCHNS(x) \ 4272 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 4273#define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 4274 4275#define S_FW_IQ_CMD_FL1FETCHRO 6 4276#define M_FW_IQ_CMD_FL1FETCHRO 0x1 4277#define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 4278#define G_FW_IQ_CMD_FL1FETCHRO(x) \ 4279 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 4280#define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 4281 4282#define S_FW_IQ_CMD_FL1HOSTFCMODE 4 4283#define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 4284#define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 4285#define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 4286 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 4287 4288#define S_FW_IQ_CMD_FL1CPRIO 3 4289#define M_FW_IQ_CMD_FL1CPRIO 0x1 4290#define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 4291#define G_FW_IQ_CMD_FL1CPRIO(x) \ 4292 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 4293#define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 4294 4295#define S_FW_IQ_CMD_FL1PADEN 2 4296#define M_FW_IQ_CMD_FL1PADEN 0x1 4297#define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 4298#define G_FW_IQ_CMD_FL1PADEN(x) \ 4299 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 4300#define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 4301 4302#define S_FW_IQ_CMD_FL1PACKEN 1 4303#define M_FW_IQ_CMD_FL1PACKEN 0x1 4304#define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 4305#define G_FW_IQ_CMD_FL1PACKEN(x) \ 4306 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 4307#define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 4308 4309#define S_FW_IQ_CMD_FL1CONGEN 0 4310#define M_FW_IQ_CMD_FL1CONGEN 0x1 4311#define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 4312#define G_FW_IQ_CMD_FL1CONGEN(x) \ 4313 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 4314#define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 4315 4316#define S_FW_IQ_CMD_FL1DCAEN 15 4317#define M_FW_IQ_CMD_FL1DCAEN 0x1 4318#define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 4319#define G_FW_IQ_CMD_FL1DCAEN(x) \ 4320 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 4321#define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 4322 4323#define S_FW_IQ_CMD_FL1DCACPU 10 4324#define M_FW_IQ_CMD_FL1DCACPU 0x1f 4325#define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 4326#define G_FW_IQ_CMD_FL1DCACPU(x) \ 4327 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 4328 4329#define S_FW_IQ_CMD_FL1FBMIN 7 4330#define M_FW_IQ_CMD_FL1FBMIN 0x7 4331#define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 4332#define G_FW_IQ_CMD_FL1FBMIN(x) \ 4333 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 4334 4335#define S_FW_IQ_CMD_FL1FBMAX 4 4336#define M_FW_IQ_CMD_FL1FBMAX 0x7 4337#define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 4338#define G_FW_IQ_CMD_FL1FBMAX(x) \ 4339 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 4340 4341#define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 4342#define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 4343#define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 4344#define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 4345 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 4346#define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 4347 4348#define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 4349#define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 4350#define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 4351#define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 4352 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 4353 4354struct fw_eq_mngt_cmd { 4355 __be32 op_to_vfn; 4356 __be32 alloc_to_len16; 4357 __be32 cmpliqid_eqid; 4358 __be32 physeqid_pkd; 4359 __be32 fetchszm_to_iqid; 4360 __be32 dcaen_to_eqsize; 4361 __be64 eqaddr; 4362}; 4363 4364#define S_FW_EQ_MNGT_CMD_PFN 8 4365#define M_FW_EQ_MNGT_CMD_PFN 0x7 4366#define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 4367#define G_FW_EQ_MNGT_CMD_PFN(x) \ 4368 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 4369 4370#define S_FW_EQ_MNGT_CMD_VFN 0 4371#define M_FW_EQ_MNGT_CMD_VFN 0xff 4372#define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 4373#define G_FW_EQ_MNGT_CMD_VFN(x) \ 4374 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 4375 4376#define S_FW_EQ_MNGT_CMD_ALLOC 31 4377#define M_FW_EQ_MNGT_CMD_ALLOC 0x1 4378#define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 4379#define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 4380 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 4381#define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 4382 4383#define S_FW_EQ_MNGT_CMD_FREE 30 4384#define M_FW_EQ_MNGT_CMD_FREE 0x1 4385#define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 4386#define G_FW_EQ_MNGT_CMD_FREE(x) \ 4387 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 4388#define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 4389 4390#define S_FW_EQ_MNGT_CMD_MODIFY 29 4391#define M_FW_EQ_MNGT_CMD_MODIFY 0x1 4392#define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 4393#define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 4394 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 4395#define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 4396 4397#define S_FW_EQ_MNGT_CMD_EQSTART 28 4398#define M_FW_EQ_MNGT_CMD_EQSTART 0x1 4399#define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 4400#define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 4401 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 4402#define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 4403 4404#define S_FW_EQ_MNGT_CMD_EQSTOP 27 4405#define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 4406#define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 4407#define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 4408 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 4409#define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 4410 4411#define S_FW_EQ_MNGT_CMD_CMPLIQID 20 4412#define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 4413#define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 4414#define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 4415 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 4416 4417#define S_FW_EQ_MNGT_CMD_EQID 0 4418#define M_FW_EQ_MNGT_CMD_EQID 0xfffff 4419#define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 4420#define G_FW_EQ_MNGT_CMD_EQID(x) \ 4421 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 4422 4423#define S_FW_EQ_MNGT_CMD_PHYSEQID 0 4424#define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 4425#define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 4426#define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 4427 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 4428 4429#define S_FW_EQ_MNGT_CMD_FETCHSZM 26 4430#define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 4431#define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 4432#define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 4433 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 4434#define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 4435 4436#define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 4437#define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 4438#define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 4439#define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 4440 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 4441#define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 4442 4443#define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 4444#define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 4445#define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 4446#define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 4447 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 4448#define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 4449 4450#define S_FW_EQ_MNGT_CMD_FETCHNS 23 4451#define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 4452#define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 4453#define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 4454 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 4455#define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 4456 4457#define S_FW_EQ_MNGT_CMD_FETCHRO 22 4458#define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 4459#define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 4460#define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 4461 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 4462#define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 4463 4464#define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 4465#define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 4466#define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 4467#define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 4468 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 4469 4470#define S_FW_EQ_MNGT_CMD_CPRIO 19 4471#define M_FW_EQ_MNGT_CMD_CPRIO 0x1 4472#define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 4473#define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 4474 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 4475#define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 4476 4477#define S_FW_EQ_MNGT_CMD_ONCHIP 18 4478#define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 4479#define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 4480#define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 4481 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 4482#define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 4483 4484#define S_FW_EQ_MNGT_CMD_PCIECHN 16 4485#define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 4486#define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 4487#define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 4488 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 4489 4490#define S_FW_EQ_MNGT_CMD_IQID 0 4491#define M_FW_EQ_MNGT_CMD_IQID 0xffff 4492#define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 4493#define G_FW_EQ_MNGT_CMD_IQID(x) \ 4494 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 4495 4496#define S_FW_EQ_MNGT_CMD_DCAEN 31 4497#define M_FW_EQ_MNGT_CMD_DCAEN 0x1 4498#define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 4499#define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 4500 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 4501#define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 4502 4503#define S_FW_EQ_MNGT_CMD_DCACPU 26 4504#define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 4505#define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 4506#define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 4507 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 4508 4509#define S_FW_EQ_MNGT_CMD_FBMIN 23 4510#define M_FW_EQ_MNGT_CMD_FBMIN 0x7 4511#define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 4512#define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 4513 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 4514 4515#define S_FW_EQ_MNGT_CMD_FBMAX 20 4516#define M_FW_EQ_MNGT_CMD_FBMAX 0x7 4517#define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 4518#define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 4519 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 4520 4521#define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 4522#define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 4523#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4524 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4525#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4526 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4527#define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 4528 4529#define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 4530#define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 4531#define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4532#define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 4533 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4534 4535#define S_FW_EQ_MNGT_CMD_EQSIZE 0 4536#define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 4537#define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 4538#define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 4539 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 4540 4541struct fw_eq_eth_cmd { 4542 __be32 op_to_vfn; 4543 __be32 alloc_to_len16; 4544 __be32 eqid_pkd; 4545 __be32 physeqid_pkd; 4546 __be32 fetchszm_to_iqid; 4547 __be32 dcaen_to_eqsize; 4548 __be64 eqaddr; 4549 __be32 viid_pkd; 4550 __be32 r8_lo; 4551 __be64 r9; 4552}; 4553 4554#define S_FW_EQ_ETH_CMD_PFN 8 4555#define M_FW_EQ_ETH_CMD_PFN 0x7 4556#define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 4557#define G_FW_EQ_ETH_CMD_PFN(x) \ 4558 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 4559 4560#define S_FW_EQ_ETH_CMD_VFN 0 4561#define M_FW_EQ_ETH_CMD_VFN 0xff 4562#define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 4563#define G_FW_EQ_ETH_CMD_VFN(x) \ 4564 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 4565 4566#define S_FW_EQ_ETH_CMD_ALLOC 31 4567#define M_FW_EQ_ETH_CMD_ALLOC 0x1 4568#define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 4569#define G_FW_EQ_ETH_CMD_ALLOC(x) \ 4570 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 4571#define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 4572 4573#define S_FW_EQ_ETH_CMD_FREE 30 4574#define M_FW_EQ_ETH_CMD_FREE 0x1 4575#define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 4576#define G_FW_EQ_ETH_CMD_FREE(x) \ 4577 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 4578#define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 4579 4580#define S_FW_EQ_ETH_CMD_MODIFY 29 4581#define M_FW_EQ_ETH_CMD_MODIFY 0x1 4582#define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 4583#define G_FW_EQ_ETH_CMD_MODIFY(x) \ 4584 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 4585#define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 4586 4587#define S_FW_EQ_ETH_CMD_EQSTART 28 4588#define M_FW_EQ_ETH_CMD_EQSTART 0x1 4589#define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 4590#define G_FW_EQ_ETH_CMD_EQSTART(x) \ 4591 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 4592#define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 4593 4594#define S_FW_EQ_ETH_CMD_EQSTOP 27 4595#define M_FW_EQ_ETH_CMD_EQSTOP 0x1 4596#define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 4597#define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 4598 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 4599#define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 4600 4601#define S_FW_EQ_ETH_CMD_EQID 0 4602#define M_FW_EQ_ETH_CMD_EQID 0xfffff 4603#define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 4604#define G_FW_EQ_ETH_CMD_EQID(x) \ 4605 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 4606 4607#define S_FW_EQ_ETH_CMD_PHYSEQID 0 4608#define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 4609#define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 4610#define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 4611 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 4612 4613#define S_FW_EQ_ETH_CMD_FETCHSZM 26 4614#define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 4615#define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 4616#define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 4617 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 4618#define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 4619 4620#define S_FW_EQ_ETH_CMD_STATUSPGNS 25 4621#define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 4622#define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 4623#define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 4624 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 4625#define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 4626 4627#define S_FW_EQ_ETH_CMD_STATUSPGRO 24 4628#define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 4629#define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 4630#define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 4631 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 4632#define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 4633 4634#define S_FW_EQ_ETH_CMD_FETCHNS 23 4635#define M_FW_EQ_ETH_CMD_FETCHNS 0x1 4636#define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 4637#define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 4638 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 4639#define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 4640 4641#define S_FW_EQ_ETH_CMD_FETCHRO 22 4642#define M_FW_EQ_ETH_CMD_FETCHRO 0x1 4643#define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 4644#define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 4645 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 4646#define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 4647 4648#define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 4649#define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 4650#define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 4651#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 4652 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 4653 4654#define S_FW_EQ_ETH_CMD_CPRIO 19 4655#define M_FW_EQ_ETH_CMD_CPRIO 0x1 4656#define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 4657#define G_FW_EQ_ETH_CMD_CPRIO(x) \ 4658 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 4659#define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 4660 4661#define S_FW_EQ_ETH_CMD_ONCHIP 18 4662#define M_FW_EQ_ETH_CMD_ONCHIP 0x1 4663#define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 4664#define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 4665 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 4666#define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 4667 4668#define S_FW_EQ_ETH_CMD_PCIECHN 16 4669#define M_FW_EQ_ETH_CMD_PCIECHN 0x3 4670#define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 4671#define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 4672 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 4673 4674#define S_FW_EQ_ETH_CMD_IQID 0 4675#define M_FW_EQ_ETH_CMD_IQID 0xffff 4676#define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 4677#define G_FW_EQ_ETH_CMD_IQID(x) \ 4678 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 4679 4680#define S_FW_EQ_ETH_CMD_DCAEN 31 4681#define M_FW_EQ_ETH_CMD_DCAEN 0x1 4682#define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 4683#define G_FW_EQ_ETH_CMD_DCAEN(x) \ 4684 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 4685#define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 4686 4687#define S_FW_EQ_ETH_CMD_DCACPU 26 4688#define M_FW_EQ_ETH_CMD_DCACPU 0x1f 4689#define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 4690#define G_FW_EQ_ETH_CMD_DCACPU(x) \ 4691 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 4692 4693#define S_FW_EQ_ETH_CMD_FBMIN 23 4694#define M_FW_EQ_ETH_CMD_FBMIN 0x7 4695#define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 4696#define G_FW_EQ_ETH_CMD_FBMIN(x) \ 4697 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 4698 4699#define S_FW_EQ_ETH_CMD_FBMAX 20 4700#define M_FW_EQ_ETH_CMD_FBMAX 0x7 4701#define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 4702#define G_FW_EQ_ETH_CMD_FBMAX(x) \ 4703 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 4704 4705#define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 4706#define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 4707#define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4708#define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 4709 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4710#define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 4711 4712#define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 4713#define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 4714#define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 4715#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 4716 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 4717 4718#define S_FW_EQ_ETH_CMD_EQSIZE 0 4719#define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 4720#define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 4721#define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 4722 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 4723 4724#define S_FW_EQ_ETH_CMD_VIID 16 4725#define M_FW_EQ_ETH_CMD_VIID 0xfff 4726#define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 4727#define G_FW_EQ_ETH_CMD_VIID(x) \ 4728 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 4729 4730struct fw_eq_ctrl_cmd { 4731 __be32 op_to_vfn; 4732 __be32 alloc_to_len16; 4733 __be32 cmpliqid_eqid; 4734 __be32 physeqid_pkd; 4735 __be32 fetchszm_to_iqid; 4736 __be32 dcaen_to_eqsize; 4737 __be64 eqaddr; 4738}; 4739 4740#define S_FW_EQ_CTRL_CMD_PFN 8 4741#define M_FW_EQ_CTRL_CMD_PFN 0x7 4742#define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 4743#define G_FW_EQ_CTRL_CMD_PFN(x) \ 4744 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 4745 4746#define S_FW_EQ_CTRL_CMD_VFN 0 4747#define M_FW_EQ_CTRL_CMD_VFN 0xff 4748#define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 4749#define G_FW_EQ_CTRL_CMD_VFN(x) \ 4750 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 4751 4752#define S_FW_EQ_CTRL_CMD_ALLOC 31 4753#define M_FW_EQ_CTRL_CMD_ALLOC 0x1 4754#define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 4755#define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 4756 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 4757#define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 4758 4759#define S_FW_EQ_CTRL_CMD_FREE 30 4760#define M_FW_EQ_CTRL_CMD_FREE 0x1 4761#define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 4762#define G_FW_EQ_CTRL_CMD_FREE(x) \ 4763 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 4764#define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 4765 4766#define S_FW_EQ_CTRL_CMD_MODIFY 29 4767#define M_FW_EQ_CTRL_CMD_MODIFY 0x1 4768#define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 4769#define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 4770 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 4771#define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 4772 4773#define S_FW_EQ_CTRL_CMD_EQSTART 28 4774#define M_FW_EQ_CTRL_CMD_EQSTART 0x1 4775#define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 4776#define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 4777 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 4778#define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 4779 4780#define S_FW_EQ_CTRL_CMD_EQSTOP 27 4781#define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 4782#define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 4783#define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 4784 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 4785#define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 4786 4787#define S_FW_EQ_CTRL_CMD_CMPLIQID 20 4788#define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 4789#define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 4790#define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 4791 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 4792 4793#define S_FW_EQ_CTRL_CMD_EQID 0 4794#define M_FW_EQ_CTRL_CMD_EQID 0xfffff 4795#define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 4796#define G_FW_EQ_CTRL_CMD_EQID(x) \ 4797 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 4798 4799#define S_FW_EQ_CTRL_CMD_PHYSEQID 0 4800#define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 4801#define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 4802#define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 4803 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 4804 4805#define S_FW_EQ_CTRL_CMD_FETCHSZM 26 4806#define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 4807#define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 4808#define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 4809 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 4810#define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 4811 4812#define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 4813#define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 4814#define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 4815#define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 4816 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 4817#define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 4818 4819#define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 4820#define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 4821#define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 4822#define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 4823 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 4824#define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 4825 4826#define S_FW_EQ_CTRL_CMD_FETCHNS 23 4827#define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 4828#define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 4829#define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 4830 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 4831#define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 4832 4833#define S_FW_EQ_CTRL_CMD_FETCHRO 22 4834#define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 4835#define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 4836#define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 4837 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 4838#define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 4839 4840#define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 4841#define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 4842#define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 4843#define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 4844 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 4845 4846#define S_FW_EQ_CTRL_CMD_CPRIO 19 4847#define M_FW_EQ_CTRL_CMD_CPRIO 0x1 4848#define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 4849#define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 4850 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 4851#define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 4852 4853#define S_FW_EQ_CTRL_CMD_ONCHIP 18 4854#define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 4855#define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 4856#define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 4857 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 4858#define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 4859 4860#define S_FW_EQ_CTRL_CMD_PCIECHN 16 4861#define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 4862#define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 4863#define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 4864 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 4865 4866#define S_FW_EQ_CTRL_CMD_IQID 0 4867#define M_FW_EQ_CTRL_CMD_IQID 0xffff 4868#define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 4869#define G_FW_EQ_CTRL_CMD_IQID(x) \ 4870 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 4871 4872#define S_FW_EQ_CTRL_CMD_DCAEN 31 4873#define M_FW_EQ_CTRL_CMD_DCAEN 0x1 4874#define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 4875#define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 4876 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 4877#define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 4878 4879#define S_FW_EQ_CTRL_CMD_DCACPU 26 4880#define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 4881#define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 4882#define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 4883 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 4884 4885#define S_FW_EQ_CTRL_CMD_FBMIN 23 4886#define M_FW_EQ_CTRL_CMD_FBMIN 0x7 4887#define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 4888#define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 4889 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 4890 4891#define S_FW_EQ_CTRL_CMD_FBMAX 20 4892#define M_FW_EQ_CTRL_CMD_FBMAX 0x7 4893#define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 4894#define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 4895 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 4896 4897#define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 4898#define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 4899#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4900 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4901#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4902 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4903#define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 4904 4905#define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 4906#define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 4907#define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4908#define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 4909 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4910 4911#define S_FW_EQ_CTRL_CMD_EQSIZE 0 4912#define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 4913#define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 4914#define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 4915 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 4916 4917struct fw_eq_ofld_cmd { 4918 __be32 op_to_vfn; 4919 __be32 alloc_to_len16; 4920 __be32 eqid_pkd; 4921 __be32 physeqid_pkd; 4922 __be32 fetchszm_to_iqid; 4923 __be32 dcaen_to_eqsize; 4924 __be64 eqaddr; 4925}; 4926 4927#define S_FW_EQ_OFLD_CMD_PFN 8 4928#define M_FW_EQ_OFLD_CMD_PFN 0x7 4929#define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 4930#define G_FW_EQ_OFLD_CMD_PFN(x) \ 4931 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 4932 4933#define S_FW_EQ_OFLD_CMD_VFN 0 4934#define M_FW_EQ_OFLD_CMD_VFN 0xff 4935#define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 4936#define G_FW_EQ_OFLD_CMD_VFN(x) \ 4937 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 4938 4939#define S_FW_EQ_OFLD_CMD_ALLOC 31 4940#define M_FW_EQ_OFLD_CMD_ALLOC 0x1 4941#define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 4942#define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 4943 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 4944#define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 4945 4946#define S_FW_EQ_OFLD_CMD_FREE 30 4947#define M_FW_EQ_OFLD_CMD_FREE 0x1 4948#define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 4949#define G_FW_EQ_OFLD_CMD_FREE(x) \ 4950 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 4951#define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 4952 4953#define S_FW_EQ_OFLD_CMD_MODIFY 29 4954#define M_FW_EQ_OFLD_CMD_MODIFY 0x1 4955#define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 4956#define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 4957 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 4958#define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 4959 4960#define S_FW_EQ_OFLD_CMD_EQSTART 28 4961#define M_FW_EQ_OFLD_CMD_EQSTART 0x1 4962#define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 4963#define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 4964 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 4965#define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 4966 4967#define S_FW_EQ_OFLD_CMD_EQSTOP 27 4968#define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 4969#define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 4970#define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 4971 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 4972#define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 4973 4974#define S_FW_EQ_OFLD_CMD_EQID 0 4975#define M_FW_EQ_OFLD_CMD_EQID 0xfffff 4976#define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 4977#define G_FW_EQ_OFLD_CMD_EQID(x) \ 4978 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 4979 4980#define S_FW_EQ_OFLD_CMD_PHYSEQID 0 4981#define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 4982#define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 4983#define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 4984 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 4985 4986#define S_FW_EQ_OFLD_CMD_FETCHSZM 26 4987#define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 4988#define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 4989#define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 4990 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 4991#define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 4992 4993#define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 4994#define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 4995#define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 4996#define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 4997 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 4998#define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 4999 5000#define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 5001#define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 5002#define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 5003#define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 5004 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 5005#define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 5006 5007#define S_FW_EQ_OFLD_CMD_FETCHNS 23 5008#define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 5009#define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 5010#define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 5011 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 5012#define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 5013 5014#define S_FW_EQ_OFLD_CMD_FETCHRO 22 5015#define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 5016#define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 5017#define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 5018 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 5019#define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 5020 5021#define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 5022#define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 5023#define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 5024#define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 5025 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 5026 5027#define S_FW_EQ_OFLD_CMD_CPRIO 19 5028#define M_FW_EQ_OFLD_CMD_CPRIO 0x1 5029#define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 5030#define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 5031 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 5032#define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 5033 5034#define S_FW_EQ_OFLD_CMD_ONCHIP 18 5035#define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 5036#define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 5037#define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 5038 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 5039#define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 5040 5041#define S_FW_EQ_OFLD_CMD_PCIECHN 16 5042#define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 5043#define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 5044#define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 5045 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 5046 5047#define S_FW_EQ_OFLD_CMD_IQID 0 5048#define M_FW_EQ_OFLD_CMD_IQID 0xffff 5049#define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 5050#define G_FW_EQ_OFLD_CMD_IQID(x) \ 5051 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 5052 5053#define S_FW_EQ_OFLD_CMD_DCAEN 31 5054#define M_FW_EQ_OFLD_CMD_DCAEN 0x1 5055#define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 5056#define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 5057 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 5058#define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 5059 5060#define S_FW_EQ_OFLD_CMD_DCACPU 26 5061#define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 5062#define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 5063#define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 5064 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 5065 5066#define S_FW_EQ_OFLD_CMD_FBMIN 23 5067#define M_FW_EQ_OFLD_CMD_FBMIN 0x7 5068#define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 5069#define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 5070 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 5071 5072#define S_FW_EQ_OFLD_CMD_FBMAX 20 5073#define M_FW_EQ_OFLD_CMD_FBMAX 0x7 5074#define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 5075#define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 5076 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 5077 5078#define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 5079#define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 5080#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5081 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5082#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 5083 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 5084#define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 5085 5086#define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 5087#define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 5088#define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5089#define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 5090 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 5091 5092#define S_FW_EQ_OFLD_CMD_EQSIZE 0 5093#define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 5094#define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 5095#define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 5096 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 5097 5098/* Macros for VIID parsing: 5099 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 5100#define S_FW_VIID_PFN 8 5101#define M_FW_VIID_PFN 0x7 5102#define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 5103#define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 5104 5105#define S_FW_VIID_VIVLD 7 5106#define M_FW_VIID_VIVLD 0x1 5107#define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 5108#define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 5109 5110#define S_FW_VIID_VIN 0 5111#define M_FW_VIID_VIN 0x7F 5112#define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 5113#define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 5114 5115enum fw_vi_func { 5116 FW_VI_FUNC_ETH, 5117 FW_VI_FUNC_OFLD, 5118 FW_VI_FUNC_IWARP, 5119 FW_VI_FUNC_OPENISCSI, 5120 FW_VI_FUNC_OPENFCOE, 5121 FW_VI_FUNC_FOISCSI, 5122 FW_VI_FUNC_FOFCOE, 5123 FW_VI_FUNC_FW, 5124}; 5125 5126struct fw_vi_cmd { 5127 __be32 op_to_vfn; 5128 __be32 alloc_to_len16; 5129 __be16 type_to_viid; 5130 __u8 mac[6]; 5131 __u8 portid_pkd; 5132 __u8 nmac; 5133 __u8 nmac0[6]; 5134 __be16 norss_rsssize; 5135 __u8 nmac1[6]; 5136 __be16 idsiiq_pkd; 5137 __u8 nmac2[6]; 5138 __be16 idseiq_pkd; 5139 __u8 nmac3[6]; 5140 __be64 r9; 5141 __be64 r10; 5142}; 5143 5144#define S_FW_VI_CMD_PFN 8 5145#define M_FW_VI_CMD_PFN 0x7 5146#define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 5147#define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 5148 5149#define S_FW_VI_CMD_VFN 0 5150#define M_FW_VI_CMD_VFN 0xff 5151#define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 5152#define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 5153 5154#define S_FW_VI_CMD_ALLOC 31 5155#define M_FW_VI_CMD_ALLOC 0x1 5156#define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 5157#define G_FW_VI_CMD_ALLOC(x) \ 5158 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 5159#define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 5160 5161#define S_FW_VI_CMD_FREE 30 5162#define M_FW_VI_CMD_FREE 0x1 5163#define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 5164#define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 5165#define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 5166 5167#define S_FW_VI_CMD_TYPE 15 5168#define M_FW_VI_CMD_TYPE 0x1 5169#define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 5170#define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 5171#define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 5172 5173#define S_FW_VI_CMD_FUNC 12 5174#define M_FW_VI_CMD_FUNC 0x7 5175#define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 5176#define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 5177 5178#define S_FW_VI_CMD_VIID 0 5179#define M_FW_VI_CMD_VIID 0xfff 5180#define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 5181#define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 5182 5183#define S_FW_VI_CMD_PORTID 4 5184#define M_FW_VI_CMD_PORTID 0xf 5185#define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 5186#define G_FW_VI_CMD_PORTID(x) \ 5187 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5188 5189#define S_FW_VI_CMD_NORSS 11 5190#define M_FW_VI_CMD_NORSS 0x1 5191#define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 5192#define G_FW_VI_CMD_NORSS(x) \ 5193 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 5194#define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 5195 5196#define S_FW_VI_CMD_RSSSIZE 0 5197#define M_FW_VI_CMD_RSSSIZE 0x7ff 5198#define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5199#define G_FW_VI_CMD_RSSSIZE(x) \ 5200 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5201 5202#define S_FW_VI_CMD_IDSIIQ 0 5203#define M_FW_VI_CMD_IDSIIQ 0x3ff 5204#define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 5205#define G_FW_VI_CMD_IDSIIQ(x) \ 5206 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 5207 5208#define S_FW_VI_CMD_IDSEIQ 0 5209#define M_FW_VI_CMD_IDSEIQ 0x3ff 5210#define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 5211#define G_FW_VI_CMD_IDSEIQ(x) \ 5212 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 5213 5214/* Special VI_MAC command index ids */ 5215#define FW_VI_MAC_ADD_MAC 0x3FF 5216#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5217#define FW_VI_MAC_MAC_BASED_FREE 0x3FD 5218 5219enum fw_vi_mac_smac { 5220 FW_VI_MAC_MPS_TCAM_ENTRY, 5221 FW_VI_MAC_MPS_TCAM_ONLY, 5222 FW_VI_MAC_SMT_ONLY, 5223 FW_VI_MAC_SMT_AND_MPSTCAM 5224}; 5225 5226enum fw_vi_mac_result { 5227 FW_VI_MAC_R_SUCCESS, 5228 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 5229 FW_VI_MAC_R_SMAC_FAIL, 5230 FW_VI_MAC_R_F_ACL_CHECK 5231}; 5232 5233struct fw_vi_mac_cmd { 5234 __be32 op_to_viid; 5235 __be32 freemacs_to_len16; 5236 union fw_vi_mac { 5237 struct fw_vi_mac_exact { 5238 __be16 valid_to_idx; 5239 __u8 macaddr[6]; 5240 } exact[7]; 5241 struct fw_vi_mac_hash { 5242 __be64 hashvec; 5243 } hash; 5244 } u; 5245}; 5246 5247#define S_FW_VI_MAC_CMD_VIID 0 5248#define M_FW_VI_MAC_CMD_VIID 0xfff 5249#define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 5250#define G_FW_VI_MAC_CMD_VIID(x) \ 5251 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 5252 5253#define S_FW_VI_MAC_CMD_FREEMACS 31 5254#define M_FW_VI_MAC_CMD_FREEMACS 0x1 5255#define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 5256#define G_FW_VI_MAC_CMD_FREEMACS(x) \ 5257 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 5258#define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 5259 5260#define S_FW_VI_MAC_CMD_HASHVECEN 23 5261#define M_FW_VI_MAC_CMD_HASHVECEN 0x1 5262#define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN) 5263#define G_FW_VI_MAC_CMD_HASHVECEN(x) \ 5264 (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN) 5265#define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U) 5266 5267#define S_FW_VI_MAC_CMD_HASHUNIEN 22 5268#define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 5269#define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 5270#define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 5271 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 5272#define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 5273 5274#define S_FW_VI_MAC_CMD_VALID 15 5275#define M_FW_VI_MAC_CMD_VALID 0x1 5276#define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 5277#define G_FW_VI_MAC_CMD_VALID(x) \ 5278 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 5279#define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 5280 5281#define S_FW_VI_MAC_CMD_PRIO 12 5282#define M_FW_VI_MAC_CMD_PRIO 0x7 5283#define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 5284#define G_FW_VI_MAC_CMD_PRIO(x) \ 5285 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 5286 5287#define S_FW_VI_MAC_CMD_SMAC_RESULT 10 5288#define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 5289#define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 5290#define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 5291 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 5292 5293#define S_FW_VI_MAC_CMD_IDX 0 5294#define M_FW_VI_MAC_CMD_IDX 0x3ff 5295#define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 5296#define G_FW_VI_MAC_CMD_IDX(x) \ 5297 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 5298 5299/* T4 max MTU supported */ 5300#define T4_MAX_MTU_SUPPORTED 9600 5301#define FW_RXMODE_MTU_NO_CHG 65535 5302 5303struct fw_vi_rxmode_cmd { 5304 __be32 op_to_viid; 5305 __be32 retval_len16; 5306 __be32 mtu_to_vlanexen; 5307 __be32 r4_lo; 5308}; 5309 5310#define S_FW_VI_RXMODE_CMD_VIID 0 5311#define M_FW_VI_RXMODE_CMD_VIID 0xfff 5312#define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 5313#define G_FW_VI_RXMODE_CMD_VIID(x) \ 5314 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 5315 5316#define S_FW_VI_RXMODE_CMD_MTU 16 5317#define M_FW_VI_RXMODE_CMD_MTU 0xffff 5318#define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 5319#define G_FW_VI_RXMODE_CMD_MTU(x) \ 5320 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 5321 5322#define S_FW_VI_RXMODE_CMD_PROMISCEN 14 5323#define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 5324#define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 5325#define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 5326 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 5327 5328#define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 5329#define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 5330#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5331 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 5332#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5333 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 5334 5335#define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 5336#define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 5337#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5338 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 5339#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5340 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 5341 5342#define S_FW_VI_RXMODE_CMD_VLANEXEN 8 5343#define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 5344#define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 5345#define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 5346 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 5347 5348struct fw_vi_enable_cmd { 5349 __be32 op_to_viid; 5350 __be32 ien_to_len16; 5351 __be16 blinkdur; 5352 __be16 r3; 5353 __be32 r4; 5354}; 5355 5356#define S_FW_VI_ENABLE_CMD_VIID 0 5357#define M_FW_VI_ENABLE_CMD_VIID 0xfff 5358#define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 5359#define G_FW_VI_ENABLE_CMD_VIID(x) \ 5360 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 5361 5362#define S_FW_VI_ENABLE_CMD_IEN 31 5363#define M_FW_VI_ENABLE_CMD_IEN 0x1 5364#define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 5365#define G_FW_VI_ENABLE_CMD_IEN(x) \ 5366 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 5367#define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 5368 5369#define S_FW_VI_ENABLE_CMD_EEN 30 5370#define M_FW_VI_ENABLE_CMD_EEN 0x1 5371#define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 5372#define G_FW_VI_ENABLE_CMD_EEN(x) \ 5373 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 5374#define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 5375 5376#define S_FW_VI_ENABLE_CMD_LED 29 5377#define M_FW_VI_ENABLE_CMD_LED 0x1 5378#define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 5379#define G_FW_VI_ENABLE_CMD_LED(x) \ 5380 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 5381#define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 5382 5383#define S_FW_VI_ENABLE_CMD_DCB_INFO 28 5384#define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 5385#define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 5386#define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 5387 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 5388#define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 5389 5390/* VI VF stats offset definitions */ 5391#define VI_VF_NUM_STATS 16 5392enum fw_vi_stats_vf_index { 5393 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 5394 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 5395 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 5396 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 5397 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 5398 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 5399 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 5400 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 5401 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 5402 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 5403 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 5404 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 5405 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 5406 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 5407 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 5408 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 5409}; 5410 5411/* VI PF stats offset definitions */ 5412#define VI_PF_NUM_STATS 17 5413enum fw_vi_stats_pf_index { 5414 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 5415 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 5416 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 5417 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 5418 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 5419 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 5420 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 5421 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 5422 FW_VI_PF_STAT_RX_BYTES_IX, 5423 FW_VI_PF_STAT_RX_FRAMES_IX, 5424 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 5425 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 5426 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 5427 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 5428 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 5429 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 5430 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 5431}; 5432 5433struct fw_vi_stats_cmd { 5434 __be32 op_to_viid; 5435 __be32 retval_len16; 5436 union fw_vi_stats { 5437 struct fw_vi_stats_ctl { 5438 __be16 nstats_ix; 5439 __be16 r6; 5440 __be32 r7; 5441 __be64 stat0; 5442 __be64 stat1; 5443 __be64 stat2; 5444 __be64 stat3; 5445 __be64 stat4; 5446 __be64 stat5; 5447 } ctl; 5448 struct fw_vi_stats_pf { 5449 __be64 tx_bcast_bytes; 5450 __be64 tx_bcast_frames; 5451 __be64 tx_mcast_bytes; 5452 __be64 tx_mcast_frames; 5453 __be64 tx_ucast_bytes; 5454 __be64 tx_ucast_frames; 5455 __be64 tx_offload_bytes; 5456 __be64 tx_offload_frames; 5457 __be64 rx_pf_bytes; 5458 __be64 rx_pf_frames; 5459 __be64 rx_bcast_bytes; 5460 __be64 rx_bcast_frames; 5461 __be64 rx_mcast_bytes; 5462 __be64 rx_mcast_frames; 5463 __be64 rx_ucast_bytes; 5464 __be64 rx_ucast_frames; 5465 __be64 rx_err_frames; 5466 } pf; 5467 struct fw_vi_stats_vf { 5468 __be64 tx_bcast_bytes; 5469 __be64 tx_bcast_frames; 5470 __be64 tx_mcast_bytes; 5471 __be64 tx_mcast_frames; 5472 __be64 tx_ucast_bytes; 5473 __be64 tx_ucast_frames; 5474 __be64 tx_drop_frames; 5475 __be64 tx_offload_bytes; 5476 __be64 tx_offload_frames; 5477 __be64 rx_bcast_bytes; 5478 __be64 rx_bcast_frames; 5479 __be64 rx_mcast_bytes; 5480 __be64 rx_mcast_frames; 5481 __be64 rx_ucast_bytes; 5482 __be64 rx_ucast_frames; 5483 __be64 rx_err_frames; 5484 } vf; 5485 } u; 5486}; 5487 5488#define S_FW_VI_STATS_CMD_VIID 0 5489#define M_FW_VI_STATS_CMD_VIID 0xfff 5490#define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 5491#define G_FW_VI_STATS_CMD_VIID(x) \ 5492 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 5493 5494#define S_FW_VI_STATS_CMD_NSTATS 12 5495#define M_FW_VI_STATS_CMD_NSTATS 0x7 5496#define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 5497#define G_FW_VI_STATS_CMD_NSTATS(x) \ 5498 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 5499 5500#define S_FW_VI_STATS_CMD_IX 0 5501#define M_FW_VI_STATS_CMD_IX 0x1f 5502#define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 5503#define G_FW_VI_STATS_CMD_IX(x) \ 5504 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 5505 5506struct fw_acl_mac_cmd { 5507 __be32 op_to_vfn; 5508 __be32 en_to_len16; 5509 __u8 nmac; 5510 __u8 r3[7]; 5511 __be16 r4; 5512 __u8 macaddr0[6]; 5513 __be16 r5; 5514 __u8 macaddr1[6]; 5515 __be16 r6; 5516 __u8 macaddr2[6]; 5517 __be16 r7; 5518 __u8 macaddr3[6]; 5519}; 5520 5521#define S_FW_ACL_MAC_CMD_PFN 8 5522#define M_FW_ACL_MAC_CMD_PFN 0x7 5523#define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 5524#define G_FW_ACL_MAC_CMD_PFN(x) \ 5525 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 5526 5527#define S_FW_ACL_MAC_CMD_VFN 0 5528#define M_FW_ACL_MAC_CMD_VFN 0xff 5529#define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 5530#define G_FW_ACL_MAC_CMD_VFN(x) \ 5531 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 5532 5533#define S_FW_ACL_MAC_CMD_EN 31 5534#define M_FW_ACL_MAC_CMD_EN 0x1 5535#define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 5536#define G_FW_ACL_MAC_CMD_EN(x) \ 5537 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 5538#define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 5539 5540struct fw_acl_vlan_cmd { 5541 __be32 op_to_vfn; 5542 __be32 en_to_len16; 5543 __u8 nvlan; 5544 __u8 dropnovlan_fm; 5545 __u8 r3_lo[6]; 5546 __be16 vlanid[16]; 5547}; 5548 5549#define S_FW_ACL_VLAN_CMD_PFN 8 5550#define M_FW_ACL_VLAN_CMD_PFN 0x7 5551#define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 5552#define G_FW_ACL_VLAN_CMD_PFN(x) \ 5553 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 5554 5555#define S_FW_ACL_VLAN_CMD_VFN 0 5556#define M_FW_ACL_VLAN_CMD_VFN 0xff 5557#define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 5558#define G_FW_ACL_VLAN_CMD_VFN(x) \ 5559 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 5560 5561#define S_FW_ACL_VLAN_CMD_EN 31 5562#define M_FW_ACL_VLAN_CMD_EN 0x1 5563#define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 5564#define G_FW_ACL_VLAN_CMD_EN(x) \ 5565 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 5566#define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 5567 5568#define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 5569#define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 5570#define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 5571#define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 5572 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 5573#define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 5574 5575#define S_FW_ACL_VLAN_CMD_FM 6 5576#define M_FW_ACL_VLAN_CMD_FM 0x1 5577#define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 5578#define G_FW_ACL_VLAN_CMD_FM(x) \ 5579 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 5580#define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 5581 5582/* port capabilities bitmap */ 5583enum fw_port_cap { 5584 FW_PORT_CAP_SPEED_100M = 0x0001, 5585 FW_PORT_CAP_SPEED_1G = 0x0002, 5586 FW_PORT_CAP_SPEED_2_5G = 0x0004, 5587 FW_PORT_CAP_SPEED_10G = 0x0008, 5588 FW_PORT_CAP_SPEED_40G = 0x0010, 5589 FW_PORT_CAP_SPEED_100G = 0x0020, 5590 FW_PORT_CAP_FC_RX = 0x0040, 5591 FW_PORT_CAP_FC_TX = 0x0080, 5592 FW_PORT_CAP_ANEG = 0x0100, 5593 FW_PORT_CAP_MDIX = 0x0200, 5594 FW_PORT_CAP_MDIAUTO = 0x0400, 5595 FW_PORT_CAP_FEC = 0x0800, 5596 FW_PORT_CAP_TECHKR = 0x1000, 5597 FW_PORT_CAP_TECHKX4 = 0x2000, 5598}; 5599 5600#define S_FW_PORT_AUXLINFO_MDI 3 5601#define M_FW_PORT_AUXLINFO_MDI 0x3 5602#define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 5603#define G_FW_PORT_AUXLINFO_MDI(x) \ 5604 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 5605 5606#define S_FW_PORT_AUXLINFO_KX4 2 5607#define M_FW_PORT_AUXLINFO_KX4 0x1 5608#define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 5609#define G_FW_PORT_AUXLINFO_KX4(x) \ 5610 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 5611#define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 5612 5613#define S_FW_PORT_AUXLINFO_KR 1 5614#define M_FW_PORT_AUXLINFO_KR 0x1 5615#define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 5616#define G_FW_PORT_AUXLINFO_KR(x) \ 5617 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 5618#define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 5619 5620#define S_FW_PORT_AUXLINFO_FEC 0 5621#define M_FW_PORT_AUXLINFO_FEC 0x1 5622#define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 5623#define G_FW_PORT_AUXLINFO_FEC(x) \ 5624 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 5625#define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 5626 5627#define S_FW_PORT_RCAP_AUX 11 5628#define M_FW_PORT_RCAP_AUX 0x7 5629#define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 5630#define G_FW_PORT_RCAP_AUX(x) \ 5631 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 5632 5633#define S_FW_PORT_CAP_SPEED 0 5634#define M_FW_PORT_CAP_SPEED 0x3f 5635#define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 5636#define G_FW_PORT_CAP_SPEED(x) \ 5637 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 5638 5639#define S_FW_PORT_CAP_FC 6 5640#define M_FW_PORT_CAP_FC 0x3 5641#define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 5642#define G_FW_PORT_CAP_FC(x) \ 5643 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 5644 5645#define S_FW_PORT_CAP_ANEG 8 5646#define M_FW_PORT_CAP_ANEG 0x1 5647#define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 5648#define G_FW_PORT_CAP_ANEG(x) \ 5649 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 5650 5651enum fw_port_mdi { 5652 FW_PORT_CAP_MDI_UNCHANGED, 5653 FW_PORT_CAP_MDI_AUTO, 5654 FW_PORT_CAP_MDI_F_STRAIGHT, 5655 FW_PORT_CAP_MDI_F_CROSSOVER 5656}; 5657 5658#define S_FW_PORT_CAP_MDI 9 5659#define M_FW_PORT_CAP_MDI 3 5660#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 5661#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 5662 5663enum fw_port_action { 5664 FW_PORT_ACTION_L1_CFG = 0x0001, 5665 FW_PORT_ACTION_L2_CFG = 0x0002, 5666 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 5667 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 5668 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 5669 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 5670 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 5671 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 5672 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 5673 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 5674 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 5675 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 5676 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 5677 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 5678 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 5679 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 5680 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 5681 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 5682 FW_PORT_ACTION_PHY_RESET = 0x0040, 5683 FW_PORT_ACTION_PMA_RESET = 0x0041, 5684 FW_PORT_ACTION_PCS_RESET = 0x0042, 5685 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 5686 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 5687 FW_PORT_ACTION_AN_RESET = 0x0045, 5688 5689}; 5690 5691enum fw_port_l2cfg_ctlbf { 5692 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 5693 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 5694 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 5695 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 5696 FW_PORT_L2_CTLBF_IVLAN = 0x10, 5697 FW_PORT_L2_CTLBF_TXIPG = 0x20, 5698 FW_PORT_L2_CTLBF_MTU = 0x40 5699}; 5700 5701enum fw_dcb_app_tlv_sf { 5702 FW_DCB_APP_SF_ETHERTYPE, 5703 FW_DCB_APP_SF_SOCKET_TCP, 5704 FW_DCB_APP_SF_SOCKET_UDP, 5705 FW_DCB_APP_SF_SOCKET_ALL, 5706}; 5707 5708enum fw_port_dcb_versions { 5709 FW_PORT_DCB_VER_CEE1D0, 5710 FW_PORT_DCB_VER_CEE1D01, 5711 FW_PORT_DCB_VER_IEEE, 5712 FW_PORT_DCB_VER_UNKNOWN=7 5713}; 5714 5715enum fw_port_dcb_cfg { 5716 FW_PORT_DCB_CFG_PG = 0x01, 5717 FW_PORT_DCB_CFG_PFC = 0x02, 5718 FW_PORT_DCB_CFG_APPL = 0x04 5719}; 5720 5721enum fw_port_dcb_cfg_rc { 5722 FW_PORT_DCB_CFG_SUCCESS = 0x0, 5723 FW_PORT_DCB_CFG_ERROR = 0x1 5724}; 5725 5726enum fw_port_dcb_type { 5727 FW_PORT_DCB_TYPE_PGID = 0x00, 5728 FW_PORT_DCB_TYPE_PGRATE = 0x01, 5729 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 5730 FW_PORT_DCB_TYPE_PFC = 0x03, 5731 FW_PORT_DCB_TYPE_APP_ID = 0x04, 5732 FW_PORT_DCB_TYPE_CONTROL = 0x05, 5733}; 5734 5735enum fw_port_dcb_feature_state { 5736 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 5737 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 5738 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 5739 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 5740}; 5741 5742enum fw_port_diag_ops { 5743 FW_PORT_DIAGS_TEMP = 0x00, 5744 FW_PORT_DIAGS_TX_POWER = 0x01, 5745 FW_PORT_DIAGS_RX_POWER = 0x02, 5746}; 5747 5748struct fw_port_cmd { 5749 __be32 op_to_portid; 5750 __be32 action_to_len16; 5751 union fw_port { 5752 struct fw_port_l1cfg { 5753 __be32 rcap; 5754 __be32 r; 5755 } l1cfg; 5756 struct fw_port_l2cfg { 5757 __u8 ctlbf; 5758 __u8 ovlan3_to_ivlan0; 5759 __be16 ivlantype; 5760 __be16 txipg_force_pinfo; 5761 __be16 mtu; 5762 __be16 ovlan0mask; 5763 __be16 ovlan0type; 5764 __be16 ovlan1mask; 5765 __be16 ovlan1type; 5766 __be16 ovlan2mask; 5767 __be16 ovlan2type; 5768 __be16 ovlan3mask; 5769 __be16 ovlan3type; 5770 } l2cfg; 5771 struct fw_port_info { 5772 __be32 lstatus_to_modtype; 5773 __be16 pcap; 5774 __be16 acap; 5775 __be16 mtu; 5776 __u8 cbllen; 5777 __u8 auxlinfo; 5778 __u8 dcbxdis_pkd; 5779 __u8 r8_lo[3]; 5780 __be64 r9; 5781 } info; 5782 struct fw_port_diags { 5783 __u8 diagop; 5784 __u8 r[3]; 5785 __be32 diagval; 5786 } diags; 5787 union fw_port_dcb { 5788 struct fw_port_dcb_pgid { 5789 __u8 type; 5790 __u8 apply_pkd; 5791 __u8 r10_lo[2]; 5792 __be32 pgid; 5793 __be64 r11; 5794 } pgid; 5795 struct fw_port_dcb_pgrate { 5796 __u8 type; 5797 __u8 apply_pkd; 5798 __u8 r10_lo[5]; 5799 __u8 num_tcs_supported; 5800 __u8 pgrate[8]; 5801 } pgrate; 5802 struct fw_port_dcb_priorate { 5803 __u8 type; 5804 __u8 apply_pkd; 5805 __u8 r10_lo[6]; 5806 __u8 strict_priorate[8]; 5807 } priorate; 5808 struct fw_port_dcb_pfc { 5809 __u8 type; 5810 __u8 pfcen; 5811 __be16 r10[3]; 5812 __be64 r11; 5813 } pfc; 5814 struct fw_port_app_priority { 5815 __u8 type; 5816 __u8 r10[2]; 5817 __u8 idx; 5818 __u8 user_prio_map; 5819 __u8 sel_field; 5820 __be16 protocolid; 5821 __be64 r12; 5822 } app_priority; 5823 struct fw_port_dcb_control { 5824 __u8 type; 5825 __u8 all_syncd_pkd; 5826 __be16 pfc_state_to_app_state; 5827 __be32 r11; 5828 __be64 r12; 5829 } control; 5830 } dcb; 5831 } u; 5832}; 5833 5834#define S_FW_PORT_CMD_READ 22 5835#define M_FW_PORT_CMD_READ 0x1 5836#define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 5837#define G_FW_PORT_CMD_READ(x) \ 5838 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 5839#define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 5840 5841#define S_FW_PORT_CMD_PORTID 0 5842#define M_FW_PORT_CMD_PORTID 0xf 5843#define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 5844#define G_FW_PORT_CMD_PORTID(x) \ 5845 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 5846 5847#define S_FW_PORT_CMD_ACTION 16 5848#define M_FW_PORT_CMD_ACTION 0xffff 5849#define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 5850#define G_FW_PORT_CMD_ACTION(x) \ 5851 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 5852 5853#define S_FW_PORT_CMD_OVLAN3 7 5854#define M_FW_PORT_CMD_OVLAN3 0x1 5855#define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 5856#define G_FW_PORT_CMD_OVLAN3(x) \ 5857 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 5858#define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 5859 5860#define S_FW_PORT_CMD_OVLAN2 6 5861#define M_FW_PORT_CMD_OVLAN2 0x1 5862#define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 5863#define G_FW_PORT_CMD_OVLAN2(x) \ 5864 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 5865#define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 5866 5867#define S_FW_PORT_CMD_OVLAN1 5 5868#define M_FW_PORT_CMD_OVLAN1 0x1 5869#define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 5870#define G_FW_PORT_CMD_OVLAN1(x) \ 5871 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 5872#define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 5873 5874#define S_FW_PORT_CMD_OVLAN0 4 5875#define M_FW_PORT_CMD_OVLAN0 0x1 5876#define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 5877#define G_FW_PORT_CMD_OVLAN0(x) \ 5878 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 5879#define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 5880 5881#define S_FW_PORT_CMD_IVLAN0 3 5882#define M_FW_PORT_CMD_IVLAN0 0x1 5883#define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 5884#define G_FW_PORT_CMD_IVLAN0(x) \ 5885 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 5886#define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 5887 5888#define S_FW_PORT_CMD_TXIPG 3 5889#define M_FW_PORT_CMD_TXIPG 0x1fff 5890#define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 5891#define G_FW_PORT_CMD_TXIPG(x) \ 5892 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 5893 5894#define S_FW_PORT_CMD_FORCE_PINFO 0 5895#define M_FW_PORT_CMD_FORCE_PINFO 0x1 5896#define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 5897#define G_FW_PORT_CMD_FORCE_PINFO(x) \ 5898 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 5899#define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 5900 5901#define S_FW_PORT_CMD_LSTATUS 31 5902#define M_FW_PORT_CMD_LSTATUS 0x1 5903#define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 5904#define G_FW_PORT_CMD_LSTATUS(x) \ 5905 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 5906#define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 5907 5908#define S_FW_PORT_CMD_LSPEED 24 5909#define M_FW_PORT_CMD_LSPEED 0x3f 5910#define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 5911#define G_FW_PORT_CMD_LSPEED(x) \ 5912 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 5913 5914#define S_FW_PORT_CMD_TXPAUSE 23 5915#define M_FW_PORT_CMD_TXPAUSE 0x1 5916#define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 5917#define G_FW_PORT_CMD_TXPAUSE(x) \ 5918 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 5919#define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 5920 5921#define S_FW_PORT_CMD_RXPAUSE 22 5922#define M_FW_PORT_CMD_RXPAUSE 0x1 5923#define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 5924#define G_FW_PORT_CMD_RXPAUSE(x) \ 5925 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 5926#define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 5927 5928#define S_FW_PORT_CMD_MDIOCAP 21 5929#define M_FW_PORT_CMD_MDIOCAP 0x1 5930#define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 5931#define G_FW_PORT_CMD_MDIOCAP(x) \ 5932 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 5933#define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 5934 5935#define S_FW_PORT_CMD_MDIOADDR 16 5936#define M_FW_PORT_CMD_MDIOADDR 0x1f 5937#define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 5938#define G_FW_PORT_CMD_MDIOADDR(x) \ 5939 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 5940 5941#define S_FW_PORT_CMD_LPTXPAUSE 15 5942#define M_FW_PORT_CMD_LPTXPAUSE 0x1 5943#define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 5944#define G_FW_PORT_CMD_LPTXPAUSE(x) \ 5945 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 5946#define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 5947 5948#define S_FW_PORT_CMD_LPRXPAUSE 14 5949#define M_FW_PORT_CMD_LPRXPAUSE 0x1 5950#define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 5951#define G_FW_PORT_CMD_LPRXPAUSE(x) \ 5952 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 5953#define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 5954 5955#define S_FW_PORT_CMD_PTYPE 8 5956#define M_FW_PORT_CMD_PTYPE 0x1f 5957#define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 5958#define G_FW_PORT_CMD_PTYPE(x) \ 5959 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 5960 5961#define S_FW_PORT_CMD_LINKDNRC 5 5962#define M_FW_PORT_CMD_LINKDNRC 0x7 5963#define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 5964#define G_FW_PORT_CMD_LINKDNRC(x) \ 5965 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 5966 5967#define S_FW_PORT_CMD_MODTYPE 0 5968#define M_FW_PORT_CMD_MODTYPE 0x1f 5969#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 5970#define G_FW_PORT_CMD_MODTYPE(x) \ 5971 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 5972 5973#define S_FW_PORT_CMD_DCBXDIS 7 5974#define M_FW_PORT_CMD_DCBXDIS 0x1 5975#define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 5976#define G_FW_PORT_CMD_DCBXDIS(x) \ 5977 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 5978#define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 5979 5980#define S_FW_PORT_CMD_APPLY 7 5981#define M_FW_PORT_CMD_APPLY 0x1 5982#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 5983#define G_FW_PORT_CMD_APPLY(x) \ 5984 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 5985#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 5986 5987#define S_FW_PORT_CMD_ALL_SYNCD 7 5988#define M_FW_PORT_CMD_ALL_SYNCD 0x1 5989#define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 5990#define G_FW_PORT_CMD_ALL_SYNCD(x) \ 5991 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 5992#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 5993 5994#define S_FW_PORT_CMD_PFC_STATE 8 5995#define M_FW_PORT_CMD_PFC_STATE 0xf 5996#define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 5997#define G_FW_PORT_CMD_PFC_STATE(x) \ 5998 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 5999 6000#define S_FW_PORT_CMD_ETS_STATE 4 6001#define M_FW_PORT_CMD_ETS_STATE 0xf 6002#define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 6003#define G_FW_PORT_CMD_ETS_STATE(x) \ 6004 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 6005 6006#define S_FW_PORT_CMD_APP_STATE 0 6007#define M_FW_PORT_CMD_APP_STATE 0xf 6008#define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 6009#define G_FW_PORT_CMD_APP_STATE(x) \ 6010 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 6011 6012/* 6013 * These are configured into the VPD and hence tools that generate 6014 * VPD may use this enumeration. 6015 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 6016 * 6017 * REMEMBER: 6018 * Update the Common Code t4_hw.c:t4_get_port_type_description() 6019 * with any new Firmware Port Technology Types! 6020 */ 6021enum fw_port_type { 6022 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 6023 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 6024 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 6025 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 6026 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 6027 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 6028 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 6029 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 6030 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 6031 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 6032 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 6033 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 6034 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 6035 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 6036 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 6037 6038 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 6039}; 6040 6041/* These are read from module's EEPROM and determined once the 6042 module is inserted. */ 6043enum fw_port_module_type { 6044 FW_PORT_MOD_TYPE_NA = 0x0, 6045 FW_PORT_MOD_TYPE_LR = 0x1, 6046 FW_PORT_MOD_TYPE_SR = 0x2, 6047 FW_PORT_MOD_TYPE_ER = 0x3, 6048 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 6049 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 6050 FW_PORT_MOD_TYPE_LRM = 0x6, 6051 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 6052 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 6053 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 6054 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 6055}; 6056 6057/* used by FW and tools may use this to generate VPD */ 6058enum fw_port_mod_sub_type { 6059 FW_PORT_MOD_SUB_TYPE_NA, 6060 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 6061 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 6062 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 6063 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 6064 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 6065 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 6066 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 6067 6068 /* 6069 * The following will never been in the VPD. They are TWINAX cable 6070 * lengths decoded from SFP+ module i2c PROMs. These should almost 6071 * certainly go somewhere else ... 6072 */ 6073 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 6074 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 6075 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 6076 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 6077}; 6078 6079/* link down reason codes (3b) */ 6080enum fw_port_link_dn_rc { 6081 FW_PORT_LINK_DN_RC_NONE, 6082 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 6083 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 6084 FW_PORT_LINK_DN_RESERVED3, 6085 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 6086 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 6087 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 6088 FW_PORT_LINK_DN_RESERVED7 6089}; 6090 6091/* port stats */ 6092#define FW_NUM_PORT_STATS 50 6093#define FW_NUM_PORT_TX_STATS 23 6094#define FW_NUM_PORT_RX_STATS 27 6095 6096enum fw_port_stats_tx_index { 6097 FW_STAT_TX_PORT_BYTES_IX, 6098 FW_STAT_TX_PORT_FRAMES_IX, 6099 FW_STAT_TX_PORT_BCAST_IX, 6100 FW_STAT_TX_PORT_MCAST_IX, 6101 FW_STAT_TX_PORT_UCAST_IX, 6102 FW_STAT_TX_PORT_ERROR_IX, 6103 FW_STAT_TX_PORT_64B_IX, 6104 FW_STAT_TX_PORT_65B_127B_IX, 6105 FW_STAT_TX_PORT_128B_255B_IX, 6106 FW_STAT_TX_PORT_256B_511B_IX, 6107 FW_STAT_TX_PORT_512B_1023B_IX, 6108 FW_STAT_TX_PORT_1024B_1518B_IX, 6109 FW_STAT_TX_PORT_1519B_MAX_IX, 6110 FW_STAT_TX_PORT_DROP_IX, 6111 FW_STAT_TX_PORT_PAUSE_IX, 6112 FW_STAT_TX_PORT_PPP0_IX, 6113 FW_STAT_TX_PORT_PPP1_IX, 6114 FW_STAT_TX_PORT_PPP2_IX, 6115 FW_STAT_TX_PORT_PPP3_IX, 6116 FW_STAT_TX_PORT_PPP4_IX, 6117 FW_STAT_TX_PORT_PPP5_IX, 6118 FW_STAT_TX_PORT_PPP6_IX, 6119 FW_STAT_TX_PORT_PPP7_IX 6120}; 6121 6122enum fw_port_stat_rx_index { 6123 FW_STAT_RX_PORT_BYTES_IX, 6124 FW_STAT_RX_PORT_FRAMES_IX, 6125 FW_STAT_RX_PORT_BCAST_IX, 6126 FW_STAT_RX_PORT_MCAST_IX, 6127 FW_STAT_RX_PORT_UCAST_IX, 6128 FW_STAT_RX_PORT_MTU_ERROR_IX, 6129 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 6130 FW_STAT_RX_PORT_CRC_ERROR_IX, 6131 FW_STAT_RX_PORT_LEN_ERROR_IX, 6132 FW_STAT_RX_PORT_SYM_ERROR_IX, 6133 FW_STAT_RX_PORT_64B_IX, 6134 FW_STAT_RX_PORT_65B_127B_IX, 6135 FW_STAT_RX_PORT_128B_255B_IX, 6136 FW_STAT_RX_PORT_256B_511B_IX, 6137 FW_STAT_RX_PORT_512B_1023B_IX, 6138 FW_STAT_RX_PORT_1024B_1518B_IX, 6139 FW_STAT_RX_PORT_1519B_MAX_IX, 6140 FW_STAT_RX_PORT_PAUSE_IX, 6141 FW_STAT_RX_PORT_PPP0_IX, 6142 FW_STAT_RX_PORT_PPP1_IX, 6143 FW_STAT_RX_PORT_PPP2_IX, 6144 FW_STAT_RX_PORT_PPP3_IX, 6145 FW_STAT_RX_PORT_PPP4_IX, 6146 FW_STAT_RX_PORT_PPP5_IX, 6147 FW_STAT_RX_PORT_PPP6_IX, 6148 FW_STAT_RX_PORT_PPP7_IX, 6149 FW_STAT_RX_PORT_LESS_64B_IX 6150}; 6151 6152struct fw_port_stats_cmd { 6153 __be32 op_to_portid; 6154 __be32 retval_len16; 6155 union fw_port_stats { 6156 struct fw_port_stats_ctl { 6157 __u8 nstats_bg_bm; 6158 __u8 tx_ix; 6159 __be16 r6; 6160 __be32 r7; 6161 __be64 stat0; 6162 __be64 stat1; 6163 __be64 stat2; 6164 __be64 stat3; 6165 __be64 stat4; 6166 __be64 stat5; 6167 } ctl; 6168 struct fw_port_stats_all { 6169 __be64 tx_bytes; 6170 __be64 tx_frames; 6171 __be64 tx_bcast; 6172 __be64 tx_mcast; 6173 __be64 tx_ucast; 6174 __be64 tx_error; 6175 __be64 tx_64b; 6176 __be64 tx_65b_127b; 6177 __be64 tx_128b_255b; 6178 __be64 tx_256b_511b; 6179 __be64 tx_512b_1023b; 6180 __be64 tx_1024b_1518b; 6181 __be64 tx_1519b_max; 6182 __be64 tx_drop; 6183 __be64 tx_pause; 6184 __be64 tx_ppp0; 6185 __be64 tx_ppp1; 6186 __be64 tx_ppp2; 6187 __be64 tx_ppp3; 6188 __be64 tx_ppp4; 6189 __be64 tx_ppp5; 6190 __be64 tx_ppp6; 6191 __be64 tx_ppp7; 6192 __be64 rx_bytes; 6193 __be64 rx_frames; 6194 __be64 rx_bcast; 6195 __be64 rx_mcast; 6196 __be64 rx_ucast; 6197 __be64 rx_mtu_error; 6198 __be64 rx_mtu_crc_error; 6199 __be64 rx_crc_error; 6200 __be64 rx_len_error; 6201 __be64 rx_sym_error; 6202 __be64 rx_64b; 6203 __be64 rx_65b_127b; 6204 __be64 rx_128b_255b; 6205 __be64 rx_256b_511b; 6206 __be64 rx_512b_1023b; 6207 __be64 rx_1024b_1518b; 6208 __be64 rx_1519b_max; 6209 __be64 rx_pause; 6210 __be64 rx_ppp0; 6211 __be64 rx_ppp1; 6212 __be64 rx_ppp2; 6213 __be64 rx_ppp3; 6214 __be64 rx_ppp4; 6215 __be64 rx_ppp5; 6216 __be64 rx_ppp6; 6217 __be64 rx_ppp7; 6218 __be64 rx_less_64b; 6219 __be64 rx_bg_drop; 6220 __be64 rx_bg_trunc; 6221 } all; 6222 } u; 6223}; 6224 6225#define S_FW_PORT_STATS_CMD_NSTATS 4 6226#define M_FW_PORT_STATS_CMD_NSTATS 0x7 6227#define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 6228#define G_FW_PORT_STATS_CMD_NSTATS(x) \ 6229 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 6230 6231#define S_FW_PORT_STATS_CMD_BG_BM 0 6232#define M_FW_PORT_STATS_CMD_BG_BM 0x3 6233#define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 6234#define G_FW_PORT_STATS_CMD_BG_BM(x) \ 6235 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 6236 6237#define S_FW_PORT_STATS_CMD_TX 7 6238#define M_FW_PORT_STATS_CMD_TX 0x1 6239#define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 6240#define G_FW_PORT_STATS_CMD_TX(x) \ 6241 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 6242#define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 6243 6244#define S_FW_PORT_STATS_CMD_IX 0 6245#define M_FW_PORT_STATS_CMD_IX 0x3f 6246#define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 6247#define G_FW_PORT_STATS_CMD_IX(x) \ 6248 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 6249 6250/* port loopback stats */ 6251#define FW_NUM_LB_STATS 14 6252enum fw_port_lb_stats_index { 6253 FW_STAT_LB_PORT_BYTES_IX, 6254 FW_STAT_LB_PORT_FRAMES_IX, 6255 FW_STAT_LB_PORT_BCAST_IX, 6256 FW_STAT_LB_PORT_MCAST_IX, 6257 FW_STAT_LB_PORT_UCAST_IX, 6258 FW_STAT_LB_PORT_ERROR_IX, 6259 FW_STAT_LB_PORT_64B_IX, 6260 FW_STAT_LB_PORT_65B_127B_IX, 6261 FW_STAT_LB_PORT_128B_255B_IX, 6262 FW_STAT_LB_PORT_256B_511B_IX, 6263 FW_STAT_LB_PORT_512B_1023B_IX, 6264 FW_STAT_LB_PORT_1024B_1518B_IX, 6265 FW_STAT_LB_PORT_1519B_MAX_IX, 6266 FW_STAT_LB_PORT_DROP_FRAMES_IX 6267}; 6268 6269struct fw_port_lb_stats_cmd { 6270 __be32 op_to_lbport; 6271 __be32 retval_len16; 6272 union fw_port_lb_stats { 6273 struct fw_port_lb_stats_ctl { 6274 __u8 nstats_bg_bm; 6275 __u8 ix_pkd; 6276 __be16 r6; 6277 __be32 r7; 6278 __be64 stat0; 6279 __be64 stat1; 6280 __be64 stat2; 6281 __be64 stat3; 6282 __be64 stat4; 6283 __be64 stat5; 6284 } ctl; 6285 struct fw_port_lb_stats_all { 6286 __be64 tx_bytes; 6287 __be64 tx_frames; 6288 __be64 tx_bcast; 6289 __be64 tx_mcast; 6290 __be64 tx_ucast; 6291 __be64 tx_error; 6292 __be64 tx_64b; 6293 __be64 tx_65b_127b; 6294 __be64 tx_128b_255b; 6295 __be64 tx_256b_511b; 6296 __be64 tx_512b_1023b; 6297 __be64 tx_1024b_1518b; 6298 __be64 tx_1519b_max; 6299 __be64 rx_lb_drop; 6300 __be64 rx_lb_trunc; 6301 } all; 6302 } u; 6303}; 6304 6305#define S_FW_PORT_LB_STATS_CMD_LBPORT 0 6306#define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 6307#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6308 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 6309#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6310 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 6311 6312#define S_FW_PORT_LB_STATS_CMD_NSTATS 4 6313#define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 6314#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6315 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 6316#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6317 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 6318 6319#define S_FW_PORT_LB_STATS_CMD_BG_BM 0 6320#define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 6321#define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 6322#define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 6323 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 6324 6325#define S_FW_PORT_LB_STATS_CMD_IX 0 6326#define M_FW_PORT_LB_STATS_CMD_IX 0xf 6327#define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 6328#define G_FW_PORT_LB_STATS_CMD_IX(x) \ 6329 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 6330 6331/* Trace related defines */ 6332#define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 6333#define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 6334 6335struct fw_port_trace_cmd { 6336 __be32 op_to_portid; 6337 __be32 retval_len16; 6338 __be16 traceen_to_pciech; 6339 __be16 qnum; 6340 __be32 r5; 6341}; 6342 6343#define S_FW_PORT_TRACE_CMD_PORTID 0 6344#define M_FW_PORT_TRACE_CMD_PORTID 0xf 6345#define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 6346#define G_FW_PORT_TRACE_CMD_PORTID(x) \ 6347 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 6348 6349#define S_FW_PORT_TRACE_CMD_TRACEEN 15 6350#define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 6351#define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 6352#define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 6353 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 6354#define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 6355 6356#define S_FW_PORT_TRACE_CMD_FLTMODE 14 6357#define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 6358#define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 6359#define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 6360 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 6361#define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 6362 6363#define S_FW_PORT_TRACE_CMD_DUPLEN 13 6364#define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 6365#define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 6366#define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 6367 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 6368#define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 6369 6370#define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 6371#define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 6372#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6373 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6374#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6375 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 6376 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6377 6378#define S_FW_PORT_TRACE_CMD_PCIECH 6 6379#define M_FW_PORT_TRACE_CMD_PCIECH 0x3 6380#define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 6381#define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 6382 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 6383 6384struct fw_port_trace_mmap_cmd { 6385 __be32 op_to_portid; 6386 __be32 retval_len16; 6387 __be32 fid_to_skipoffset; 6388 __be32 minpktsize_capturemax; 6389 __u8 map[224]; 6390}; 6391 6392#define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 6393#define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 6394#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6395 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 6396#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6397 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 6398 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 6399 6400#define S_FW_PORT_TRACE_MMAP_CMD_FID 30 6401#define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 6402#define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 6403#define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 6404 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 6405 6406#define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 6407#define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 6408#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6409 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6410#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6411 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 6412 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6413#define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 6414 6415#define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 6416#define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 6417#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6418 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6419#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6420 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 6421 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6422#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \ 6423 V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 6424 6425#define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 6426#define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 6427#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6428 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6429#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6430 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 6431 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6432 6433#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 6434#define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 6435#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6436 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6437#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6438 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 6439 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6440 6441#define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 6442#define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 6443#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6444 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6445#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6446 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 6447 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6448 6449#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 6450#define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 6451#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6452 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6453#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6454 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 6455 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6456 6457struct fw_rss_ind_tbl_cmd { 6458 __be32 op_to_viid; 6459 __be32 retval_len16; 6460 __be16 niqid; 6461 __be16 startidx; 6462 __be32 r3; 6463 __be32 iq0_to_iq2; 6464 __be32 iq3_to_iq5; 6465 __be32 iq6_to_iq8; 6466 __be32 iq9_to_iq11; 6467 __be32 iq12_to_iq14; 6468 __be32 iq15_to_iq17; 6469 __be32 iq18_to_iq20; 6470 __be32 iq21_to_iq23; 6471 __be32 iq24_to_iq26; 6472 __be32 iq27_to_iq29; 6473 __be32 iq30_iq31; 6474 __be32 r15_lo; 6475}; 6476 6477#define S_FW_RSS_IND_TBL_CMD_VIID 0 6478#define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 6479#define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 6480#define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 6481 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 6482 6483#define S_FW_RSS_IND_TBL_CMD_IQ0 20 6484#define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 6485#define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 6486#define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 6487 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 6488 6489#define S_FW_RSS_IND_TBL_CMD_IQ1 10 6490#define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 6491#define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 6492#define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 6493 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 6494 6495#define S_FW_RSS_IND_TBL_CMD_IQ2 0 6496#define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 6497#define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 6498#define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 6499 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 6500 6501#define S_FW_RSS_IND_TBL_CMD_IQ3 20 6502#define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 6503#define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 6504#define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 6505 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 6506 6507#define S_FW_RSS_IND_TBL_CMD_IQ4 10 6508#define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 6509#define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 6510#define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 6511 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 6512 6513#define S_FW_RSS_IND_TBL_CMD_IQ5 0 6514#define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 6515#define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 6516#define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 6517 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 6518 6519#define S_FW_RSS_IND_TBL_CMD_IQ6 20 6520#define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 6521#define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 6522#define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 6523 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 6524 6525#define S_FW_RSS_IND_TBL_CMD_IQ7 10 6526#define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 6527#define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 6528#define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 6529 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 6530 6531#define S_FW_RSS_IND_TBL_CMD_IQ8 0 6532#define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 6533#define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 6534#define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 6535 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 6536 6537#define S_FW_RSS_IND_TBL_CMD_IQ9 20 6538#define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 6539#define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 6540#define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 6541 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 6542 6543#define S_FW_RSS_IND_TBL_CMD_IQ10 10 6544#define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 6545#define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 6546#define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 6547 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 6548 6549#define S_FW_RSS_IND_TBL_CMD_IQ11 0 6550#define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 6551#define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 6552#define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 6553 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 6554 6555#define S_FW_RSS_IND_TBL_CMD_IQ12 20 6556#define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 6557#define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 6558#define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 6559 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 6560 6561#define S_FW_RSS_IND_TBL_CMD_IQ13 10 6562#define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 6563#define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 6564#define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 6565 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 6566 6567#define S_FW_RSS_IND_TBL_CMD_IQ14 0 6568#define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 6569#define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 6570#define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 6571 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 6572 6573#define S_FW_RSS_IND_TBL_CMD_IQ15 20 6574#define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 6575#define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 6576#define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 6577 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 6578 6579#define S_FW_RSS_IND_TBL_CMD_IQ16 10 6580#define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 6581#define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 6582#define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 6583 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 6584 6585#define S_FW_RSS_IND_TBL_CMD_IQ17 0 6586#define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 6587#define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 6588#define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 6589 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 6590 6591#define S_FW_RSS_IND_TBL_CMD_IQ18 20 6592#define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 6593#define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 6594#define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 6595 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 6596 6597#define S_FW_RSS_IND_TBL_CMD_IQ19 10 6598#define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 6599#define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 6600#define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 6601 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 6602 6603#define S_FW_RSS_IND_TBL_CMD_IQ20 0 6604#define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 6605#define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 6606#define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 6607 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 6608 6609#define S_FW_RSS_IND_TBL_CMD_IQ21 20 6610#define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 6611#define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 6612#define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 6613 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 6614 6615#define S_FW_RSS_IND_TBL_CMD_IQ22 10 6616#define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 6617#define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 6618#define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 6619 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 6620 6621#define S_FW_RSS_IND_TBL_CMD_IQ23 0 6622#define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 6623#define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 6624#define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 6625 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 6626 6627#define S_FW_RSS_IND_TBL_CMD_IQ24 20 6628#define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 6629#define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 6630#define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 6631 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 6632 6633#define S_FW_RSS_IND_TBL_CMD_IQ25 10 6634#define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 6635#define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 6636#define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 6637 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 6638 6639#define S_FW_RSS_IND_TBL_CMD_IQ26 0 6640#define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 6641#define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 6642#define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 6643 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 6644 6645#define S_FW_RSS_IND_TBL_CMD_IQ27 20 6646#define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 6647#define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 6648#define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 6649 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 6650 6651#define S_FW_RSS_IND_TBL_CMD_IQ28 10 6652#define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 6653#define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 6654#define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 6655 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 6656 6657#define S_FW_RSS_IND_TBL_CMD_IQ29 0 6658#define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 6659#define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 6660#define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 6661 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 6662 6663#define S_FW_RSS_IND_TBL_CMD_IQ30 20 6664#define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 6665#define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 6666#define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 6667 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 6668 6669#define S_FW_RSS_IND_TBL_CMD_IQ31 10 6670#define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 6671#define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 6672#define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 6673 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 6674 6675struct fw_rss_glb_config_cmd { 6676 __be32 op_to_write; 6677 __be32 retval_len16; 6678 union fw_rss_glb_config { 6679 struct fw_rss_glb_config_manual { 6680 __be32 mode_pkd; 6681 __be32 r3; 6682 __be64 r4; 6683 __be64 r5; 6684 } manual; 6685 struct fw_rss_glb_config_basicvirtual { 6686 __be32 mode_pkd; 6687 __be32 synmapen_to_hashtoeplitz; 6688 __be64 r8; 6689 __be64 r9; 6690 } basicvirtual; 6691 } u; 6692}; 6693 6694#define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 6695#define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 6696#define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 6697#define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 6698 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 6699 6700#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 6701#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 6702#define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 6703 6704#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 6705#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 6706#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6707 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6708#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6709 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 6710 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6711#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \ 6712 V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 6713 6714#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 6715#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 6716#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6717 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6718#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6719 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 6720 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6721#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 6722 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 6723 6724#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 6725#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 6726#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6727 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6728#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6729 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 6730 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6731#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 6732 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 6733 6734#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 6735#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 6736#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6737 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6738#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6739 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 6740 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6741#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 6742 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 6743 6744#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 6745#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 6746#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6747 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6748#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6749 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 6750 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6751#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 6752 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 6753 6754#define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 6755#define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 6756#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6757 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6758#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6759 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 6760 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6761#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \ 6762 V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 6763 6764#define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 6765#define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 6766#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6767 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6768#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6769 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 6770 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6771#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \ 6772 V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 6773 6774#define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 6775#define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 6776#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6777 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6778#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6779 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 6780 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6781#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 6782 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 6783 6784#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 6785#define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 6786#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6787 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6788#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6789 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 6790 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6791#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 6792 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 6793 6794struct fw_rss_vi_config_cmd { 6795 __be32 op_to_viid; 6796 __be32 retval_len16; 6797 union fw_rss_vi_config { 6798 struct fw_rss_vi_config_manual { 6799 __be64 r3; 6800 __be64 r4; 6801 __be64 r5; 6802 } manual; 6803 struct fw_rss_vi_config_basicvirtual { 6804 __be32 r6; 6805 __be32 defaultq_to_udpen; 6806 __be64 r9; 6807 __be64 r10; 6808 } basicvirtual; 6809 } u; 6810}; 6811 6812#define S_FW_RSS_VI_CONFIG_CMD_VIID 0 6813#define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 6814#define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 6815#define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 6816 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 6817 6818#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 6819#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 6820#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6821 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6822#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6823 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 6824 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6825 6826#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 6827#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 6828#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6829 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6830#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6831 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 6832 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6833#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 6834 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 6835 6836#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 6837#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 6838#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6839 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6840#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6841 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 6842 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6843#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 6844 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 6845 6846#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 6847#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 6848#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6849 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6850#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6851 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 6852 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6853#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 6854 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 6855 6856#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 6857#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 6858#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6859 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6860#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6861 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 6862 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6863#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 6864 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 6865 6866#define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 6867#define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 6868#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 6869#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 6870 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 6871#define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 6872 6873enum fw_sched_sc { 6874 FW_SCHED_SC_CONFIG = 0, 6875 FW_SCHED_SC_PARAMS = 1, 6876}; 6877 6878enum fw_sched_type { 6879 FW_SCHED_TYPE_PKTSCHED = 0, 6880 FW_SCHED_TYPE_STREAMSCHED = 1, 6881}; 6882 6883enum fw_sched_params_level { 6884 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 6885 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 6886 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 6887}; 6888 6889enum fw_sched_params_mode { 6890 FW_SCHED_PARAMS_MODE_CLASS = 0, 6891 FW_SCHED_PARAMS_MODE_FLOW = 1, 6892}; 6893 6894enum fw_sched_params_unit { 6895 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 6896 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 6897}; 6898 6899enum fw_sched_params_rate { 6900 FW_SCHED_PARAMS_RATE_REL = 0, 6901 FW_SCHED_PARAMS_RATE_ABS = 1, 6902}; 6903 6904struct fw_sched_cmd { 6905 __be32 op_to_write; 6906 __be32 retval_len16; 6907 union fw_sched { 6908 struct fw_sched_config { 6909 __u8 sc; 6910 __u8 type; 6911 __u8 minmaxen; 6912 __u8 r3[5]; 6913 __u8 nclasses[4]; 6914 __be32 r4; 6915 } config; 6916 struct fw_sched_params { 6917 __u8 sc; 6918 __u8 type; 6919 __u8 level; 6920 __u8 mode; 6921 __u8 unit; 6922 __u8 rate; 6923 __u8 ch; 6924 __u8 cl; 6925 __be32 min; 6926 __be32 max; 6927 __be16 weight; 6928 __be16 pktsize; 6929 __be16 burstsize; 6930 __be16 r4; 6931 } params; 6932 } u; 6933}; 6934 6935/* 6936 * length of the formatting string 6937 */ 6938#define FW_DEVLOG_FMT_LEN 192 6939 6940/* 6941 * maximum number of the formatting string parameters 6942 */ 6943#define FW_DEVLOG_FMT_PARAMS_NUM 8 6944 6945/* 6946 * priority levels 6947 */ 6948enum fw_devlog_level { 6949 FW_DEVLOG_LEVEL_EMERG = 0x0, 6950 FW_DEVLOG_LEVEL_CRIT = 0x1, 6951 FW_DEVLOG_LEVEL_ERR = 0x2, 6952 FW_DEVLOG_LEVEL_NOTICE = 0x3, 6953 FW_DEVLOG_LEVEL_INFO = 0x4, 6954 FW_DEVLOG_LEVEL_DEBUG = 0x5, 6955 FW_DEVLOG_LEVEL_MAX = 0x5, 6956}; 6957 6958/* 6959 * facilities that may send a log message 6960 */ 6961enum fw_devlog_facility { 6962 FW_DEVLOG_FACILITY_CORE = 0x00, 6963 FW_DEVLOG_FACILITY_CF = 0x01, 6964 FW_DEVLOG_FACILITY_SCHED = 0x02, 6965 FW_DEVLOG_FACILITY_TIMER = 0x04, 6966 FW_DEVLOG_FACILITY_RES = 0x06, 6967 FW_DEVLOG_FACILITY_HW = 0x08, 6968 FW_DEVLOG_FACILITY_FLR = 0x10, 6969 FW_DEVLOG_FACILITY_DMAQ = 0x12, 6970 FW_DEVLOG_FACILITY_PHY = 0x14, 6971 FW_DEVLOG_FACILITY_MAC = 0x16, 6972 FW_DEVLOG_FACILITY_PORT = 0x18, 6973 FW_DEVLOG_FACILITY_VI = 0x1A, 6974 FW_DEVLOG_FACILITY_FILTER = 0x1C, 6975 FW_DEVLOG_FACILITY_ACL = 0x1E, 6976 FW_DEVLOG_FACILITY_TM = 0x20, 6977 FW_DEVLOG_FACILITY_QFC = 0x22, 6978 FW_DEVLOG_FACILITY_DCB = 0x24, 6979 FW_DEVLOG_FACILITY_ETH = 0x26, 6980 FW_DEVLOG_FACILITY_OFLD = 0x28, 6981 FW_DEVLOG_FACILITY_RI = 0x2A, 6982 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 6983 FW_DEVLOG_FACILITY_FCOE = 0x2E, 6984 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 6985 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 6986 FW_DEVLOG_FACILITY_MAX = 0x32, 6987}; 6988 6989/* 6990 * log message format 6991 */ 6992struct fw_devlog_e { 6993 __be64 timestamp; 6994 __be32 seqno; 6995 __be16 reserved1; 6996 __u8 level; 6997 __u8 facility; 6998 __u8 fmt[FW_DEVLOG_FMT_LEN]; 6999 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 7000 __be32 reserved3[4]; 7001}; 7002 7003struct fw_devlog_cmd { 7004 __be32 op_to_write; 7005 __be32 retval_len16; 7006 __u8 level; 7007 __u8 r2[7]; 7008 __be32 memtype_devlog_memaddr16_devlog; 7009 __be32 memsize_devlog; 7010 __be32 r3[2]; 7011}; 7012 7013#define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 7014#define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 7015#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 7016 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 7017#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 7018 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 7019 7020#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 7021#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 7022#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 7023 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 7024#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 7025 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 7026 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 7027 7028enum fw_watchdog_actions { 7029 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 7030 FW_WATCHDOG_ACTION_FLR = 1, 7031 FW_WATCHDOG_ACTION_BYPASS = 2, 7032 FW_WATCHDOG_ACTION_TMPCHK = 3, 7033 7034 FW_WATCHDOG_ACTION_MAX = 4, 7035}; 7036 7037#define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 7038 7039struct fw_watchdog_cmd { 7040 __be32 op_to_vfn; 7041 __be32 retval_len16; 7042 __be32 timeout; 7043 __be32 action; 7044}; 7045 7046#define S_FW_WATCHDOG_CMD_PFN 8 7047#define M_FW_WATCHDOG_CMD_PFN 0x7 7048#define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 7049#define G_FW_WATCHDOG_CMD_PFN(x) \ 7050 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 7051 7052#define S_FW_WATCHDOG_CMD_VFN 0 7053#define M_FW_WATCHDOG_CMD_VFN 0xff 7054#define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 7055#define G_FW_WATCHDOG_CMD_VFN(x) \ 7056 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 7057 7058struct fw_clip_cmd { 7059 __be32 op_to_write; 7060 __be32 alloc_to_len16; 7061 __be64 ip_hi; 7062 __be64 ip_lo; 7063 __be32 r4[2]; 7064}; 7065 7066#define S_FW_CLIP_CMD_ALLOC 31 7067#define M_FW_CLIP_CMD_ALLOC 0x1 7068#define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 7069#define G_FW_CLIP_CMD_ALLOC(x) \ 7070 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 7071#define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 7072 7073#define S_FW_CLIP_CMD_FREE 30 7074#define M_FW_CLIP_CMD_FREE 0x1 7075#define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 7076#define G_FW_CLIP_CMD_FREE(x) \ 7077 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 7078#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 7079 7080/****************************************************************************** 7081 * F O i S C S I C O M M A N D s 7082 **************************************/ 7083 7084#define FW_CHNET_IFACE_ADDR_MAX 3 7085 7086enum fw_chnet_iface_cmd_subop { 7087 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 7088 7089 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 7090 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 7091 7092 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 7093 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 7094 7095 FW_CHNET_IFACE_CMD_SUBOP_MAX, 7096}; 7097 7098struct fw_chnet_iface_cmd { 7099 __be32 op_to_portid; 7100 __be32 retval_len16; 7101 __u8 subop; 7102 __u8 r2[3]; 7103 __be32 ifid_ifstate; 7104 __be16 mtu; 7105 __be16 vlanid; 7106 __be32 r3; 7107 __be16 r4; 7108 __u8 mac[6]; 7109}; 7110 7111#define S_FW_CHNET_IFACE_CMD_PORTID 0 7112#define M_FW_CHNET_IFACE_CMD_PORTID 0xf 7113#define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 7114#define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 7115 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 7116 7117#define S_FW_CHNET_IFACE_CMD_IFID 8 7118#define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 7119#define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 7120#define G_FW_CHNET_IFACE_CMD_IFID(x) \ 7121 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 7122 7123#define S_FW_CHNET_IFACE_CMD_IFSTATE 0 7124#define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 7125#define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 7126#define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 7127 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 7128 7129/****************************************************************************** 7130 * F O F C O E C O M M A N D s 7131 ************************************/ 7132 7133struct fw_fcoe_res_info_cmd { 7134 __be32 op_to_read; 7135 __be32 retval_len16; 7136 __be16 e_d_tov; 7137 __be16 r_a_tov_seq; 7138 __be16 r_a_tov_els; 7139 __be16 r_r_tov; 7140 __be32 max_xchgs; 7141 __be32 max_ssns; 7142 __be32 used_xchgs; 7143 __be32 used_ssns; 7144 __be32 max_fcfs; 7145 __be32 max_vnps; 7146 __be32 used_fcfs; 7147 __be32 used_vnps; 7148}; 7149 7150struct fw_fcoe_link_cmd { 7151 __be32 op_to_portid; 7152 __be32 retval_len16; 7153 __be32 sub_opcode_fcfi; 7154 __u8 r3; 7155 __u8 lstatus; 7156 __be16 flags; 7157 __u8 r4; 7158 __u8 set_vlan; 7159 __be16 vlan_id; 7160 __be32 vnpi_pkd; 7161 __be16 r6; 7162 __u8 phy_mac[6]; 7163 __u8 vnport_wwnn[8]; 7164 __u8 vnport_wwpn[8]; 7165}; 7166 7167#define S_FW_FCOE_LINK_CMD_PORTID 0 7168#define M_FW_FCOE_LINK_CMD_PORTID 0xf 7169#define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 7170#define G_FW_FCOE_LINK_CMD_PORTID(x) \ 7171 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 7172 7173#define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 7174#define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 7175#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7176 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 7177#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7178 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 7179 7180#define S_FW_FCOE_LINK_CMD_FCFI 0 7181#define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 7182#define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 7183#define G_FW_FCOE_LINK_CMD_FCFI(x) \ 7184 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 7185 7186#define S_FW_FCOE_LINK_CMD_VNPI 0 7187#define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 7188#define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 7189#define G_FW_FCOE_LINK_CMD_VNPI(x) \ 7190 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 7191 7192struct fw_fcoe_vnp_cmd { 7193 __be32 op_to_fcfi; 7194 __be32 alloc_to_len16; 7195 __be32 gen_wwn_to_vnpi; 7196 __be32 vf_id; 7197 __be16 iqid; 7198 __u8 vnport_mac[6]; 7199 __u8 vnport_wwnn[8]; 7200 __u8 vnport_wwpn[8]; 7201 __u8 cmn_srv_parms[16]; 7202 __u8 clsp_word_0_1[8]; 7203}; 7204 7205#define S_FW_FCOE_VNP_CMD_FCFI 0 7206#define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 7207#define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 7208#define G_FW_FCOE_VNP_CMD_FCFI(x) \ 7209 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 7210 7211#define S_FW_FCOE_VNP_CMD_ALLOC 31 7212#define M_FW_FCOE_VNP_CMD_ALLOC 0x1 7213#define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 7214#define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 7215 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 7216#define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 7217 7218#define S_FW_FCOE_VNP_CMD_FREE 30 7219#define M_FW_FCOE_VNP_CMD_FREE 0x1 7220#define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 7221#define G_FW_FCOE_VNP_CMD_FREE(x) \ 7222 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 7223#define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 7224 7225#define S_FW_FCOE_VNP_CMD_MODIFY 29 7226#define M_FW_FCOE_VNP_CMD_MODIFY 0x1 7227#define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 7228#define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 7229 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 7230#define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 7231 7232#define S_FW_FCOE_VNP_CMD_GEN_WWN 22 7233#define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 7234#define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 7235#define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 7236 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 7237#define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 7238 7239#define S_FW_FCOE_VNP_CMD_PERSIST 21 7240#define M_FW_FCOE_VNP_CMD_PERSIST 0x1 7241#define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 7242#define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 7243 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 7244#define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 7245 7246#define S_FW_FCOE_VNP_CMD_VFID_EN 20 7247#define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 7248#define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 7249#define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 7250 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 7251#define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 7252 7253#define S_FW_FCOE_VNP_CMD_VNPI 0 7254#define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 7255#define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 7256#define G_FW_FCOE_VNP_CMD_VNPI(x) \ 7257 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 7258 7259struct fw_fcoe_sparams_cmd { 7260 __be32 op_to_portid; 7261 __be32 retval_len16; 7262 __u8 r3[7]; 7263 __u8 cos; 7264 __u8 lport_wwnn[8]; 7265 __u8 lport_wwpn[8]; 7266 __u8 cmn_srv_parms[16]; 7267 __u8 cls_srv_parms[16]; 7268}; 7269 7270#define S_FW_FCOE_SPARAMS_CMD_PORTID 0 7271#define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 7272#define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 7273#define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 7274 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 7275 7276struct fw_fcoe_stats_cmd { 7277 __be32 op_to_flowid; 7278 __be32 free_to_len16; 7279 union fw_fcoe_stats { 7280 struct fw_fcoe_stats_ctl { 7281 __u8 nstats_port; 7282 __u8 port_valid_ix; 7283 __be16 r6; 7284 __be32 r7; 7285 __be64 stat0; 7286 __be64 stat1; 7287 __be64 stat2; 7288 __be64 stat3; 7289 __be64 stat4; 7290 __be64 stat5; 7291 } ctl; 7292 struct fw_fcoe_port_stats { 7293 __be64 tx_bcast_bytes; 7294 __be64 tx_bcast_frames; 7295 __be64 tx_mcast_bytes; 7296 __be64 tx_mcast_frames; 7297 __be64 tx_ucast_bytes; 7298 __be64 tx_ucast_frames; 7299 __be64 tx_drop_frames; 7300 __be64 tx_offload_bytes; 7301 __be64 tx_offload_frames; 7302 __be64 rx_bcast_bytes; 7303 __be64 rx_bcast_frames; 7304 __be64 rx_mcast_bytes; 7305 __be64 rx_mcast_frames; 7306 __be64 rx_ucast_bytes; 7307 __be64 rx_ucast_frames; 7308 __be64 rx_err_frames; 7309 } port_stats; 7310 struct fw_fcoe_fcf_stats { 7311 __be32 fip_tx_bytes; 7312 __be32 fip_tx_fr; 7313 __be64 fcf_ka; 7314 __be64 mcast_adv_rcvd; 7315 __be16 ucast_adv_rcvd; 7316 __be16 sol_sent; 7317 __be16 vlan_req; 7318 __be16 vlan_rpl; 7319 __be16 clr_vlink; 7320 __be16 link_down; 7321 __be16 link_up; 7322 __be16 logo; 7323 __be16 flogi_req; 7324 __be16 flogi_rpl; 7325 __be16 fdisc_req; 7326 __be16 fdisc_rpl; 7327 __be16 fka_prd_chg; 7328 __be16 fc_map_chg; 7329 __be16 vfid_chg; 7330 __u8 no_fka_req; 7331 __u8 no_vnp; 7332 } fcf_stats; 7333 struct fw_fcoe_pcb_stats { 7334 __be64 tx_bytes; 7335 __be64 tx_frames; 7336 __be64 rx_bytes; 7337 __be64 rx_frames; 7338 __be32 vnp_ka; 7339 __be32 unsol_els_rcvd; 7340 __be64 unsol_cmd_rcvd; 7341 __be16 implicit_logo; 7342 __be16 flogi_inv_sparm; 7343 __be16 fdisc_inv_sparm; 7344 __be16 flogi_rjt; 7345 __be16 fdisc_rjt; 7346 __be16 no_ssn; 7347 __be16 mac_flt_fail; 7348 __be16 inv_fr_rcvd; 7349 } pcb_stats; 7350 struct fw_fcoe_scb_stats { 7351 __be64 tx_bytes; 7352 __be64 tx_frames; 7353 __be64 rx_bytes; 7354 __be64 rx_frames; 7355 __be32 host_abrt_req; 7356 __be32 adap_auto_abrt; 7357 __be32 adap_abrt_rsp; 7358 __be32 host_ios_req; 7359 __be16 ssn_offl_ios; 7360 __be16 ssn_not_rdy_ios; 7361 __u8 rx_data_ddp_err; 7362 __u8 ddp_flt_set_err; 7363 __be16 rx_data_fr_err; 7364 __u8 bad_st_abrt_req; 7365 __u8 no_io_abrt_req; 7366 __u8 abort_tmo; 7367 __u8 abort_tmo_2; 7368 __be32 abort_req; 7369 __u8 no_ppod_res_tmo; 7370 __u8 bp_tmo; 7371 __u8 adap_auto_cls; 7372 __u8 no_io_cls_req; 7373 __be32 host_cls_req; 7374 __be64 unsol_cmd_rcvd; 7375 __be32 plogi_req_rcvd; 7376 __be32 prli_req_rcvd; 7377 __be16 logo_req_rcvd; 7378 __be16 prlo_req_rcvd; 7379 __be16 plogi_rjt_rcvd; 7380 __be16 prli_rjt_rcvd; 7381 __be32 adisc_req_rcvd; 7382 __be32 rscn_rcvd; 7383 __be32 rrq_req_rcvd; 7384 __be32 unsol_els_rcvd; 7385 __u8 adisc_rjt_rcvd; 7386 __u8 scr_rjt; 7387 __u8 ct_rjt; 7388 __u8 inval_bls_rcvd; 7389 __be32 ba_rjt_rcvd; 7390 } scb_stats; 7391 } u; 7392}; 7393 7394#define S_FW_FCOE_STATS_CMD_FLOWID 0 7395#define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 7396#define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 7397#define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 7398 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 7399 7400#define S_FW_FCOE_STATS_CMD_FREE 30 7401#define M_FW_FCOE_STATS_CMD_FREE 0x1 7402#define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 7403#define G_FW_FCOE_STATS_CMD_FREE(x) \ 7404 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 7405#define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 7406 7407#define S_FW_FCOE_STATS_CMD_NSTATS 4 7408#define M_FW_FCOE_STATS_CMD_NSTATS 0x7 7409#define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 7410#define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 7411 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 7412 7413#define S_FW_FCOE_STATS_CMD_PORT 0 7414#define M_FW_FCOE_STATS_CMD_PORT 0x3 7415#define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 7416#define G_FW_FCOE_STATS_CMD_PORT(x) \ 7417 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 7418 7419#define S_FW_FCOE_STATS_CMD_PORT_VALID 7 7420#define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 7421#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7422 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 7423#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7424 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 7425#define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 7426 7427#define S_FW_FCOE_STATS_CMD_IX 0 7428#define M_FW_FCOE_STATS_CMD_IX 0x3f 7429#define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 7430#define G_FW_FCOE_STATS_CMD_IX(x) \ 7431 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 7432 7433struct fw_fcoe_fcf_cmd { 7434 __be32 op_to_fcfi; 7435 __be32 retval_len16; 7436 __be16 priority_pkd; 7437 __u8 mac[6]; 7438 __u8 name_id[8]; 7439 __u8 fabric[8]; 7440 __be16 vf_id; 7441 __be16 max_fcoe_size; 7442 __u8 vlan_id; 7443 __u8 fc_map[3]; 7444 __be32 fka_adv; 7445 __be32 r6; 7446 __u8 r7_hi; 7447 __u8 fpma_to_portid; 7448 __u8 spma_mac[6]; 7449 __be64 r8; 7450}; 7451 7452#define S_FW_FCOE_FCF_CMD_FCFI 0 7453#define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 7454#define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 7455#define G_FW_FCOE_FCF_CMD_FCFI(x) \ 7456 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 7457 7458#define S_FW_FCOE_FCF_CMD_PRIORITY 0 7459#define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 7460#define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 7461#define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 7462 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 7463 7464#define S_FW_FCOE_FCF_CMD_FPMA 6 7465#define M_FW_FCOE_FCF_CMD_FPMA 0x1 7466#define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 7467#define G_FW_FCOE_FCF_CMD_FPMA(x) \ 7468 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 7469#define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 7470 7471#define S_FW_FCOE_FCF_CMD_SPMA 5 7472#define M_FW_FCOE_FCF_CMD_SPMA 0x1 7473#define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 7474#define G_FW_FCOE_FCF_CMD_SPMA(x) \ 7475 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 7476#define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 7477 7478#define S_FW_FCOE_FCF_CMD_LOGIN 4 7479#define M_FW_FCOE_FCF_CMD_LOGIN 0x1 7480#define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 7481#define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 7482 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 7483#define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 7484 7485#define S_FW_FCOE_FCF_CMD_PORTID 0 7486#define M_FW_FCOE_FCF_CMD_PORTID 0xf 7487#define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 7488#define G_FW_FCOE_FCF_CMD_PORTID(x) \ 7489 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 7490 7491/****************************************************************************** 7492 * E R R O R a n d D E B U G C O M M A N D s 7493 ******************************************************/ 7494 7495enum fw_error_type { 7496 FW_ERROR_TYPE_EXCEPTION = 0x0, 7497 FW_ERROR_TYPE_HWMODULE = 0x1, 7498 FW_ERROR_TYPE_WR = 0x2, 7499 FW_ERROR_TYPE_ACL = 0x3, 7500}; 7501 7502struct fw_error_cmd { 7503 __be32 op_to_type; 7504 __be32 len16_pkd; 7505 union fw_error { 7506 struct fw_error_exception { 7507 __be32 info[6]; 7508 } exception; 7509 struct fw_error_hwmodule { 7510 __be32 regaddr; 7511 __be32 regval; 7512 } hwmodule; 7513 struct fw_error_wr { 7514 __be16 cidx; 7515 __be16 pfn_vfn; 7516 __be32 eqid; 7517 __u8 wrhdr[16]; 7518 } wr; 7519 struct fw_error_acl { 7520 __be16 cidx; 7521 __be16 pfn_vfn; 7522 __be32 eqid; 7523 __be16 mv_pkd; 7524 __u8 val[6]; 7525 __be64 r4; 7526 } acl; 7527 } u; 7528}; 7529 7530#define S_FW_ERROR_CMD_FATAL 4 7531#define M_FW_ERROR_CMD_FATAL 0x1 7532#define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 7533#define G_FW_ERROR_CMD_FATAL(x) \ 7534 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 7535#define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 7536 7537#define S_FW_ERROR_CMD_TYPE 0 7538#define M_FW_ERROR_CMD_TYPE 0xf 7539#define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 7540#define G_FW_ERROR_CMD_TYPE(x) \ 7541 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 7542 7543#define S_FW_ERROR_CMD_PFN 8 7544#define M_FW_ERROR_CMD_PFN 0x7 7545#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7546#define G_FW_ERROR_CMD_PFN(x) \ 7547 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7548 7549#define S_FW_ERROR_CMD_VFN 0 7550#define M_FW_ERROR_CMD_VFN 0xff 7551#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7552#define G_FW_ERROR_CMD_VFN(x) \ 7553 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7554 7555#define S_FW_ERROR_CMD_PFN 8 7556#define M_FW_ERROR_CMD_PFN 0x7 7557#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7558#define G_FW_ERROR_CMD_PFN(x) \ 7559 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7560 7561#define S_FW_ERROR_CMD_VFN 0 7562#define M_FW_ERROR_CMD_VFN 0xff 7563#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7564#define G_FW_ERROR_CMD_VFN(x) \ 7565 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7566 7567#define S_FW_ERROR_CMD_MV 15 7568#define M_FW_ERROR_CMD_MV 0x1 7569#define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 7570#define G_FW_ERROR_CMD_MV(x) \ 7571 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 7572#define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 7573 7574struct fw_debug_cmd { 7575 __be32 op_type; 7576 __be32 len16_pkd; 7577 union fw_debug { 7578 struct fw_debug_assert { 7579 __be32 fcid; 7580 __be32 line; 7581 __be32 x; 7582 __be32 y; 7583 __u8 filename_0_7[8]; 7584 __u8 filename_8_15[8]; 7585 __be64 r3; 7586 } assert; 7587 struct fw_debug_prt { 7588 __be16 dprtstridx; 7589 __be16 r3[3]; 7590 __be32 dprtstrparam0; 7591 __be32 dprtstrparam1; 7592 __be32 dprtstrparam2; 7593 __be32 dprtstrparam3; 7594 } prt; 7595 } u; 7596}; 7597 7598#define S_FW_DEBUG_CMD_TYPE 0 7599#define M_FW_DEBUG_CMD_TYPE 0xff 7600#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7601#define G_FW_DEBUG_CMD_TYPE(x) \ 7602 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7603 7604/****************************************************************************** 7605 * P C I E F W R E G I S T E R 7606 **************************************/ 7607 7608enum pcie_fw_eval { 7609 PCIE_FW_EVAL_CRASH = 0, 7610 PCIE_FW_EVAL_PREP = 1, 7611 PCIE_FW_EVAL_CONF = 2, 7612 PCIE_FW_EVAL_INIT = 3, 7613 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 7614 PCIE_FW_EVAL_OVERHEAT = 5, 7615 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 7616}; 7617 7618/** 7619 * Register definitions for the PCIE_FW register which the firmware uses 7620 * to retain status across RESETs. This register should be considered 7621 * as a READ-ONLY register for Host Software and only to be used to 7622 * track firmware initialization/error state, etc. 7623 */ 7624#define S_PCIE_FW_ERR 31 7625#define M_PCIE_FW_ERR 0x1 7626#define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 7627#define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 7628#define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 7629 7630#define S_PCIE_FW_INIT 30 7631#define M_PCIE_FW_INIT 0x1 7632#define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 7633#define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 7634#define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 7635 7636#define S_PCIE_FW_HALT 29 7637#define M_PCIE_FW_HALT 0x1 7638#define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 7639#define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 7640#define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 7641 7642#define S_PCIE_FW_EVAL 24 7643#define M_PCIE_FW_EVAL 0x7 7644#define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 7645#define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 7646 7647#define S_PCIE_FW_STAGE 21 7648#define M_PCIE_FW_STAGE 0x7 7649#define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 7650#define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 7651 7652#define S_PCIE_FW_ASYNCNOT_VLD 20 7653#define M_PCIE_FW_ASYNCNOT_VLD 0x1 7654#define V_PCIE_FW_ASYNCNOT_VLD(x) \ 7655 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 7656#define G_PCIE_FW_ASYNCNOT_VLD(x) \ 7657 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 7658#define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 7659 7660#define S_PCIE_FW_ASYNCNOTINT 19 7661#define M_PCIE_FW_ASYNCNOTINT 0x1 7662#define V_PCIE_FW_ASYNCNOTINT(x) \ 7663 ((x) << S_PCIE_FW_ASYNCNOTINT) 7664#define G_PCIE_FW_ASYNCNOTINT(x) \ 7665 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 7666#define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 7667 7668#define S_PCIE_FW_ASYNCNOT 16 7669#define M_PCIE_FW_ASYNCNOT 0x7 7670#define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 7671#define G_PCIE_FW_ASYNCNOT(x) \ 7672 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 7673 7674#define S_PCIE_FW_MASTER_VLD 15 7675#define M_PCIE_FW_MASTER_VLD 0x1 7676#define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 7677#define G_PCIE_FW_MASTER_VLD(x) \ 7678 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 7679#define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 7680 7681#define S_PCIE_FW_MASTER 12 7682#define M_PCIE_FW_MASTER 0x7 7683#define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 7684#define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 7685 7686#define S_PCIE_FW_RESET_VLD 11 7687#define M_PCIE_FW_RESET_VLD 0x1 7688#define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 7689#define G_PCIE_FW_RESET_VLD(x) \ 7690 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 7691#define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 7692 7693#define S_PCIE_FW_RESET 8 7694#define M_PCIE_FW_RESET 0x7 7695#define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 7696#define G_PCIE_FW_RESET(x) \ 7697 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 7698 7699#define S_PCIE_FW_REGISTERED 0 7700#define M_PCIE_FW_REGISTERED 0xff 7701#define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 7702#define G_PCIE_FW_REGISTERED(x) \ 7703 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 7704 7705 7706/****************************************************************************** 7707 * P C I E F W P F 0 R E G I S T E R 7708 **********************************************/ 7709 7710/* 7711 * this register is available as 32-bit of persistent storage (accross 7712 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 7713 * will not write it) 7714 */ 7715 7716 7717/****************************************************************************** 7718 * B I N A R Y H E A D E R F O R M A T 7719 **********************************************/ 7720 7721/* 7722 * firmware binary header format 7723 */ 7724struct fw_hdr { 7725 __u8 ver; 7726 __u8 chip; /* terminator chip family */ 7727 __be16 len512; /* bin length in units of 512-bytes */ 7728 __be32 fw_ver; /* firmware version */ 7729 __be32 tp_microcode_ver; /* tcp processor microcode version */ 7730 __u8 intfver_nic; 7731 __u8 intfver_vnic; 7732 __u8 intfver_ofld; 7733 __u8 intfver_ri; 7734 __u8 intfver_iscsipdu; 7735 __u8 intfver_iscsi; 7736 __u8 intfver_fcoepdu; 7737 __u8 intfver_fcoe; 7738 __u32 reserved2; 7739 __u32 reserved3; 7740 __u32 magic; /* runtime or bootstrap fw */ 7741 __be32 flags; 7742 __be32 reserved6[23]; 7743}; 7744 7745enum fw_hdr_chip { 7746 FW_HDR_CHIP_T4, 7747 FW_HDR_CHIP_T5 7748}; 7749 7750#define S_FW_HDR_FW_VER_MAJOR 24 7751#define M_FW_HDR_FW_VER_MAJOR 0xff 7752#define V_FW_HDR_FW_VER_MAJOR(x) \ 7753 ((x) << S_FW_HDR_FW_VER_MAJOR) 7754#define G_FW_HDR_FW_VER_MAJOR(x) \ 7755 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 7756 7757#define S_FW_HDR_FW_VER_MINOR 16 7758#define M_FW_HDR_FW_VER_MINOR 0xff 7759#define V_FW_HDR_FW_VER_MINOR(x) \ 7760 ((x) << S_FW_HDR_FW_VER_MINOR) 7761#define G_FW_HDR_FW_VER_MINOR(x) \ 7762 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 7763 7764#define S_FW_HDR_FW_VER_MICRO 8 7765#define M_FW_HDR_FW_VER_MICRO 0xff 7766#define V_FW_HDR_FW_VER_MICRO(x) \ 7767 ((x) << S_FW_HDR_FW_VER_MICRO) 7768#define G_FW_HDR_FW_VER_MICRO(x) \ 7769 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 7770 7771#define S_FW_HDR_FW_VER_BUILD 0 7772#define M_FW_HDR_FW_VER_BUILD 0xff 7773#define V_FW_HDR_FW_VER_BUILD(x) \ 7774 ((x) << S_FW_HDR_FW_VER_BUILD) 7775#define G_FW_HDR_FW_VER_BUILD(x) \ 7776 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 7777 7778enum { 7779 /* T4 7780 */ 7781 FW_HDR_INTFVER_NIC = 0x00, 7782 FW_HDR_INTFVER_VNIC = 0x00, 7783 FW_HDR_INTFVER_OFLD = 0x00, 7784 FW_HDR_INTFVER_RI = 0x00, 7785 FW_HDR_INTFVER_ISCSIPDU = 0x00, 7786 FW_HDR_INTFVER_ISCSI = 0x00, 7787 FW_HDR_INTFVER_FCOEPDU = 0x00, 7788 FW_HDR_INTFVER_FCOE = 0x00, 7789 7790 /* T5 7791 */ 7792 T5FW_HDR_INTFVER_NIC = 0x00, 7793 T5FW_HDR_INTFVER_VNIC = 0x00, 7794 T5FW_HDR_INTFVER_OFLD = 0x00, 7795 T5FW_HDR_INTFVER_RI = 0x00, 7796 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 7797 T5FW_HDR_INTFVER_ISCSI = 0x00, 7798 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 7799 T5FW_HDR_INTFVER_FCOE = 0x00, 7800}; 7801 7802enum { 7803 FW_HDR_MAGIC_RUNTIME = 0x00000000, 7804 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 7805}; 7806 7807enum fw_hdr_flags { 7808 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 7809}; 7810 7811#endif /* _T4FW_INTERFACE_H_ */ 7812