1//===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief This pass lowers the pseudo control flow instructions to real
12/// machine instructions.
13///
14/// All control flow is handled using predicated instructions and
15/// a predicate stack.  Each Scalar ALU controls the operations of 64 Vector
16/// ALUs.  The Scalar ALU can update the predicate for any of the Vector ALUs
17/// by writting to the 64-bit EXEC register (each bit corresponds to a
18/// single vector ALU).  Typically, for predicates, a vector ALU will write
19/// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20/// Vector ALU) and then the ScalarALU will AND the VCC register with the
21/// EXEC to update the predicates.
22///
23/// For example:
24/// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25/// %SGPR0 = SI_IF %VCC
26///   %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
27/// %SGPR0 = SI_ELSE %SGPR0
28///   %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
29/// SI_END_CF %SGPR0
30///
31/// becomes:
32///
33/// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC  // Save and update the exec mask
34/// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC  // Clear live bits from saved exec mask
35/// S_CBRANCH_EXECZ label0            // This instruction is an optional
36///                                   // optimization which allows us to
37///                                   // branch if all the bits of
38///                                   // EXEC are zero.
39/// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
40///
41/// label0:
42/// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC   // Restore the exec mask for the Then block
43/// %EXEC = S_XOR_B64 %SGPR0, %EXEC    // Clear live bits from saved exec mask
44/// S_BRANCH_EXECZ label1              // Use our branch optimization
45///                                    // instruction again.
46/// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR   // Do the THEN block
47/// label1:
48/// %EXEC = S_OR_B64 %EXEC, %SGPR0     // Re-enable saved exec mask bits
49//===----------------------------------------------------------------------===//
50
51#include "AMDGPU.h"
52#include "SIInstrInfo.h"
53#include "SIMachineFunctionInfo.h"
54#include "llvm/CodeGen/MachineFunction.h"
55#include "llvm/CodeGen/MachineFunctionPass.h"
56#include "llvm/CodeGen/MachineInstrBuilder.h"
57#include "llvm/CodeGen/MachineRegisterInfo.h"
58
59using namespace llvm;
60
61namespace {
62
63class SILowerControlFlowPass : public MachineFunctionPass {
64
65private:
66  static const unsigned SkipThreshold = 12;
67
68  static char ID;
69  const TargetRegisterInfo *TRI;
70  const TargetInstrInfo *TII;
71
72  bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
73
74  void Skip(MachineInstr &From, MachineOperand &To);
75  void SkipIfDead(MachineInstr &MI);
76
77  void If(MachineInstr &MI);
78  void Else(MachineInstr &MI);
79  void Break(MachineInstr &MI);
80  void IfBreak(MachineInstr &MI);
81  void ElseBreak(MachineInstr &MI);
82  void Loop(MachineInstr &MI);
83  void EndCf(MachineInstr &MI);
84
85  void Kill(MachineInstr &MI);
86  void Branch(MachineInstr &MI);
87
88  void LoadM0(MachineInstr &MI, MachineInstr *MovRel);
89  void IndirectSrc(MachineInstr &MI);
90  void IndirectDst(MachineInstr &MI);
91
92public:
93  SILowerControlFlowPass(TargetMachine &tm) :
94    MachineFunctionPass(ID), TRI(0), TII(0) { }
95
96  virtual bool runOnMachineFunction(MachineFunction &MF);
97
98  const char *getPassName() const {
99    return "SI Lower control flow instructions";
100  }
101
102};
103
104} // End anonymous namespace
105
106char SILowerControlFlowPass::ID = 0;
107
108FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
109  return new SILowerControlFlowPass(tm);
110}
111
112static bool isDS(unsigned Opcode) {
113  switch(Opcode) {
114  default: return false;
115  case AMDGPU::DS_ADD_U32_RTN:
116  case AMDGPU::DS_SUB_U32_RTN:
117  case AMDGPU::DS_WRITE_B32:
118  case AMDGPU::DS_WRITE_B8:
119  case AMDGPU::DS_WRITE_B16:
120  case AMDGPU::DS_READ_B32:
121  case AMDGPU::DS_READ_I8:
122  case AMDGPU::DS_READ_U8:
123  case AMDGPU::DS_READ_I16:
124  case AMDGPU::DS_READ_U16:
125    return true;
126  }
127}
128
129bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
130                                        MachineBasicBlock *To) {
131
132  unsigned NumInstr = 0;
133
134  for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
135       MBB = *MBB->succ_begin()) {
136
137    for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
138         NumInstr < SkipThreshold && I != E; ++I) {
139
140      if (I->isBundle() || !I->isBundled())
141        if (++NumInstr >= SkipThreshold)
142          return true;
143    }
144  }
145
146  return false;
147}
148
149void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
150
151  if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
152    return;
153
154  DebugLoc DL = From.getDebugLoc();
155  BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
156          .addOperand(To)
157          .addReg(AMDGPU::EXEC);
158}
159
160void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
161
162  MachineBasicBlock &MBB = *MI.getParent();
163  DebugLoc DL = MI.getDebugLoc();
164
165  if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType !=
166      ShaderType::PIXEL ||
167      !shouldSkip(&MBB, &MBB.getParent()->back()))
168    return;
169
170  MachineBasicBlock::iterator Insert = &MI;
171  ++Insert;
172
173  // If the exec mask is non-zero, skip the next two instructions
174  BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
175          .addImm(3)
176          .addReg(AMDGPU::EXEC);
177
178  // Exec mask is zero: Export to NULL target...
179  BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
180          .addImm(0)
181          .addImm(0x09) // V_008DFC_SQ_EXP_NULL
182          .addImm(0)
183          .addImm(1)
184          .addImm(1)
185          .addReg(AMDGPU::VGPR0)
186          .addReg(AMDGPU::VGPR0)
187          .addReg(AMDGPU::VGPR0)
188          .addReg(AMDGPU::VGPR0);
189
190  // ... and terminate wavefront
191  BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
192}
193
194void SILowerControlFlowPass::If(MachineInstr &MI) {
195  MachineBasicBlock &MBB = *MI.getParent();
196  DebugLoc DL = MI.getDebugLoc();
197  unsigned Reg = MI.getOperand(0).getReg();
198  unsigned Vcc = MI.getOperand(1).getReg();
199
200  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
201          .addReg(Vcc);
202
203  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
204          .addReg(AMDGPU::EXEC)
205          .addReg(Reg);
206
207  Skip(MI, MI.getOperand(2));
208
209  MI.eraseFromParent();
210}
211
212void SILowerControlFlowPass::Else(MachineInstr &MI) {
213  MachineBasicBlock &MBB = *MI.getParent();
214  DebugLoc DL = MI.getDebugLoc();
215  unsigned Dst = MI.getOperand(0).getReg();
216  unsigned Src = MI.getOperand(1).getReg();
217
218  BuildMI(MBB, MBB.getFirstNonPHI(), DL,
219          TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
220          .addReg(Src); // Saved EXEC
221
222  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
223          .addReg(AMDGPU::EXEC)
224          .addReg(Dst);
225
226  Skip(MI, MI.getOperand(2));
227
228  MI.eraseFromParent();
229}
230
231void SILowerControlFlowPass::Break(MachineInstr &MI) {
232  MachineBasicBlock &MBB = *MI.getParent();
233  DebugLoc DL = MI.getDebugLoc();
234
235  unsigned Dst = MI.getOperand(0).getReg();
236  unsigned Src = MI.getOperand(1).getReg();
237
238  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
239          .addReg(AMDGPU::EXEC)
240          .addReg(Src);
241
242  MI.eraseFromParent();
243}
244
245void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
246  MachineBasicBlock &MBB = *MI.getParent();
247  DebugLoc DL = MI.getDebugLoc();
248
249  unsigned Dst = MI.getOperand(0).getReg();
250  unsigned Vcc = MI.getOperand(1).getReg();
251  unsigned Src = MI.getOperand(2).getReg();
252
253  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
254          .addReg(Vcc)
255          .addReg(Src);
256
257  MI.eraseFromParent();
258}
259
260void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
261  MachineBasicBlock &MBB = *MI.getParent();
262  DebugLoc DL = MI.getDebugLoc();
263
264  unsigned Dst = MI.getOperand(0).getReg();
265  unsigned Saved = MI.getOperand(1).getReg();
266  unsigned Src = MI.getOperand(2).getReg();
267
268  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
269          .addReg(Saved)
270          .addReg(Src);
271
272  MI.eraseFromParent();
273}
274
275void SILowerControlFlowPass::Loop(MachineInstr &MI) {
276  MachineBasicBlock &MBB = *MI.getParent();
277  DebugLoc DL = MI.getDebugLoc();
278  unsigned Src = MI.getOperand(0).getReg();
279
280  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
281          .addReg(AMDGPU::EXEC)
282          .addReg(Src);
283
284  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
285          .addOperand(MI.getOperand(1))
286          .addReg(AMDGPU::EXEC);
287
288  MI.eraseFromParent();
289}
290
291void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
292  MachineBasicBlock &MBB = *MI.getParent();
293  DebugLoc DL = MI.getDebugLoc();
294  unsigned Reg = MI.getOperand(0).getReg();
295
296  BuildMI(MBB, MBB.getFirstNonPHI(), DL,
297          TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
298          .addReg(AMDGPU::EXEC)
299          .addReg(Reg);
300
301  MI.eraseFromParent();
302}
303
304void SILowerControlFlowPass::Branch(MachineInstr &MI) {
305  MachineBasicBlock *Next = MI.getParent()->getNextNode();
306  MachineBasicBlock *Target = MI.getOperand(0).getMBB();
307  if (Target == Next)
308    MI.eraseFromParent();
309  else
310    assert(0);
311}
312
313void SILowerControlFlowPass::Kill(MachineInstr &MI) {
314
315  MachineBasicBlock &MBB = *MI.getParent();
316  DebugLoc DL = MI.getDebugLoc();
317
318  // Kill is only allowed in pixel / geometry shaders
319  assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
320         ShaderType::PIXEL ||
321         MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
322         ShaderType::GEOMETRY);
323
324  // Clear this pixel from the exec mask if the operand is negative
325  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
326          .addImm(0)
327          .addOperand(MI.getOperand(0));
328
329  MI.eraseFromParent();
330}
331
332void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) {
333
334  MachineBasicBlock &MBB = *MI.getParent();
335  DebugLoc DL = MI.getDebugLoc();
336  MachineBasicBlock::iterator I = MI;
337
338  unsigned Save = MI.getOperand(1).getReg();
339  unsigned Idx = MI.getOperand(3).getReg();
340
341  if (AMDGPU::SReg_32RegClass.contains(Idx)) {
342    BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
343            .addReg(Idx);
344    MBB.insert(I, MovRel);
345    MI.eraseFromParent();
346    return;
347  }
348
349  assert(AMDGPU::SReg_64RegClass.contains(Save));
350  assert(AMDGPU::VReg_32RegClass.contains(Idx));
351
352  // Save the EXEC mask
353  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
354          .addReg(AMDGPU::EXEC);
355
356  // Read the next variant into VCC (lower 32 bits) <- also loop target
357  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC)
358          .addReg(Idx);
359
360  // Move index from VCC into M0
361  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
362          .addReg(AMDGPU::VCC);
363
364  // Compare the just read M0 value to all possible Idx values
365  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
366          .addReg(AMDGPU::M0)
367          .addReg(Idx);
368
369  // Update EXEC, save the original EXEC value to VCC
370  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
371          .addReg(AMDGPU::VCC);
372
373  // Do the actual move
374  MBB.insert(I, MovRel);
375
376  // Update EXEC, switch all done bits to 0 and all todo bits to 1
377  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
378          .addReg(AMDGPU::EXEC)
379          .addReg(AMDGPU::VCC);
380
381  // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover
382  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
383          .addImm(-7)
384          .addReg(AMDGPU::EXEC);
385
386  // Restore EXEC
387  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
388          .addReg(Save);
389
390  MI.eraseFromParent();
391}
392
393void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
394
395  MachineBasicBlock &MBB = *MI.getParent();
396  DebugLoc DL = MI.getDebugLoc();
397
398  unsigned Dst = MI.getOperand(0).getReg();
399  unsigned Vec = MI.getOperand(2).getReg();
400  unsigned Off = MI.getOperand(4).getImm();
401  unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0);
402  if (!SubReg)
403    SubReg = Vec;
404
405  MachineInstr *MovRel =
406    BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
407            .addReg(SubReg + Off)
408            .addReg(AMDGPU::M0, RegState::Implicit)
409            .addReg(Vec, RegState::Implicit);
410
411  LoadM0(MI, MovRel);
412}
413
414void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
415
416  MachineBasicBlock &MBB = *MI.getParent();
417  DebugLoc DL = MI.getDebugLoc();
418
419  unsigned Dst = MI.getOperand(0).getReg();
420  unsigned Off = MI.getOperand(4).getImm();
421  unsigned Val = MI.getOperand(5).getReg();
422  unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0);
423  if (!SubReg)
424    SubReg = Dst;
425
426  MachineInstr *MovRel =
427    BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
428            .addReg(SubReg + Off, RegState::Define)
429            .addReg(Val)
430            .addReg(AMDGPU::M0, RegState::Implicit)
431            .addReg(Dst, RegState::Implicit);
432
433  LoadM0(MI, MovRel);
434}
435
436bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
437  TII = MF.getTarget().getInstrInfo();
438  TRI = MF.getTarget().getRegisterInfo();
439  SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
440
441  bool HaveKill = false;
442  bool NeedM0 = false;
443  bool NeedWQM = false;
444  unsigned Depth = 0;
445
446  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
447       BI != BE; ++BI) {
448
449    MachineBasicBlock &MBB = *BI;
450    for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
451         I != MBB.end(); I = Next) {
452
453      Next = llvm::next(I);
454      MachineInstr &MI = *I;
455      if (isDS(MI.getOpcode())) {
456        NeedM0 = true;
457        NeedWQM = true;
458      }
459
460      switch (MI.getOpcode()) {
461        default: break;
462        case AMDGPU::SI_IF:
463          ++Depth;
464          If(MI);
465          break;
466
467        case AMDGPU::SI_ELSE:
468          Else(MI);
469          break;
470
471        case AMDGPU::SI_BREAK:
472          Break(MI);
473          break;
474
475        case AMDGPU::SI_IF_BREAK:
476          IfBreak(MI);
477          break;
478
479        case AMDGPU::SI_ELSE_BREAK:
480          ElseBreak(MI);
481          break;
482
483        case AMDGPU::SI_LOOP:
484          ++Depth;
485          Loop(MI);
486          break;
487
488        case AMDGPU::SI_END_CF:
489          if (--Depth == 0 && HaveKill) {
490            SkipIfDead(MI);
491            HaveKill = false;
492          }
493          EndCf(MI);
494          break;
495
496        case AMDGPU::SI_KILL:
497          if (Depth == 0)
498            SkipIfDead(MI);
499          else
500            HaveKill = true;
501          Kill(MI);
502          break;
503
504        case AMDGPU::S_BRANCH:
505          Branch(MI);
506          break;
507
508        case AMDGPU::SI_INDIRECT_SRC:
509          IndirectSrc(MI);
510          break;
511
512        case AMDGPU::SI_INDIRECT_DST_V1:
513        case AMDGPU::SI_INDIRECT_DST_V2:
514        case AMDGPU::SI_INDIRECT_DST_V4:
515        case AMDGPU::SI_INDIRECT_DST_V8:
516        case AMDGPU::SI_INDIRECT_DST_V16:
517          IndirectDst(MI);
518          break;
519
520        case AMDGPU::V_INTERP_P1_F32:
521        case AMDGPU::V_INTERP_P2_F32:
522        case AMDGPU::V_INTERP_MOV_F32:
523          NeedWQM = true;
524          break;
525
526      }
527    }
528  }
529
530  if (NeedM0) {
531    MachineBasicBlock &MBB = MF.front();
532    // Initialize M0 to a value that won't cause LDS access to be discarded
533    // due to offset clamping
534    BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32),
535            AMDGPU::M0).addImm(0xffffffff);
536  }
537
538  if (NeedWQM && MFI->ShaderType == ShaderType::PIXEL) {
539    MachineBasicBlock &MBB = MF.front();
540    BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
541            AMDGPU::EXEC).addReg(AMDGPU::EXEC);
542  }
543
544  return true;
545}
546