1/* Target-dependent code for GDB, the GNU debugger. 2 3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software 5 Foundation, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 59 Temple Place - Suite 330, 22 Boston, MA 02111-1307, USA. */ 23 24#include "defs.h" 25#include "frame.h" 26#include "inferior.h" 27#include "symtab.h" 28#include "target.h" 29#include "gdbcore.h" 30#include "gdbcmd.h" 31#include "objfiles.h" 32#include "arch-utils.h" 33#include "regcache.h" 34#include "doublest.h" 35#include "value.h" 36#include "parser-defs.h" 37#include "osabi.h" 38 39#include "libbfd.h" /* for bfd_default_set_arch_mach */ 40#include "coff/internal.h" /* for libcoff.h */ 41#include "libcoff.h" /* for xcoff_data */ 42#include "coff/xcoff.h" 43#include "libxcoff.h" 44 45#include "elf-bfd.h" 46 47#include "solib-svr4.h" 48#include "ppc-tdep.h" 49 50#include "gdb_assert.h" 51#include "dis-asm.h" 52 53/* If the kernel has to deliver a signal, it pushes a sigcontext 54 structure on the stack and then calls the signal handler, passing 55 the address of the sigcontext in an argument register. Usually 56 the signal handler doesn't save this register, so we have to 57 access the sigcontext structure via an offset from the signal handler 58 frame. 59 The following constants were determined by experimentation on AIX 3.2. */ 60#define SIG_FRAME_PC_OFFSET 96 61#define SIG_FRAME_LR_OFFSET 108 62#define SIG_FRAME_FP_OFFSET 284 63 64/* To be used by skip_prologue. */ 65 66struct rs6000_framedata 67 { 68 int offset; /* total size of frame --- the distance 69 by which we decrement sp to allocate 70 the frame */ 71 int saved_gpr; /* smallest # of saved gpr */ 72 int saved_fpr; /* smallest # of saved fpr */ 73 int saved_vr; /* smallest # of saved vr */ 74 int saved_ev; /* smallest # of saved ev */ 75 int alloca_reg; /* alloca register number (frame ptr) */ 76 char frameless; /* true if frameless functions. */ 77 char nosavedpc; /* true if pc not saved. */ 78 int gpr_offset; /* offset of saved gprs from prev sp */ 79 int fpr_offset; /* offset of saved fprs from prev sp */ 80 int vr_offset; /* offset of saved vrs from prev sp */ 81 int ev_offset; /* offset of saved evs from prev sp */ 82 int lr_offset; /* offset of saved lr */ 83 int cr_offset; /* offset of saved cr */ 84 int vrsave_offset; /* offset of saved vrsave register */ 85 }; 86 87/* Description of a single register. */ 88 89struct reg 90 { 91 char *name; /* name of register */ 92 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */ 93 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ 94 unsigned char fpr; /* whether register is floating-point */ 95 unsigned char pseudo; /* whether register is pseudo */ 96 }; 97 98/* Breakpoint shadows for the single step instructions will be kept here. */ 99 100static struct sstep_breaks 101 { 102 /* Address, or 0 if this is not in use. */ 103 CORE_ADDR address; 104 /* Shadow contents. */ 105 char data[4]; 106 } 107stepBreaks[2]; 108 109/* Hook for determining the TOC address when calling functions in the 110 inferior under AIX. The initialization code in rs6000-nat.c sets 111 this hook to point to find_toc_address. */ 112 113CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; 114 115/* Hook to set the current architecture when starting a child process. 116 rs6000-nat.c sets this. */ 117 118void (*rs6000_set_host_arch_hook) (int) = NULL; 119 120/* Static function prototypes */ 121 122static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, 123 CORE_ADDR safety); 124static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, 125 struct rs6000_framedata *); 126static void frame_get_saved_regs (struct frame_info * fi, 127 struct rs6000_framedata * fdatap); 128static CORE_ADDR frame_initial_stack_address (struct frame_info *); 129 130/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ 131int 132altivec_register_p (int regno) 133{ 134 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 135 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) 136 return 0; 137 else 138 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); 139} 140 141/* Use the architectures FP registers? */ 142int 143ppc_floating_point_unit_p (struct gdbarch *gdbarch) 144{ 145 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); 146 if (info->arch == bfd_arch_powerpc) 147 return (info->mach != bfd_mach_ppc_e500); 148 if (info->arch == bfd_arch_rs6000) 149 return 1; 150 return 0; 151} 152 153/* Read a LEN-byte address from debugged memory address MEMADDR. */ 154 155static CORE_ADDR 156read_memory_addr (CORE_ADDR memaddr, int len) 157{ 158 return read_memory_unsigned_integer (memaddr, len); 159} 160 161static CORE_ADDR 162rs6000_skip_prologue (CORE_ADDR pc) 163{ 164 struct rs6000_framedata frame; 165 pc = skip_prologue (pc, 0, &frame); 166 return pc; 167} 168 169 170/* Fill in fi->saved_regs */ 171 172struct frame_extra_info 173{ 174 /* Functions calling alloca() change the value of the stack 175 pointer. We need to use initial stack pointer (which is saved in 176 r31 by gcc) in such cases. If a compiler emits traceback table, 177 then we should use the alloca register specified in traceback 178 table. FIXME. */ 179 CORE_ADDR initial_sp; /* initial stack pointer. */ 180}; 181 182void 183rs6000_init_extra_frame_info (int fromleaf, struct frame_info *fi) 184{ 185 struct frame_extra_info *extra_info = 186 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); 187 extra_info->initial_sp = 0; 188 if (get_next_frame (fi) != NULL 189 && get_frame_pc (fi) < TEXT_SEGMENT_BASE) 190 /* We're in get_prev_frame */ 191 /* and this is a special signal frame. */ 192 /* (fi->pc will be some low address in the kernel, */ 193 /* to which the signal handler returns). */ 194 deprecated_set_frame_type (fi, SIGTRAMP_FRAME); 195} 196 197/* Put here the code to store, into a struct frame_saved_regs, 198 the addresses of the saved registers of frame described by FRAME_INFO. 199 This includes special registers such as pc and fp saved in special 200 ways in the stack frame. sp is even more special: 201 the address we return for it IS the sp for the next frame. */ 202 203/* In this implementation for RS/6000, we do *not* save sp. I am 204 not sure if it will be needed. The following function takes care of gpr's 205 and fpr's only. */ 206 207void 208rs6000_frame_init_saved_regs (struct frame_info *fi) 209{ 210 frame_get_saved_regs (fi, NULL); 211} 212 213static CORE_ADDR 214rs6000_frame_args_address (struct frame_info *fi) 215{ 216 struct frame_extra_info *extra_info = get_frame_extra_info (fi); 217 if (extra_info->initial_sp != 0) 218 return extra_info->initial_sp; 219 else 220 return frame_initial_stack_address (fi); 221} 222 223/* Immediately after a function call, return the saved pc. 224 Can't go through the frames for this because on some machines 225 the new frame is not set up until the new function executes 226 some instructions. */ 227 228static CORE_ADDR 229rs6000_saved_pc_after_call (struct frame_info *fi) 230{ 231 return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); 232} 233 234/* Get the ith function argument for the current function. */ 235static CORE_ADDR 236rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, 237 struct type *type) 238{ 239 CORE_ADDR addr; 240 get_frame_register (frame, 3 + argi, &addr); 241 return addr; 242} 243 244/* Calculate the destination of a branch/jump. Return -1 if not a branch. */ 245 246static CORE_ADDR 247branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) 248{ 249 CORE_ADDR dest; 250 int immediate; 251 int absolute; 252 int ext_op; 253 254 absolute = (int) ((instr >> 1) & 1); 255 256 switch (opcode) 257 { 258 case 18: 259 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ 260 if (absolute) 261 dest = immediate; 262 else 263 dest = pc + immediate; 264 break; 265 266 case 16: 267 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ 268 if (absolute) 269 dest = immediate; 270 else 271 dest = pc + immediate; 272 break; 273 274 case 19: 275 ext_op = (instr >> 1) & 0x3ff; 276 277 if (ext_op == 16) /* br conditional register */ 278 { 279 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; 280 281 /* If we are about to return from a signal handler, dest is 282 something like 0x3c90. The current frame is a signal handler 283 caller frame, upon completion of the sigreturn system call 284 execution will return to the saved PC in the frame. */ 285 if (dest < TEXT_SEGMENT_BASE) 286 { 287 struct frame_info *fi; 288 289 fi = get_current_frame (); 290 if (fi != NULL) 291 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, 292 gdbarch_tdep (current_gdbarch)->wordsize); 293 } 294 } 295 296 else if (ext_op == 528) /* br cond to count reg */ 297 { 298 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; 299 300 /* If we are about to execute a system call, dest is something 301 like 0x22fc or 0x3b00. Upon completion the system call 302 will return to the address in the link register. */ 303 if (dest < TEXT_SEGMENT_BASE) 304 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; 305 } 306 else 307 return -1; 308 break; 309 310 default: 311 return -1; 312 } 313 return (dest < TEXT_SEGMENT_BASE) ? safety : dest; 314} 315 316 317/* Sequence of bytes for breakpoint instruction. */ 318 319const static unsigned char * 320rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) 321{ 322 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; 323 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; 324 *bp_size = 4; 325 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 326 return big_breakpoint; 327 else 328 return little_breakpoint; 329} 330 331 332/* AIX does not support PT_STEP. Simulate it. */ 333 334void 335rs6000_software_single_step (enum target_signal signal, 336 int insert_breakpoints_p) 337{ 338 CORE_ADDR dummy; 339 int breakp_sz; 340 const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); 341 int ii, insn; 342 CORE_ADDR loc; 343 CORE_ADDR breaks[2]; 344 int opcode; 345 346 if (insert_breakpoints_p) 347 { 348 349 loc = read_pc (); 350 351 insn = read_memory_integer (loc, 4); 352 353 breaks[0] = loc + breakp_sz; 354 opcode = insn >> 26; 355 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); 356 357 /* Don't put two breakpoints on the same address. */ 358 if (breaks[1] == breaks[0]) 359 breaks[1] = -1; 360 361 stepBreaks[1].address = 0; 362 363 for (ii = 0; ii < 2; ++ii) 364 { 365 366 /* ignore invalid breakpoint. */ 367 if (breaks[ii] == -1) 368 continue; 369 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); 370 stepBreaks[ii].address = breaks[ii]; 371 } 372 373 } 374 else 375 { 376 377 /* remove step breakpoints. */ 378 for (ii = 0; ii < 2; ++ii) 379 if (stepBreaks[ii].address != 0) 380 target_remove_breakpoint (stepBreaks[ii].address, 381 stepBreaks[ii].data); 382 } 383 errno = 0; /* FIXME, don't ignore errors! */ 384 /* What errors? {read,write}_memory call error(). */ 385} 386 387 388/* return pc value after skipping a function prologue and also return 389 information about a function frame. 390 391 in struct rs6000_framedata fdata: 392 - frameless is TRUE, if function does not have a frame. 393 - nosavedpc is TRUE, if function does not save %pc value in its frame. 394 - offset is the initial size of this stack frame --- the amount by 395 which we decrement the sp to allocate the frame. 396 - saved_gpr is the number of the first saved gpr. 397 - saved_fpr is the number of the first saved fpr. 398 - saved_vr is the number of the first saved vr. 399 - saved_ev is the number of the first saved ev. 400 - alloca_reg is the number of the register used for alloca() handling. 401 Otherwise -1. 402 - gpr_offset is the offset of the first saved gpr from the previous frame. 403 - fpr_offset is the offset of the first saved fpr from the previous frame. 404 - vr_offset is the offset of the first saved vr from the previous frame. 405 - ev_offset is the offset of the first saved ev from the previous frame. 406 - lr_offset is the offset of the saved lr 407 - cr_offset is the offset of the saved cr 408 - vrsave_offset is the offset of the saved vrsave register 409 */ 410 411#define SIGNED_SHORT(x) \ 412 ((sizeof (short) == 2) \ 413 ? ((int)(short)(x)) \ 414 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) 415 416#define GET_SRC_REG(x) (((x) >> 21) & 0x1f) 417 418/* Limit the number of skipped non-prologue instructions, as the examining 419 of the prologue is expensive. */ 420static int max_skip_non_prologue_insns = 10; 421 422/* Given PC representing the starting address of a function, and 423 LIM_PC which is the (sloppy) limit to which to scan when looking 424 for a prologue, attempt to further refine this limit by using 425 the line data in the symbol table. If successful, a better guess 426 on where the prologue ends is returned, otherwise the previous 427 value of lim_pc is returned. */ 428 429/* FIXME: cagney/2004-02-14: This function and logic have largely been 430 superseded by skip_prologue_using_sal. */ 431 432static CORE_ADDR 433refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) 434{ 435 struct symtab_and_line prologue_sal; 436 437 prologue_sal = find_pc_line (pc, 0); 438 if (prologue_sal.line != 0) 439 { 440 int i; 441 CORE_ADDR addr = prologue_sal.end; 442 443 /* Handle the case in which compiler's optimizer/scheduler 444 has moved instructions into the prologue. We scan ahead 445 in the function looking for address ranges whose corresponding 446 line number is less than or equal to the first one that we 447 found for the function. (It can be less than when the 448 scheduler puts a body instruction before the first prologue 449 instruction.) */ 450 for (i = 2 * max_skip_non_prologue_insns; 451 i > 0 && (lim_pc == 0 || addr < lim_pc); 452 i--) 453 { 454 struct symtab_and_line sal; 455 456 sal = find_pc_line (addr, 0); 457 if (sal.line == 0) 458 break; 459 if (sal.line <= prologue_sal.line 460 && sal.symtab == prologue_sal.symtab) 461 { 462 prologue_sal = sal; 463 } 464 addr = sal.end; 465 } 466 467 if (lim_pc == 0 || prologue_sal.end < lim_pc) 468 lim_pc = prologue_sal.end; 469 } 470 return lim_pc; 471} 472 473 474static CORE_ADDR 475skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) 476{ 477 CORE_ADDR orig_pc = pc; 478 CORE_ADDR last_prologue_pc = pc; 479 CORE_ADDR li_found_pc = 0; 480 char buf[4]; 481 unsigned long op; 482 long offset = 0; 483 long vr_saved_offset = 0; 484 int lr_reg = -1; 485 int cr_reg = -1; 486 int vr_reg = -1; 487 int ev_reg = -1; 488 long ev_offset = 0; 489 int vrsave_reg = -1; 490 int reg; 491 int framep = 0; 492 int minimal_toc_loaded = 0; 493 int prev_insn_was_prologue_insn = 1; 494 int num_skip_non_prologue_insns = 0; 495 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); 496 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 497 498 /* Attempt to find the end of the prologue when no limit is specified. 499 Note that refine_prologue_limit() has been written so that it may 500 be used to "refine" the limits of non-zero PC values too, but this 501 is only safe if we 1) trust the line information provided by the 502 compiler and 2) iterate enough to actually find the end of the 503 prologue. 504 505 It may become a good idea at some point (for both performance and 506 accuracy) to unconditionally call refine_prologue_limit(). But, 507 until we can make a clear determination that this is beneficial, 508 we'll play it safe and only use it to obtain a limit when none 509 has been specified. */ 510 if (lim_pc == 0) 511 lim_pc = refine_prologue_limit (pc, lim_pc); 512 513 memset (fdata, 0, sizeof (struct rs6000_framedata)); 514 fdata->saved_gpr = -1; 515 fdata->saved_fpr = -1; 516 fdata->saved_vr = -1; 517 fdata->saved_ev = -1; 518 fdata->alloca_reg = -1; 519 fdata->frameless = 1; 520 fdata->nosavedpc = 1; 521 522 for (;; pc += 4) 523 { 524 /* Sometimes it isn't clear if an instruction is a prologue 525 instruction or not. When we encounter one of these ambiguous 526 cases, we'll set prev_insn_was_prologue_insn to 0 (false). 527 Otherwise, we'll assume that it really is a prologue instruction. */ 528 if (prev_insn_was_prologue_insn) 529 last_prologue_pc = pc; 530 531 /* Stop scanning if we've hit the limit. */ 532 if (lim_pc != 0 && pc >= lim_pc) 533 break; 534 535 prev_insn_was_prologue_insn = 1; 536 537 /* Fetch the instruction and convert it to an integer. */ 538 if (target_read_memory (pc, buf, 4)) 539 break; 540 op = extract_signed_integer (buf, 4); 541 542 if ((op & 0xfc1fffff) == 0x7c0802a6) 543 { /* mflr Rx */ 544 lr_reg = (op & 0x03e00000); 545 continue; 546 547 } 548 else if ((op & 0xfc1fffff) == 0x7c000026) 549 { /* mfcr Rx */ 550 cr_reg = (op & 0x03e00000); 551 continue; 552 553 } 554 else if ((op & 0xfc1f0000) == 0xd8010000) 555 { /* stfd Rx,NUM(r1) */ 556 reg = GET_SRC_REG (op); 557 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) 558 { 559 fdata->saved_fpr = reg; 560 fdata->fpr_offset = SIGNED_SHORT (op) + offset; 561 } 562 continue; 563 564 } 565 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ 566 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ 567 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ 568 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ 569 { 570 571 reg = GET_SRC_REG (op); 572 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) 573 { 574 fdata->saved_gpr = reg; 575 if ((op & 0xfc1f0003) == 0xf8010000) 576 op &= ~3UL; 577 fdata->gpr_offset = SIGNED_SHORT (op) + offset; 578 } 579 continue; 580 581 } 582 else if ((op & 0xffff0000) == 0x60000000) 583 { 584 /* nop */ 585 /* Allow nops in the prologue, but do not consider them to 586 be part of the prologue unless followed by other prologue 587 instructions. */ 588 prev_insn_was_prologue_insn = 0; 589 continue; 590 591 } 592 else if ((op & 0xffff0000) == 0x3c000000) 593 { /* addis 0,0,NUM, used 594 for >= 32k frames */ 595 fdata->offset = (op & 0x0000ffff) << 16; 596 fdata->frameless = 0; 597 continue; 598 599 } 600 else if ((op & 0xffff0000) == 0x60000000) 601 { /* ori 0,0,NUM, 2nd ha 602 lf of >= 32k frames */ 603 fdata->offset |= (op & 0x0000ffff); 604 fdata->frameless = 0; 605 continue; 606 607 } 608 else if (lr_reg != -1 && 609 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ 610 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || 611 /* stw Rx, NUM(r1) */ 612 ((op & 0xffff0000) == (lr_reg | 0x90010000)) || 613 /* stwu Rx, NUM(r1) */ 614 ((op & 0xffff0000) == (lr_reg | 0x94010000)))) 615 { /* where Rx == lr */ 616 fdata->lr_offset = offset; 617 fdata->nosavedpc = 0; 618 lr_reg = 0; 619 if ((op & 0xfc000003) == 0xf8000000 || /* std */ 620 (op & 0xfc000000) == 0x90000000) /* stw */ 621 { 622 /* Does not update r1, so add displacement to lr_offset. */ 623 fdata->lr_offset += SIGNED_SHORT (op); 624 } 625 continue; 626 627 } 628 else if (cr_reg != -1 && 629 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ 630 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || 631 /* stw Rx, NUM(r1) */ 632 ((op & 0xffff0000) == (cr_reg | 0x90010000)) || 633 /* stwu Rx, NUM(r1) */ 634 ((op & 0xffff0000) == (cr_reg | 0x94010000)))) 635 { /* where Rx == cr */ 636 fdata->cr_offset = offset; 637 cr_reg = 0; 638 if ((op & 0xfc000003) == 0xf8000000 || 639 (op & 0xfc000000) == 0x90000000) 640 { 641 /* Does not update r1, so add displacement to cr_offset. */ 642 fdata->cr_offset += SIGNED_SHORT (op); 643 } 644 continue; 645 646 } 647 else if (op == 0x48000005) 648 { /* bl .+4 used in 649 -mrelocatable */ 650 continue; 651 652 } 653 else if (op == 0x48000004) 654 { /* b .+4 (xlc) */ 655 break; 656 657 } 658 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used 659 in V.4 -mminimal-toc */ 660 (op & 0xffff0000) == 0x3bde0000) 661 { /* addi 30,30,foo@l */ 662 continue; 663 664 } 665 else if ((op & 0xfc000001) == 0x48000001) 666 { /* bl foo, 667 to save fprs??? */ 668 669 fdata->frameless = 0; 670 /* Don't skip over the subroutine call if it is not within 671 the first three instructions of the prologue. */ 672 if ((pc - orig_pc) > 8) 673 break; 674 675 op = read_memory_integer (pc + 4, 4); 676 677 /* At this point, make sure this is not a trampoline 678 function (a function that simply calls another functions, 679 and nothing else). If the next is not a nop, this branch 680 was part of the function prologue. */ 681 682 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ 683 break; /* don't skip over 684 this branch */ 685 continue; 686 687 } 688 /* update stack pointer */ 689 else if ((op & 0xfc1f0000) == 0x94010000) 690 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ 691 fdata->frameless = 0; 692 fdata->offset = SIGNED_SHORT (op); 693 offset = fdata->offset; 694 continue; 695 } 696 else if ((op & 0xfc1f016a) == 0x7c01016e) 697 { /* stwux rX,r1,rY */ 698 /* no way to figure out what r1 is going to be */ 699 fdata->frameless = 0; 700 offset = fdata->offset; 701 continue; 702 } 703 else if ((op & 0xfc1f0003) == 0xf8010001) 704 { /* stdu rX,NUM(r1) */ 705 fdata->frameless = 0; 706 fdata->offset = SIGNED_SHORT (op & ~3UL); 707 offset = fdata->offset; 708 continue; 709 } 710 else if ((op & 0xfc1f016a) == 0x7c01016a) 711 { /* stdux rX,r1,rY */ 712 /* no way to figure out what r1 is going to be */ 713 fdata->frameless = 0; 714 offset = fdata->offset; 715 continue; 716 } 717 /* Load up minimal toc pointer */ 718 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ 719 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ 720 && !minimal_toc_loaded) 721 { 722 minimal_toc_loaded = 1; 723 continue; 724 725 /* move parameters from argument registers to local variable 726 registers */ 727 } 728 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ 729 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ 730 (((op >> 21) & 31) <= 10) && 731 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ 732 { 733 continue; 734 735 /* store parameters in stack */ 736 } 737 else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */ 738 (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */ 739 (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ 740 { 741 continue; 742 743 /* store parameters in stack via frame pointer */ 744 } 745 else if (framep && 746 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r1) */ 747 (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r1) */ 748 (op & 0xfc1f0000) == 0xfc1f0000)) 749 { /* frsp, fp?,NUM(r1) */ 750 continue; 751 752 /* Set up frame pointer */ 753 } 754 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ 755 || op == 0x7c3f0b78) 756 { /* mr r31, r1 */ 757 fdata->frameless = 0; 758 framep = 1; 759 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); 760 continue; 761 762 /* Another way to set up the frame pointer. */ 763 } 764 else if ((op & 0xfc1fffff) == 0x38010000) 765 { /* addi rX, r1, 0x0 */ 766 fdata->frameless = 0; 767 framep = 1; 768 fdata->alloca_reg = (tdep->ppc_gp0_regnum 769 + ((op & ~0x38010000) >> 21)); 770 continue; 771 } 772 /* AltiVec related instructions. */ 773 /* Store the vrsave register (spr 256) in another register for 774 later manipulation, or load a register into the vrsave 775 register. 2 instructions are used: mfvrsave and 776 mtvrsave. They are shorthand notation for mfspr Rn, SPR256 777 and mtspr SPR256, Rn. */ 778 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 779 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ 780 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ 781 { 782 vrsave_reg = GET_SRC_REG (op); 783 continue; 784 } 785 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ 786 { 787 continue; 788 } 789 /* Store the register where vrsave was saved to onto the stack: 790 rS is the register where vrsave was stored in a previous 791 instruction. */ 792 /* 100100 sssss 00001 dddddddd dddddddd */ 793 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ 794 { 795 if (vrsave_reg == GET_SRC_REG (op)) 796 { 797 fdata->vrsave_offset = SIGNED_SHORT (op) + offset; 798 vrsave_reg = -1; 799 } 800 continue; 801 } 802 /* Compute the new value of vrsave, by modifying the register 803 where vrsave was saved to. */ 804 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ 805 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ 806 { 807 continue; 808 } 809 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first 810 in a pair of insns to save the vector registers on the 811 stack. */ 812 /* 001110 00000 00000 iiii iiii iiii iiii */ 813 /* 001110 01110 00000 iiii iiii iiii iiii */ 814 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ 815 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ 816 { 817 li_found_pc = pc; 818 vr_saved_offset = SIGNED_SHORT (op); 819 } 820 /* Store vector register S at (r31+r0) aligned to 16 bytes. */ 821 /* 011111 sssss 11111 00000 00111001110 */ 822 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ 823 { 824 if (pc == (li_found_pc + 4)) 825 { 826 vr_reg = GET_SRC_REG (op); 827 /* If this is the first vector reg to be saved, or if 828 it has a lower number than others previously seen, 829 reupdate the frame info. */ 830 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) 831 { 832 fdata->saved_vr = vr_reg; 833 fdata->vr_offset = vr_saved_offset + offset; 834 } 835 vr_saved_offset = -1; 836 vr_reg = -1; 837 li_found_pc = 0; 838 } 839 } 840 /* End AltiVec related instructions. */ 841 842 /* Start BookE related instructions. */ 843 /* Store gen register S at (r31+uimm). 844 Any register less than r13 is volatile, so we don't care. */ 845 /* 000100 sssss 11111 iiiii 01100100001 */ 846 else if (arch_info->mach == bfd_mach_ppc_e500 847 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ 848 { 849 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ 850 { 851 unsigned int imm; 852 ev_reg = GET_SRC_REG (op); 853 imm = (op >> 11) & 0x1f; 854 ev_offset = imm * 8; 855 /* If this is the first vector reg to be saved, or if 856 it has a lower number than others previously seen, 857 reupdate the frame info. */ 858 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 859 { 860 fdata->saved_ev = ev_reg; 861 fdata->ev_offset = ev_offset + offset; 862 } 863 } 864 continue; 865 } 866 /* Store gen register rS at (r1+rB). */ 867 /* 000100 sssss 00001 bbbbb 01100100000 */ 868 else if (arch_info->mach == bfd_mach_ppc_e500 869 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ 870 { 871 if (pc == (li_found_pc + 4)) 872 { 873 ev_reg = GET_SRC_REG (op); 874 /* If this is the first vector reg to be saved, or if 875 it has a lower number than others previously seen, 876 reupdate the frame info. */ 877 /* We know the contents of rB from the previous instruction. */ 878 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 879 { 880 fdata->saved_ev = ev_reg; 881 fdata->ev_offset = vr_saved_offset + offset; 882 } 883 vr_saved_offset = -1; 884 ev_reg = -1; 885 li_found_pc = 0; 886 } 887 continue; 888 } 889 /* Store gen register r31 at (rA+uimm). */ 890 /* 000100 11111 aaaaa iiiii 01100100001 */ 891 else if (arch_info->mach == bfd_mach_ppc_e500 892 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ 893 { 894 /* Wwe know that the source register is 31 already, but 895 it can't hurt to compute it. */ 896 ev_reg = GET_SRC_REG (op); 897 ev_offset = ((op >> 11) & 0x1f) * 8; 898 /* If this is the first vector reg to be saved, or if 899 it has a lower number than others previously seen, 900 reupdate the frame info. */ 901 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 902 { 903 fdata->saved_ev = ev_reg; 904 fdata->ev_offset = ev_offset + offset; 905 } 906 907 continue; 908 } 909 /* Store gen register S at (r31+r0). 910 Store param on stack when offset from SP bigger than 4 bytes. */ 911 /* 000100 sssss 11111 00000 01100100000 */ 912 else if (arch_info->mach == bfd_mach_ppc_e500 913 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ 914 { 915 if (pc == (li_found_pc + 4)) 916 { 917 if ((op & 0x03e00000) >= 0x01a00000) 918 { 919 ev_reg = GET_SRC_REG (op); 920 /* If this is the first vector reg to be saved, or if 921 it has a lower number than others previously seen, 922 reupdate the frame info. */ 923 /* We know the contents of r0 from the previous 924 instruction. */ 925 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 926 { 927 fdata->saved_ev = ev_reg; 928 fdata->ev_offset = vr_saved_offset + offset; 929 } 930 ev_reg = -1; 931 } 932 vr_saved_offset = -1; 933 li_found_pc = 0; 934 continue; 935 } 936 } 937 /* End BookE related instructions. */ 938 939 else 940 { 941 /* Not a recognized prologue instruction. 942 Handle optimizer code motions into the prologue by continuing 943 the search if we have no valid frame yet or if the return 944 address is not yet saved in the frame. */ 945 if (fdata->frameless == 0 946 && (lr_reg == -1 || fdata->nosavedpc == 0)) 947 break; 948 949 if (op == 0x4e800020 /* blr */ 950 || op == 0x4e800420) /* bctr */ 951 /* Do not scan past epilogue in frameless functions or 952 trampolines. */ 953 break; 954 if ((op & 0xf4000000) == 0x40000000) /* bxx */ 955 /* Never skip branches. */ 956 break; 957 958 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) 959 /* Do not scan too many insns, scanning insns is expensive with 960 remote targets. */ 961 break; 962 963 /* Continue scanning. */ 964 prev_insn_was_prologue_insn = 0; 965 continue; 966 } 967 } 968 969#if 0 970/* I have problems with skipping over __main() that I need to address 971 * sometime. Previously, I used to use misc_function_vector which 972 * didn't work as well as I wanted to be. -MGO */ 973 974 /* If the first thing after skipping a prolog is a branch to a function, 975 this might be a call to an initializer in main(), introduced by gcc2. 976 We'd like to skip over it as well. Fortunately, xlc does some extra 977 work before calling a function right after a prologue, thus we can 978 single out such gcc2 behaviour. */ 979 980 981 if ((op & 0xfc000001) == 0x48000001) 982 { /* bl foo, an initializer function? */ 983 op = read_memory_integer (pc + 4, 4); 984 985 if (op == 0x4def7b82) 986 { /* cror 0xf, 0xf, 0xf (nop) */ 987 988 /* Check and see if we are in main. If so, skip over this 989 initializer function as well. */ 990 991 tmp = find_pc_misc_function (pc); 992 if (tmp >= 0 993 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) 994 return pc + 8; 995 } 996 } 997#endif /* 0 */ 998 999 fdata->offset = -fdata->offset; 1000 return last_prologue_pc; 1001} 1002 1003 1004/************************************************************************* 1005 Support for creating pushing a dummy frame into the stack, and popping 1006 frames, etc. 1007*************************************************************************/ 1008 1009 1010/* Pop the innermost frame, go back to the caller. */ 1011 1012static void 1013rs6000_pop_frame (void) 1014{ 1015 CORE_ADDR pc, lr, sp, prev_sp, addr; /* %pc, %lr, %sp */ 1016 struct rs6000_framedata fdata; 1017 struct frame_info *frame = get_current_frame (); 1018 int ii, wordsize; 1019 1020 pc = read_pc (); 1021 sp = get_frame_base (frame); 1022 1023 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 1024 get_frame_base (frame), 1025 get_frame_base (frame))) 1026 { 1027 generic_pop_dummy_frame (); 1028 flush_cached_frames (); 1029 return; 1030 } 1031 1032 /* Make sure that all registers are valid. */ 1033 deprecated_read_register_bytes (0, NULL, DEPRECATED_REGISTER_BYTES); 1034 1035 /* Figure out previous %pc value. If the function is frameless, it is 1036 still in the link register, otherwise walk the frames and retrieve the 1037 saved %pc value in the previous frame. */ 1038 1039 addr = get_frame_func (frame); 1040 (void) skip_prologue (addr, get_frame_pc (frame), &fdata); 1041 1042 wordsize = gdbarch_tdep (current_gdbarch)->wordsize; 1043 if (fdata.frameless) 1044 prev_sp = sp; 1045 else 1046 prev_sp = read_memory_addr (sp, wordsize); 1047 if (fdata.lr_offset == 0) 1048 lr = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); 1049 else 1050 lr = read_memory_addr (prev_sp + fdata.lr_offset, wordsize); 1051 1052 /* reset %pc value. */ 1053 write_register (PC_REGNUM, lr); 1054 1055 /* reset register values if any was saved earlier. */ 1056 1057 if (fdata.saved_gpr != -1) 1058 { 1059 addr = prev_sp + fdata.gpr_offset; 1060 for (ii = fdata.saved_gpr; ii <= 31; ++ii) 1061 { 1062 read_memory (addr, &deprecated_registers[DEPRECATED_REGISTER_BYTE (ii)], 1063 wordsize); 1064 addr += wordsize; 1065 } 1066 } 1067 1068 if (fdata.saved_fpr != -1) 1069 { 1070 addr = prev_sp + fdata.fpr_offset; 1071 for (ii = fdata.saved_fpr; ii <= 31; ++ii) 1072 { 1073 read_memory (addr, &deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + FP0_REGNUM)], 8); 1074 addr += 8; 1075 } 1076 } 1077 1078 write_register (SP_REGNUM, prev_sp); 1079 target_store_registers (-1); 1080 flush_cached_frames (); 1081} 1082 1083/* All the ABI's require 16 byte alignment. */ 1084static CORE_ADDR 1085rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 1086{ 1087 return (addr & -16); 1088} 1089 1090/* Pass the arguments in either registers, or in the stack. In RS/6000, 1091 the first eight words of the argument list (that might be less than 1092 eight parameters if some parameters occupy more than one word) are 1093 passed in r3..r10 registers. float and double parameters are 1094 passed in fpr's, in addition to that. Rest of the parameters if any 1095 are passed in user stack. There might be cases in which half of the 1096 parameter is copied into registers, the other half is pushed into 1097 stack. 1098 1099 Stack must be aligned on 64-bit boundaries when synthesizing 1100 function calls. 1101 1102 If the function is returning a structure, then the return address is passed 1103 in r3, then the first 7 words of the parameters can be passed in registers, 1104 starting from r4. */ 1105 1106static CORE_ADDR 1107rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, 1108 struct regcache *regcache, CORE_ADDR bp_addr, 1109 int nargs, struct value **args, CORE_ADDR sp, 1110 int struct_return, CORE_ADDR struct_addr) 1111{ 1112 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1113 int ii; 1114 int len = 0; 1115 int argno; /* current argument number */ 1116 int argbytes; /* current argument byte */ 1117 char tmp_buffer[50]; 1118 int f_argno = 0; /* current floating point argno */ 1119 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; 1120 1121 struct value *arg = 0; 1122 struct type *type; 1123 1124 CORE_ADDR saved_sp; 1125 1126 /* The first eight words of ther arguments are passed in registers. 1127 Copy them appropriately. */ 1128 ii = 0; 1129 1130 /* If the function is returning a `struct', then the first word 1131 (which will be passed in r3) is used for struct return address. 1132 In that case we should advance one word and start from r4 1133 register to copy parameters. */ 1134 if (struct_return) 1135 { 1136 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, 1137 struct_addr); 1138 ii++; 1139 } 1140 1141/* 1142 effectively indirect call... gcc does... 1143 1144 return_val example( float, int); 1145 1146 eabi: 1147 float in fp0, int in r3 1148 offset of stack on overflow 8/16 1149 for varargs, must go by type. 1150 power open: 1151 float in r3&r4, int in r5 1152 offset of stack on overflow different 1153 both: 1154 return in r3 or f0. If no float, must study how gcc emulates floats; 1155 pay attention to arg promotion. 1156 User may have to cast\args to handle promotion correctly 1157 since gdb won't know if prototype supplied or not. 1158 */ 1159 1160 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) 1161 { 1162 int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3); 1163 1164 arg = args[argno]; 1165 type = check_typedef (VALUE_TYPE (arg)); 1166 len = TYPE_LENGTH (type); 1167 1168 if (TYPE_CODE (type) == TYPE_CODE_FLT) 1169 { 1170 1171 /* Floating point arguments are passed in fpr's, as well as gpr's. 1172 There are 13 fpr's reserved for passing parameters. At this point 1173 there is no way we would run out of them. */ 1174 1175 if (len > 8) 1176 printf_unfiltered ( 1177 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); 1178 1179 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], 1180 VALUE_CONTENTS (arg), 1181 len); 1182 ++f_argno; 1183 } 1184 1185 if (len > reg_size) 1186 { 1187 1188 /* Argument takes more than one register. */ 1189 while (argbytes < len) 1190 { 1191 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, 1192 reg_size); 1193 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 1194 ((char *) VALUE_CONTENTS (arg)) + argbytes, 1195 (len - argbytes) > reg_size 1196 ? reg_size : len - argbytes); 1197 ++ii, argbytes += reg_size; 1198 1199 if (ii >= 8) 1200 goto ran_out_of_registers_for_arguments; 1201 } 1202 argbytes = 0; 1203 --ii; 1204 } 1205 else 1206 { 1207 /* Argument can fit in one register. No problem. */ 1208 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; 1209 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size); 1210 memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj, 1211 VALUE_CONTENTS (arg), len); 1212 } 1213 ++argno; 1214 } 1215 1216ran_out_of_registers_for_arguments: 1217 1218 saved_sp = read_sp (); 1219 1220 /* Location for 8 parameters are always reserved. */ 1221 sp -= wordsize * 8; 1222 1223 /* Another six words for back chain, TOC register, link register, etc. */ 1224 sp -= wordsize * 6; 1225 1226 /* Stack pointer must be quadword aligned. */ 1227 sp &= -16; 1228 1229 /* If there are more arguments, allocate space for them in 1230 the stack, then push them starting from the ninth one. */ 1231 1232 if ((argno < nargs) || argbytes) 1233 { 1234 int space = 0, jj; 1235 1236 if (argbytes) 1237 { 1238 space += ((len - argbytes + 3) & -4); 1239 jj = argno + 1; 1240 } 1241 else 1242 jj = argno; 1243 1244 for (; jj < nargs; ++jj) 1245 { 1246 struct value *val = args[jj]; 1247 space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; 1248 } 1249 1250 /* Add location required for the rest of the parameters. */ 1251 space = (space + 15) & -16; 1252 sp -= space; 1253 1254 /* This is another instance we need to be concerned about 1255 securing our stack space. If we write anything underneath %sp 1256 (r1), we might conflict with the kernel who thinks he is free 1257 to use this area. So, update %sp first before doing anything 1258 else. */ 1259 1260 regcache_raw_write_signed (regcache, SP_REGNUM, sp); 1261 1262 /* If the last argument copied into the registers didn't fit there 1263 completely, push the rest of it into stack. */ 1264 1265 if (argbytes) 1266 { 1267 write_memory (sp + 24 + (ii * 4), 1268 ((char *) VALUE_CONTENTS (arg)) + argbytes, 1269 len - argbytes); 1270 ++argno; 1271 ii += ((len - argbytes + 3) & -4) / 4; 1272 } 1273 1274 /* Push the rest of the arguments into stack. */ 1275 for (; argno < nargs; ++argno) 1276 { 1277 1278 arg = args[argno]; 1279 type = check_typedef (VALUE_TYPE (arg)); 1280 len = TYPE_LENGTH (type); 1281 1282 1283 /* Float types should be passed in fpr's, as well as in the 1284 stack. */ 1285 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) 1286 { 1287 1288 if (len > 8) 1289 printf_unfiltered ( 1290 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); 1291 1292 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], 1293 VALUE_CONTENTS (arg), 1294 len); 1295 ++f_argno; 1296 } 1297 1298 write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len); 1299 ii += ((len + 3) & -4) / 4; 1300 } 1301 } 1302 1303 /* Set the stack pointer. According to the ABI, the SP is meant to 1304 be set _before_ the corresponding stack space is used. On AIX, 1305 this even applies when the target has been completely stopped! 1306 Not doing this can lead to conflicts with the kernel which thinks 1307 that it still has control over this not-yet-allocated stack 1308 region. */ 1309 regcache_raw_write_signed (regcache, SP_REGNUM, sp); 1310 1311 /* Set back chain properly. */ 1312 store_unsigned_integer (tmp_buffer, 4, saved_sp); 1313 write_memory (sp, tmp_buffer, 4); 1314 1315 /* Point the inferior function call's return address at the dummy's 1316 breakpoint. */ 1317 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); 1318 1319 /* Set the TOC register, get the value from the objfile reader 1320 which, in turn, gets it from the VMAP table. */ 1321 if (rs6000_find_toc_address_hook != NULL) 1322 { 1323 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); 1324 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); 1325 } 1326 1327 target_store_registers (-1); 1328 return sp; 1329} 1330 1331/* PowerOpen always puts structures in memory. Vectors, which were 1332 added later, do get returned in a register though. */ 1333 1334static int 1335rs6000_use_struct_convention (int gcc_p, struct type *value_type) 1336{ 1337 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8) 1338 && TYPE_VECTOR (value_type)) 1339 return 0; 1340 return 1; 1341} 1342 1343static void 1344rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) 1345{ 1346 int offset = 0; 1347 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1348 1349 if (TYPE_CODE (valtype) == TYPE_CODE_FLT) 1350 { 1351 1352 double dd; 1353 float ff; 1354 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. 1355 We need to truncate the return value into float size (4 byte) if 1356 necessary. */ 1357 1358 if (TYPE_LENGTH (valtype) > 4) /* this is a double */ 1359 memcpy (valbuf, 1360 ®buf[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1)], 1361 TYPE_LENGTH (valtype)); 1362 else 1363 { /* float */ 1364 memcpy (&dd, ®buf[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1)], 8); 1365 ff = (float) dd; 1366 memcpy (valbuf, &ff, sizeof (float)); 1367 } 1368 } 1369 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY 1370 && TYPE_LENGTH (valtype) == 16 1371 && TYPE_VECTOR (valtype)) 1372 { 1373 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), 1374 TYPE_LENGTH (valtype)); 1375 } 1376 else 1377 { 1378 /* return value is copied starting from r3. */ 1379 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 1380 && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3)) 1381 offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype); 1382 1383 memcpy (valbuf, 1384 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset, 1385 TYPE_LENGTH (valtype)); 1386 } 1387} 1388 1389/* Return whether handle_inferior_event() should proceed through code 1390 starting at PC in function NAME when stepping. 1391 1392 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to 1393 handle memory references that are too distant to fit in instructions 1394 generated by the compiler. For example, if 'foo' in the following 1395 instruction: 1396 1397 lwz r9,foo(r2) 1398 1399 is greater than 32767, the linker might replace the lwz with a branch to 1400 somewhere in @FIX1 that does the load in 2 instructions and then branches 1401 back to where execution should continue. 1402 1403 GDB should silently step over @FIX code, just like AIX dbx does. 1404 Unfortunately, the linker uses the "b" instruction for the branches, 1405 meaning that the link register doesn't get set. Therefore, GDB's usual 1406 step_over_function() mechanism won't work. 1407 1408 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks 1409 in handle_inferior_event() to skip past @FIX code. */ 1410 1411int 1412rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) 1413{ 1414 return name && !strncmp (name, "@FIX", 4); 1415} 1416 1417/* Skip code that the user doesn't want to see when stepping: 1418 1419 1. Indirect function calls use a piece of trampoline code to do context 1420 switching, i.e. to set the new TOC table. Skip such code if we are on 1421 its first instruction (as when we have single-stepped to here). 1422 1423 2. Skip shared library trampoline code (which is different from 1424 indirect function call trampolines). 1425 1426 3. Skip bigtoc fixup code. 1427 1428 Result is desired PC to step until, or NULL if we are not in 1429 code that should be skipped. */ 1430 1431CORE_ADDR 1432rs6000_skip_trampoline_code (CORE_ADDR pc) 1433{ 1434 unsigned int ii, op; 1435 int rel; 1436 CORE_ADDR solib_target_pc; 1437 struct minimal_symbol *msymbol; 1438 1439 static unsigned trampoline_code[] = 1440 { 1441 0x800b0000, /* l r0,0x0(r11) */ 1442 0x90410014, /* st r2,0x14(r1) */ 1443 0x7c0903a6, /* mtctr r0 */ 1444 0x804b0004, /* l r2,0x4(r11) */ 1445 0x816b0008, /* l r11,0x8(r11) */ 1446 0x4e800420, /* bctr */ 1447 0x4e800020, /* br */ 1448 0 1449 }; 1450 1451 /* Check for bigtoc fixup code. */ 1452 msymbol = lookup_minimal_symbol_by_pc (pc); 1453 if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol))) 1454 { 1455 /* Double-check that the third instruction from PC is relative "b". */ 1456 op = read_memory_integer (pc + 8, 4); 1457 if ((op & 0xfc000003) == 0x48000000) 1458 { 1459 /* Extract bits 6-29 as a signed 24-bit relative word address and 1460 add it to the containing PC. */ 1461 rel = ((int)(op << 6) >> 6); 1462 return pc + 8 + rel; 1463 } 1464 } 1465 1466 /* If pc is in a shared library trampoline, return its target. */ 1467 solib_target_pc = find_solib_trampoline_target (pc); 1468 if (solib_target_pc) 1469 return solib_target_pc; 1470 1471 for (ii = 0; trampoline_code[ii]; ++ii) 1472 { 1473 op = read_memory_integer (pc + (ii * 4), 4); 1474 if (op != trampoline_code[ii]) 1475 return 0; 1476 } 1477 ii = read_register (11); /* r11 holds destination addr */ 1478 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ 1479 return pc; 1480} 1481 1482/* Determines whether the function FI has a frame on the stack or not. */ 1483 1484int 1485rs6000_frameless_function_invocation (struct frame_info *fi) 1486{ 1487 CORE_ADDR func_start; 1488 struct rs6000_framedata fdata; 1489 1490 /* Don't even think about framelessness except on the innermost frame 1491 or if the function was interrupted by a signal. */ 1492 if (get_next_frame (fi) != NULL 1493 && !(get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME)) 1494 return 0; 1495 1496 func_start = get_frame_func (fi); 1497 1498 /* If we failed to find the start of the function, it is a mistake 1499 to inspect the instructions. */ 1500 1501 if (!func_start) 1502 { 1503 /* A frame with a zero PC is usually created by dereferencing a NULL 1504 function pointer, normally causing an immediate core dump of the 1505 inferior. Mark function as frameless, as the inferior has no chance 1506 of setting up a stack frame. */ 1507 if (get_frame_pc (fi) == 0) 1508 return 1; 1509 else 1510 return 0; 1511 } 1512 1513 (void) skip_prologue (func_start, get_frame_pc (fi), &fdata); 1514 return fdata.frameless; 1515} 1516 1517/* Return the PC saved in a frame. */ 1518 1519CORE_ADDR 1520rs6000_frame_saved_pc (struct frame_info *fi) 1521{ 1522 CORE_ADDR func_start; 1523 struct rs6000_framedata fdata; 1524 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1525 int wordsize = tdep->wordsize; 1526 1527 if ((get_frame_type (fi) == SIGTRAMP_FRAME)) 1528 return read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, 1529 wordsize); 1530 1531 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 1532 get_frame_base (fi), 1533 get_frame_base (fi))) 1534 return deprecated_read_register_dummy (get_frame_pc (fi), 1535 get_frame_base (fi), PC_REGNUM); 1536 1537 func_start = get_frame_func (fi); 1538 1539 /* If we failed to find the start of the function, it is a mistake 1540 to inspect the instructions. */ 1541 if (!func_start) 1542 return 0; 1543 1544 (void) skip_prologue (func_start, get_frame_pc (fi), &fdata); 1545 1546 if (fdata.lr_offset == 0 && get_next_frame (fi) != NULL) 1547 { 1548 if ((get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME)) 1549 return read_memory_addr ((get_frame_base (get_next_frame (fi)) 1550 + SIG_FRAME_LR_OFFSET), 1551 wordsize); 1552 else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) 1553 /* The link register wasn't saved by this frame and the next 1554 (inner, newer) frame is a dummy. Get the link register 1555 value by unwinding it from that [dummy] frame. */ 1556 { 1557 ULONGEST lr; 1558 frame_unwind_unsigned_register (get_next_frame (fi), 1559 tdep->ppc_lr_regnum, &lr); 1560 return lr; 1561 } 1562 else 1563 return read_memory_addr (DEPRECATED_FRAME_CHAIN (fi) 1564 + tdep->lr_frame_offset, 1565 wordsize); 1566 } 1567 1568 if (fdata.lr_offset == 0) 1569 return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); 1570 1571 return read_memory_addr (DEPRECATED_FRAME_CHAIN (fi) + fdata.lr_offset, 1572 wordsize); 1573} 1574 1575/* If saved registers of frame FI are not known yet, read and cache them. 1576 &FDATAP contains rs6000_framedata; TDATAP can be NULL, 1577 in which case the framedata are read. */ 1578 1579static void 1580frame_get_saved_regs (struct frame_info *fi, struct rs6000_framedata *fdatap) 1581{ 1582 CORE_ADDR frame_addr; 1583 struct rs6000_framedata work_fdata; 1584 struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch); 1585 int wordsize = tdep->wordsize; 1586 1587 if (deprecated_get_frame_saved_regs (fi)) 1588 return; 1589 1590 if (fdatap == NULL) 1591 { 1592 fdatap = &work_fdata; 1593 (void) skip_prologue (get_frame_func (fi), get_frame_pc (fi), fdatap); 1594 } 1595 1596 frame_saved_regs_zalloc (fi); 1597 1598 /* If there were any saved registers, figure out parent's stack 1599 pointer. */ 1600 /* The following is true only if the frame doesn't have a call to 1601 alloca(), FIXME. */ 1602 1603 if (fdatap->saved_fpr == 0 1604 && fdatap->saved_gpr == 0 1605 && fdatap->saved_vr == 0 1606 && fdatap->saved_ev == 0 1607 && fdatap->lr_offset == 0 1608 && fdatap->cr_offset == 0 1609 && fdatap->vr_offset == 0 1610 && fdatap->ev_offset == 0) 1611 frame_addr = 0; 1612 else 1613 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most 1614 address of the current frame. Things might be easier if the 1615 ->frame pointed to the outer-most address of the frame. In the 1616 mean time, the address of the prev frame is used as the base 1617 address of this frame. */ 1618 frame_addr = DEPRECATED_FRAME_CHAIN (fi); 1619 1620 /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr. 1621 All fpr's from saved_fpr to fp31 are saved. */ 1622 1623 if (fdatap->saved_fpr >= 0) 1624 { 1625 int i; 1626 CORE_ADDR fpr_addr = frame_addr + fdatap->fpr_offset; 1627 for (i = fdatap->saved_fpr; i < 32; i++) 1628 { 1629 deprecated_get_frame_saved_regs (fi)[FP0_REGNUM + i] = fpr_addr; 1630 fpr_addr += 8; 1631 } 1632 } 1633 1634 /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr. 1635 All gpr's from saved_gpr to gpr31 are saved. */ 1636 1637 if (fdatap->saved_gpr >= 0) 1638 { 1639 int i; 1640 CORE_ADDR gpr_addr = frame_addr + fdatap->gpr_offset; 1641 for (i = fdatap->saved_gpr; i < 32; i++) 1642 { 1643 deprecated_get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = gpr_addr; 1644 gpr_addr += wordsize; 1645 } 1646 } 1647 1648 /* if != -1, fdatap->saved_vr is the smallest number of saved_vr. 1649 All vr's from saved_vr to vr31 are saved. */ 1650 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) 1651 { 1652 if (fdatap->saved_vr >= 0) 1653 { 1654 int i; 1655 CORE_ADDR vr_addr = frame_addr + fdatap->vr_offset; 1656 for (i = fdatap->saved_vr; i < 32; i++) 1657 { 1658 deprecated_get_frame_saved_regs (fi)[tdep->ppc_vr0_regnum + i] = vr_addr; 1659 vr_addr += DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); 1660 } 1661 } 1662 } 1663 1664 /* if != -1, fdatap->saved_ev is the smallest number of saved_ev. 1665 All vr's from saved_ev to ev31 are saved. ????? */ 1666 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) 1667 { 1668 if (fdatap->saved_ev >= 0) 1669 { 1670 int i; 1671 CORE_ADDR ev_addr = frame_addr + fdatap->ev_offset; 1672 for (i = fdatap->saved_ev; i < 32; i++) 1673 { 1674 deprecated_get_frame_saved_regs (fi)[tdep->ppc_ev0_regnum + i] = ev_addr; 1675 deprecated_get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = ev_addr + 4; 1676 ev_addr += DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_ev0_regnum); 1677 } 1678 } 1679 } 1680 1681 /* If != 0, fdatap->cr_offset is the offset from the frame that holds 1682 the CR. */ 1683 if (fdatap->cr_offset != 0) 1684 deprecated_get_frame_saved_regs (fi)[tdep->ppc_cr_regnum] = frame_addr + fdatap->cr_offset; 1685 1686 /* If != 0, fdatap->lr_offset is the offset from the frame that holds 1687 the LR. */ 1688 if (fdatap->lr_offset != 0) 1689 deprecated_get_frame_saved_regs (fi)[tdep->ppc_lr_regnum] = frame_addr + fdatap->lr_offset; 1690 1691 /* If != 0, fdatap->vrsave_offset is the offset from the frame that holds 1692 the VRSAVE. */ 1693 if (fdatap->vrsave_offset != 0) 1694 deprecated_get_frame_saved_regs (fi)[tdep->ppc_vrsave_regnum] = frame_addr + fdatap->vrsave_offset; 1695} 1696 1697/* Return the address of a frame. This is the inital %sp value when the frame 1698 was first allocated. For functions calling alloca(), it might be saved in 1699 an alloca register. */ 1700 1701static CORE_ADDR 1702frame_initial_stack_address (struct frame_info *fi) 1703{ 1704 CORE_ADDR tmpaddr; 1705 struct rs6000_framedata fdata; 1706 struct frame_info *callee_fi; 1707 1708 /* If the initial stack pointer (frame address) of this frame is known, 1709 just return it. */ 1710 1711 if (get_frame_extra_info (fi)->initial_sp) 1712 return get_frame_extra_info (fi)->initial_sp; 1713 1714 /* Find out if this function is using an alloca register. */ 1715 1716 (void) skip_prologue (get_frame_func (fi), get_frame_pc (fi), &fdata); 1717 1718 /* If saved registers of this frame are not known yet, read and 1719 cache them. */ 1720 1721 if (!deprecated_get_frame_saved_regs (fi)) 1722 frame_get_saved_regs (fi, &fdata); 1723 1724 /* If no alloca register used, then fi->frame is the value of the %sp for 1725 this frame, and it is good enough. */ 1726 1727 if (fdata.alloca_reg < 0) 1728 { 1729 get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); 1730 return get_frame_extra_info (fi)->initial_sp; 1731 } 1732 1733 /* There is an alloca register, use its value, in the current frame, 1734 as the initial stack pointer. */ 1735 { 1736 char tmpbuf[MAX_REGISTER_SIZE]; 1737 if (frame_register_read (fi, fdata.alloca_reg, tmpbuf)) 1738 { 1739 get_frame_extra_info (fi)->initial_sp 1740 = extract_unsigned_integer (tmpbuf, 1741 DEPRECATED_REGISTER_RAW_SIZE (fdata.alloca_reg)); 1742 } 1743 else 1744 /* NOTE: cagney/2002-04-17: At present the only time 1745 frame_register_read will fail is when the register isn't 1746 available. If that does happen, use the frame. */ 1747 get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); 1748 } 1749 return get_frame_extra_info (fi)->initial_sp; 1750} 1751 1752/* Describe the pointer in each stack frame to the previous stack frame 1753 (its caller). */ 1754 1755/* DEPRECATED_FRAME_CHAIN takes a frame's nominal address and produces 1756 the frame's chain-pointer. */ 1757 1758/* In the case of the RS/6000, the frame's nominal address 1759 is the address of a 4-byte word containing the calling frame's address. */ 1760 1761CORE_ADDR 1762rs6000_frame_chain (struct frame_info *thisframe) 1763{ 1764 CORE_ADDR fp, fpp, lr; 1765 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; 1766 1767 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (thisframe), 1768 get_frame_base (thisframe), 1769 get_frame_base (thisframe))) 1770 /* A dummy frame always correctly chains back to the previous 1771 frame. */ 1772 return read_memory_addr (get_frame_base (thisframe), wordsize); 1773 1774 if (deprecated_inside_entry_file (get_frame_pc (thisframe)) 1775 || get_frame_pc (thisframe) == entry_point_address ()) 1776 return 0; 1777 1778 if ((get_frame_type (thisframe) == SIGTRAMP_FRAME)) 1779 fp = read_memory_addr (get_frame_base (thisframe) + SIG_FRAME_FP_OFFSET, 1780 wordsize); 1781 else if (get_next_frame (thisframe) != NULL 1782 && (get_frame_type (get_next_frame (thisframe)) == SIGTRAMP_FRAME) 1783 && (DEPRECATED_FRAMELESS_FUNCTION_INVOCATION_P () 1784 && DEPRECATED_FRAMELESS_FUNCTION_INVOCATION (thisframe))) 1785 /* A frameless function interrupted by a signal did not change the 1786 frame pointer. */ 1787 fp = get_frame_base (thisframe); 1788 else 1789 fp = read_memory_addr (get_frame_base (thisframe), wordsize); 1790 return fp; 1791} 1792 1793/* Return the size of register REG when words are WORDSIZE bytes long. If REG 1794 isn't available with that word size, return 0. */ 1795 1796static int 1797regsize (const struct reg *reg, int wordsize) 1798{ 1799 return wordsize == 8 ? reg->sz64 : reg->sz32; 1800} 1801 1802/* Return the name of register number N, or null if no such register exists 1803 in the current architecture. */ 1804 1805static const char * 1806rs6000_register_name (int n) 1807{ 1808 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1809 const struct reg *reg = tdep->regs + n; 1810 1811 if (!regsize (reg, tdep->wordsize)) 1812 return NULL; 1813 return reg->name; 1814} 1815 1816/* Index within `registers' of the first byte of the space for 1817 register N. */ 1818 1819static int 1820rs6000_register_byte (int n) 1821{ 1822 return gdbarch_tdep (current_gdbarch)->regoff[n]; 1823} 1824 1825/* Return the number of bytes of storage in the actual machine representation 1826 for register N if that register is available, else return 0. */ 1827 1828static int 1829rs6000_register_raw_size (int n) 1830{ 1831 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1832 const struct reg *reg = tdep->regs + n; 1833 return regsize (reg, tdep->wordsize); 1834} 1835 1836/* Return the GDB type object for the "standard" data type 1837 of data in register N. */ 1838 1839static struct type * 1840rs6000_register_virtual_type (int n) 1841{ 1842 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1843 const struct reg *reg = tdep->regs + n; 1844 1845 if (reg->fpr) 1846 return builtin_type_double; 1847 else 1848 { 1849 int size = regsize (reg, tdep->wordsize); 1850 switch (size) 1851 { 1852 case 0: 1853 return builtin_type_int0; 1854 case 4: 1855 return builtin_type_int32; 1856 case 8: 1857 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) 1858 return builtin_type_vec64; 1859 else 1860 return builtin_type_int64; 1861 break; 1862 case 16: 1863 return builtin_type_vec128; 1864 break; 1865 default: 1866 internal_error (__FILE__, __LINE__, "Register %d size %d unknown", 1867 n, size); 1868 } 1869 } 1870} 1871 1872/* Return whether register N requires conversion when moving from raw format 1873 to virtual format. 1874 1875 The register format for RS/6000 floating point registers is always 1876 double, we need a conversion if the memory format is float. */ 1877 1878static int 1879rs6000_register_convertible (int n) 1880{ 1881 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n; 1882 return reg->fpr; 1883} 1884 1885/* Convert data from raw format for register N in buffer FROM 1886 to virtual format with type TYPE in buffer TO. */ 1887 1888static void 1889rs6000_register_convert_to_virtual (int n, struct type *type, 1890 char *from, char *to) 1891{ 1892 if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) 1893 { 1894 double val = deprecated_extract_floating (from, DEPRECATED_REGISTER_RAW_SIZE (n)); 1895 deprecated_store_floating (to, TYPE_LENGTH (type), val); 1896 } 1897 else 1898 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); 1899} 1900 1901/* Convert data from virtual format with type TYPE in buffer FROM 1902 to raw format for register N in buffer TO. */ 1903 1904static void 1905rs6000_register_convert_to_raw (struct type *type, int n, 1906 const char *from, char *to) 1907{ 1908 if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) 1909 { 1910 double val = deprecated_extract_floating (from, TYPE_LENGTH (type)); 1911 deprecated_store_floating (to, DEPRECATED_REGISTER_RAW_SIZE (n), val); 1912 } 1913 else 1914 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); 1915} 1916 1917static void 1918e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 1919 int reg_nr, void *buffer) 1920{ 1921 int base_regnum; 1922 int offset = 0; 1923 char temp_buffer[MAX_REGISTER_SIZE]; 1924 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1925 1926 if (reg_nr >= tdep->ppc_gp0_regnum 1927 && reg_nr <= tdep->ppc_gplast_regnum) 1928 { 1929 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; 1930 1931 /* Build the value in the provided buffer. */ 1932 /* Read the raw register of which this one is the lower portion. */ 1933 regcache_raw_read (regcache, base_regnum, temp_buffer); 1934 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 1935 offset = 4; 1936 memcpy ((char *) buffer, temp_buffer + offset, 4); 1937 } 1938} 1939 1940static void 1941e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 1942 int reg_nr, const void *buffer) 1943{ 1944 int base_regnum; 1945 int offset = 0; 1946 char temp_buffer[MAX_REGISTER_SIZE]; 1947 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1948 1949 if (reg_nr >= tdep->ppc_gp0_regnum 1950 && reg_nr <= tdep->ppc_gplast_regnum) 1951 { 1952 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; 1953 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ 1954 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 1955 offset = 4; 1956 1957 /* Let's read the value of the base register into a temporary 1958 buffer, so that overwriting the last four bytes with the new 1959 value of the pseudo will leave the upper 4 bytes unchanged. */ 1960 regcache_raw_read (regcache, base_regnum, temp_buffer); 1961 1962 /* Write as an 8 byte quantity. */ 1963 memcpy (temp_buffer + offset, (char *) buffer, 4); 1964 regcache_raw_write (regcache, base_regnum, temp_buffer); 1965 } 1966} 1967 1968/* Convert a dwarf2 register number to a gdb REGNUM. */ 1969static int 1970e500_dwarf2_reg_to_regnum (int num) 1971{ 1972 int regnum; 1973 if (0 <= num && num <= 31) 1974 return num + gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum; 1975 else 1976 return num; 1977} 1978 1979/* Convert a dbx stab register number (from `r' declaration) to a gdb 1980 REGNUM. */ 1981static int 1982rs6000_stab_reg_to_regnum (int num) 1983{ 1984 int regnum; 1985 switch (num) 1986 { 1987 case 64: 1988 regnum = gdbarch_tdep (current_gdbarch)->ppc_mq_regnum; 1989 break; 1990 case 65: 1991 regnum = gdbarch_tdep (current_gdbarch)->ppc_lr_regnum; 1992 break; 1993 case 66: 1994 regnum = gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum; 1995 break; 1996 case 76: 1997 regnum = gdbarch_tdep (current_gdbarch)->ppc_xer_regnum; 1998 break; 1999 default: 2000 regnum = num; 2001 break; 2002 } 2003 return regnum; 2004} 2005 2006static void 2007rs6000_store_return_value (struct type *type, char *valbuf) 2008{ 2009 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2010 2011 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2012 2013 /* Floating point values are returned starting from FPR1 and up. 2014 Say a double_double_double type could be returned in 2015 FPR1/FPR2/FPR3 triple. */ 2016 2017 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1), valbuf, 2018 TYPE_LENGTH (type)); 2019 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 2020 { 2021 if (TYPE_LENGTH (type) == 16 2022 && TYPE_VECTOR (type)) 2023 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), 2024 valbuf, TYPE_LENGTH (type)); 2025 } 2026 else 2027 /* Everything else is returned in GPR3 and up. */ 2028 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3), 2029 valbuf, TYPE_LENGTH (type)); 2030} 2031 2032/* Extract from an array REGBUF containing the (raw) register state 2033 the address in which a function should return its structure value, 2034 as a CORE_ADDR (or an expression that can be used as one). */ 2035 2036static CORE_ADDR 2037rs6000_extract_struct_value_address (struct regcache *regcache) 2038{ 2039 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior 2040 function call GDB knows the address of the struct return value 2041 and hence, should not need to call this function. Unfortunately, 2042 the current call_function_by_hand() code only saves the most 2043 recent struct address leading to occasional calls. The code 2044 should instead maintain a stack of such addresses (in the dummy 2045 frame object). */ 2046 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've 2047 really got no idea where the return value is being stored. While 2048 r3, on function entry, contained the address it will have since 2049 been reused (scratch) and hence wouldn't be valid */ 2050 return 0; 2051} 2052 2053/* Hook called when a new child process is started. */ 2054 2055void 2056rs6000_create_inferior (int pid) 2057{ 2058 if (rs6000_set_host_arch_hook) 2059 rs6000_set_host_arch_hook (pid); 2060} 2061 2062/* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). 2063 2064 Usually a function pointer's representation is simply the address 2065 of the function. On the RS/6000 however, a function pointer is 2066 represented by a pointer to a TOC entry. This TOC entry contains 2067 three words, the first word is the address of the function, the 2068 second word is the TOC pointer (r2), and the third word is the 2069 static chain value. Throughout GDB it is currently assumed that a 2070 function pointer contains the address of the function, which is not 2071 easy to fix. In addition, the conversion of a function address to 2072 a function pointer would require allocation of a TOC entry in the 2073 inferior's memory space, with all its drawbacks. To be able to 2074 call C++ virtual methods in the inferior (which are called via 2075 function pointers), find_function_addr uses this function to get the 2076 function address from a function pointer. */ 2077 2078/* Return real function address if ADDR (a function pointer) is in the data 2079 space and is therefore a special function pointer. */ 2080 2081static CORE_ADDR 2082rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, 2083 CORE_ADDR addr, 2084 struct target_ops *targ) 2085{ 2086 struct obj_section *s; 2087 2088 s = find_pc_section (addr); 2089 if (s && s->the_bfd_section->flags & SEC_CODE) 2090 return addr; 2091 2092 /* ADDR is in the data space, so it's a special function pointer. */ 2093 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); 2094} 2095 2096 2097/* Handling the various POWER/PowerPC variants. */ 2098 2099 2100/* The arrays here called registers_MUMBLE hold information about available 2101 registers. 2102 2103 For each family of PPC variants, I've tried to isolate out the 2104 common registers and put them up front, so that as long as you get 2105 the general family right, GDB will correctly identify the registers 2106 common to that family. The common register sets are: 2107 2108 For the 60x family: hid0 hid1 iabr dabr pir 2109 2110 For the 505 and 860 family: eie eid nri 2111 2112 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi 2113 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 2114 pbu1 pbl2 pbu2 2115 2116 Most of these register groups aren't anything formal. I arrived at 2117 them by looking at the registers that occurred in more than one 2118 processor. 2119 2120 Note: kevinb/2002-04-30: Support for the fpscr register was added 2121 during April, 2002. Slot 70 is being used for PowerPC and slot 71 2122 for Power. For PowerPC, slot 70 was unused and was already in the 2123 PPC_UISA_SPRS which is ideally where fpscr should go. For Power, 2124 slot 70 was being used for "mq", so the next available slot (71) 2125 was chosen. It would have been nice to be able to make the 2126 register numbers the same across processor cores, but this wasn't 2127 possible without either 1) renumbering some registers for some 2128 processors or 2) assigning fpscr to a really high slot that's 2129 larger than any current register number. Doing (1) is bad because 2130 existing stubs would break. Doing (2) is undesirable because it 2131 would introduce a really large gap between fpscr and the rest of 2132 the registers for most processors. */ 2133 2134/* Convenience macros for populating register arrays. */ 2135 2136/* Within another macro, convert S to a string. */ 2137 2138#define STR(s) #s 2139 2140/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems 2141 and 64 bits on 64-bit systems. */ 2142#define R(name) { STR(name), 4, 8, 0, 0 } 2143 2144/* Return a struct reg defining register NAME that's 32 bits on all 2145 systems. */ 2146#define R4(name) { STR(name), 4, 4, 0, 0 } 2147 2148/* Return a struct reg defining register NAME that's 64 bits on all 2149 systems. */ 2150#define R8(name) { STR(name), 8, 8, 0, 0 } 2151 2152/* Return a struct reg defining register NAME that's 128 bits on all 2153 systems. */ 2154#define R16(name) { STR(name), 16, 16, 0, 0 } 2155 2156/* Return a struct reg defining floating-point register NAME. */ 2157#define F(name) { STR(name), 8, 8, 1, 0 } 2158 2159/* Return a struct reg defining a pseudo register NAME. */ 2160#define P(name) { STR(name), 4, 8, 0, 1} 2161 2162/* Return a struct reg defining register NAME that's 32 bits on 32-bit 2163 systems and that doesn't exist on 64-bit systems. */ 2164#define R32(name) { STR(name), 4, 0, 0, 0 } 2165 2166/* Return a struct reg defining register NAME that's 64 bits on 64-bit 2167 systems and that doesn't exist on 32-bit systems. */ 2168#define R64(name) { STR(name), 0, 8, 0, 0 } 2169 2170/* Return a struct reg placeholder for a register that doesn't exist. */ 2171#define R0 { 0, 0, 0, 0, 0 } 2172 2173/* UISA registers common across all architectures, including POWER. */ 2174 2175#define COMMON_UISA_REGS \ 2176 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ 2177 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ 2178 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ 2179 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ 2180 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ 2181 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ 2182 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ 2183 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ 2184 /* 64 */ R(pc), R(ps) 2185 2186#define COMMON_UISA_NOFP_REGS \ 2187 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ 2188 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ 2189 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ 2190 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ 2191 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \ 2192 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \ 2193 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \ 2194 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \ 2195 /* 64 */ R(pc), R(ps) 2196 2197/* UISA-level SPRs for PowerPC. */ 2198#define PPC_UISA_SPRS \ 2199 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr) 2200 2201/* UISA-level SPRs for PowerPC without floating point support. */ 2202#define PPC_UISA_NOFP_SPRS \ 2203 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0 2204 2205/* Segment registers, for PowerPC. */ 2206#define PPC_SEGMENT_REGS \ 2207 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ 2208 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ 2209 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ 2210 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) 2211 2212/* OEA SPRs for PowerPC. */ 2213#define PPC_OEA_SPRS \ 2214 /* 87 */ R4(pvr), \ 2215 /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \ 2216 /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \ 2217 /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \ 2218 /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \ 2219 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \ 2220 /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \ 2221 /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \ 2222 /* 116 */ R4(dec), R(dabr), R4(ear) 2223 2224/* AltiVec registers. */ 2225#define PPC_ALTIVEC_REGS \ 2226 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ 2227 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ 2228 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ 2229 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ 2230 /*151*/R4(vscr), R4(vrsave) 2231 2232/* Vectors of hi-lo general purpose registers. */ 2233#define PPC_EV_REGS \ 2234 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \ 2235 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \ 2236 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \ 2237 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31) 2238 2239/* Lower half of the EV registers. */ 2240#define PPC_GPRS_PSEUDO_REGS \ 2241 /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \ 2242 /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \ 2243 /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \ 2244 /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31) 2245 2246/* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover 2247 user-level SPR's. */ 2248static const struct reg registers_power[] = 2249{ 2250 COMMON_UISA_REGS, 2251 /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq), 2252 /* 71 */ R4(fpscr) 2253}; 2254 2255/* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only 2256 view of the PowerPC. */ 2257static const struct reg registers_powerpc[] = 2258{ 2259 COMMON_UISA_REGS, 2260 PPC_UISA_SPRS, 2261 PPC_ALTIVEC_REGS 2262}; 2263 2264/* PowerPC UISA - a PPC processor as viewed by user-level 2265 code, but without floating point registers. */ 2266static const struct reg registers_powerpc_nofp[] = 2267{ 2268 COMMON_UISA_NOFP_REGS, 2269 PPC_UISA_SPRS 2270}; 2271 2272/* IBM PowerPC 403. */ 2273static const struct reg registers_403[] = 2274{ 2275 COMMON_UISA_REGS, 2276 PPC_UISA_SPRS, 2277 PPC_SEGMENT_REGS, 2278 PPC_OEA_SPRS, 2279 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), 2280 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), 2281 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), 2282 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), 2283 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), 2284 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2) 2285}; 2286 2287/* IBM PowerPC 403GC. */ 2288static const struct reg registers_403GC[] = 2289{ 2290 COMMON_UISA_REGS, 2291 PPC_UISA_SPRS, 2292 PPC_SEGMENT_REGS, 2293 PPC_OEA_SPRS, 2294 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), 2295 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), 2296 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), 2297 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), 2298 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), 2299 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2), 2300 /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr), 2301 /* 147 */ R(tbhu), R(tblu) 2302}; 2303 2304/* Motorola PowerPC 505. */ 2305static const struct reg registers_505[] = 2306{ 2307 COMMON_UISA_REGS, 2308 PPC_UISA_SPRS, 2309 PPC_SEGMENT_REGS, 2310 PPC_OEA_SPRS, 2311 /* 119 */ R(eie), R(eid), R(nri) 2312}; 2313 2314/* Motorola PowerPC 860 or 850. */ 2315static const struct reg registers_860[] = 2316{ 2317 COMMON_UISA_REGS, 2318 PPC_UISA_SPRS, 2319 PPC_SEGMENT_REGS, 2320 PPC_OEA_SPRS, 2321 /* 119 */ R(eie), R(eid), R(nri), R(cmpa), 2322 /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr), 2323 /* 127 */ R(der), R(counta), R(countb), R(cmpe), 2324 /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1), 2325 /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst), 2326 /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr), 2327 /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr), 2328 /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc), 2329 /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap), 2330 /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn), 2331 /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1), 2332 /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1) 2333}; 2334 2335/* Motorola PowerPC 601. Note that the 601 has different register numbers 2336 for reading and writing RTCU and RTCL. However, how one reads and writes a 2337 register is the stub's problem. */ 2338static const struct reg registers_601[] = 2339{ 2340 COMMON_UISA_REGS, 2341 PPC_UISA_SPRS, 2342 PPC_SEGMENT_REGS, 2343 PPC_OEA_SPRS, 2344 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), 2345 /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl) 2346}; 2347 2348/* Motorola PowerPC 602. */ 2349static const struct reg registers_602[] = 2350{ 2351 COMMON_UISA_REGS, 2352 PPC_UISA_SPRS, 2353 PPC_SEGMENT_REGS, 2354 PPC_OEA_SPRS, 2355 /* 119 */ R(hid0), R(hid1), R(iabr), R0, 2356 /* 123 */ R0, R(tcr), R(ibr), R(esassr), 2357 /* 127 */ R(sebr), R(ser), R(sp), R(lt) 2358}; 2359 2360/* Motorola/IBM PowerPC 603 or 603e. */ 2361static const struct reg registers_603[] = 2362{ 2363 COMMON_UISA_REGS, 2364 PPC_UISA_SPRS, 2365 PPC_SEGMENT_REGS, 2366 PPC_OEA_SPRS, 2367 /* 119 */ R(hid0), R(hid1), R(iabr), R0, 2368 /* 123 */ R0, R(dmiss), R(dcmp), R(hash1), 2369 /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa) 2370}; 2371 2372/* Motorola PowerPC 604 or 604e. */ 2373static const struct reg registers_604[] = 2374{ 2375 COMMON_UISA_REGS, 2376 PPC_UISA_SPRS, 2377 PPC_SEGMENT_REGS, 2378 PPC_OEA_SPRS, 2379 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), 2380 /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2), 2381 /* 127 */ R(sia), R(sda) 2382}; 2383 2384/* Motorola/IBM PowerPC 750 or 740. */ 2385static const struct reg registers_750[] = 2386{ 2387 COMMON_UISA_REGS, 2388 PPC_UISA_SPRS, 2389 PPC_SEGMENT_REGS, 2390 PPC_OEA_SPRS, 2391 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), 2392 /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2), 2393 /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4), 2394 /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia), 2395 /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr), 2396 /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3) 2397}; 2398 2399 2400/* Motorola PowerPC 7400. */ 2401static const struct reg registers_7400[] = 2402{ 2403 /* gpr0-gpr31, fpr0-fpr31 */ 2404 COMMON_UISA_REGS, 2405 /* ctr, xre, lr, cr */ 2406 PPC_UISA_SPRS, 2407 /* sr0-sr15 */ 2408 PPC_SEGMENT_REGS, 2409 PPC_OEA_SPRS, 2410 /* vr0-vr31, vrsave, vscr */ 2411 PPC_ALTIVEC_REGS 2412 /* FIXME? Add more registers? */ 2413}; 2414 2415/* Motorola e500. */ 2416static const struct reg registers_e500[] = 2417{ 2418 R(pc), R(ps), 2419 /* cr, lr, ctr, xer, "" */ 2420 PPC_UISA_NOFP_SPRS, 2421 /* 7...38 */ 2422 PPC_EV_REGS, 2423 R8(acc), R(spefscr), 2424 /* NOTE: Add new registers here the end of the raw register 2425 list and just before the first pseudo register. */ 2426 /* 39...70 */ 2427 PPC_GPRS_PSEUDO_REGS 2428}; 2429 2430/* Information about a particular processor variant. */ 2431 2432struct variant 2433 { 2434 /* Name of this variant. */ 2435 char *name; 2436 2437 /* English description of the variant. */ 2438 char *description; 2439 2440 /* bfd_arch_info.arch corresponding to variant. */ 2441 enum bfd_architecture arch; 2442 2443 /* bfd_arch_info.mach corresponding to variant. */ 2444 unsigned long mach; 2445 2446 /* Number of real registers. */ 2447 int nregs; 2448 2449 /* Number of pseudo registers. */ 2450 int npregs; 2451 2452 /* Number of total registers (the sum of nregs and npregs). */ 2453 int num_tot_regs; 2454 2455 /* Table of register names; registers[R] is the name of the register 2456 number R. */ 2457 const struct reg *regs; 2458 }; 2459 2460#define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) 2461 2462static int 2463num_registers (const struct reg *reg_list, int num_tot_regs) 2464{ 2465 int i; 2466 int nregs = 0; 2467 2468 for (i = 0; i < num_tot_regs; i++) 2469 if (!reg_list[i].pseudo) 2470 nregs++; 2471 2472 return nregs; 2473} 2474 2475static int 2476num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) 2477{ 2478 int i; 2479 int npregs = 0; 2480 2481 for (i = 0; i < num_tot_regs; i++) 2482 if (reg_list[i].pseudo) 2483 npregs ++; 2484 2485 return npregs; 2486} 2487 2488/* Information in this table comes from the following web sites: 2489 IBM: http://www.chips.ibm.com:80/products/embedded/ 2490 Motorola: http://www.mot.com/SPS/PowerPC/ 2491 2492 I'm sure I've got some of the variant descriptions not quite right. 2493 Please report any inaccuracies you find to GDB's maintainer. 2494 2495 If you add entries to this table, please be sure to allow the new 2496 value as an argument to the --with-cpu flag, in configure.in. */ 2497 2498static struct variant variants[] = 2499{ 2500 2501 {"powerpc", "PowerPC user-level", bfd_arch_powerpc, 2502 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), 2503 registers_powerpc}, 2504 {"power", "POWER user-level", bfd_arch_rs6000, 2505 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), 2506 registers_power}, 2507 {"403", "IBM PowerPC 403", bfd_arch_powerpc, 2508 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), 2509 registers_403}, 2510 {"601", "Motorola PowerPC 601", bfd_arch_powerpc, 2511 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), 2512 registers_601}, 2513 {"602", "Motorola PowerPC 602", bfd_arch_powerpc, 2514 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), 2515 registers_602}, 2516 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, 2517 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), 2518 registers_603}, 2519 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, 2520 604, -1, -1, tot_num_registers (registers_604), 2521 registers_604}, 2522 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, 2523 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), 2524 registers_403GC}, 2525 {"505", "Motorola PowerPC 505", bfd_arch_powerpc, 2526 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), 2527 registers_505}, 2528 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, 2529 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), 2530 registers_860}, 2531 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, 2532 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), 2533 registers_750}, 2534 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, 2535 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), 2536 registers_7400}, 2537 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, 2538 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), 2539 registers_e500}, 2540 2541 /* 64-bit */ 2542 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, 2543 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), 2544 registers_powerpc}, 2545 {"620", "Motorola PowerPC 620", bfd_arch_powerpc, 2546 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), 2547 registers_powerpc}, 2548 {"630", "Motorola PowerPC 630", bfd_arch_powerpc, 2549 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), 2550 registers_powerpc}, 2551 {"a35", "PowerPC A35", bfd_arch_powerpc, 2552 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), 2553 registers_powerpc}, 2554 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, 2555 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), 2556 registers_powerpc}, 2557 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, 2558 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), 2559 registers_powerpc}, 2560 2561 /* FIXME: I haven't checked the register sets of the following. */ 2562 {"rs1", "IBM POWER RS1", bfd_arch_rs6000, 2563 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), 2564 registers_power}, 2565 {"rsc", "IBM POWER RSC", bfd_arch_rs6000, 2566 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), 2567 registers_power}, 2568 {"rs2", "IBM POWER RS2", bfd_arch_rs6000, 2569 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), 2570 registers_power}, 2571 2572 {0, 0, 0, 0, 0, 0, 0, 0} 2573}; 2574 2575/* Initialize the number of registers and pseudo registers in each variant. */ 2576 2577static void 2578init_variants (void) 2579{ 2580 struct variant *v; 2581 2582 for (v = variants; v->name; v++) 2583 { 2584 if (v->nregs == -1) 2585 v->nregs = num_registers (v->regs, v->num_tot_regs); 2586 if (v->npregs == -1) 2587 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); 2588 } 2589} 2590 2591/* Return the variant corresponding to architecture ARCH and machine number 2592 MACH. If no such variant exists, return null. */ 2593 2594static const struct variant * 2595find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) 2596{ 2597 const struct variant *v; 2598 2599 for (v = variants; v->name; v++) 2600 if (arch == v->arch && mach == v->mach) 2601 return v; 2602 2603 return NULL; 2604} 2605 2606static int 2607gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) 2608{ 2609 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 2610 return print_insn_big_powerpc (memaddr, info); 2611 else 2612 return print_insn_little_powerpc (memaddr, info); 2613} 2614 2615/* Initialize the current architecture based on INFO. If possible, re-use an 2616 architecture from ARCHES, which is a list of architectures already created 2617 during this debugging session. 2618 2619 Called e.g. at program startup, when reading a core file, and when reading 2620 a binary file. */ 2621 2622static struct gdbarch * 2623rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2624{ 2625 struct gdbarch *gdbarch; 2626 struct gdbarch_tdep *tdep; 2627 int wordsize, from_xcoff_exec, from_elf_exec, power, i, off; 2628 struct reg *regs; 2629 const struct variant *v; 2630 enum bfd_architecture arch; 2631 unsigned long mach; 2632 bfd abfd; 2633 int sysv_abi; 2634 asection *sect; 2635 2636 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && 2637 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; 2638 2639 from_elf_exec = info.abfd && info.abfd->format == bfd_object && 2640 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; 2641 2642 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; 2643 2644 /* Check word size. If INFO is from a binary file, infer it from 2645 that, else choose a likely default. */ 2646 if (from_xcoff_exec) 2647 { 2648 if (bfd_xcoff_is_xcoff64 (info.abfd)) 2649 wordsize = 8; 2650 else 2651 wordsize = 4; 2652 } 2653 else if (from_elf_exec) 2654 { 2655 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 2656 wordsize = 8; 2657 else 2658 wordsize = 4; 2659 } 2660 else 2661 { 2662 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) 2663 wordsize = info.bfd_arch_info->bits_per_word / 2664 info.bfd_arch_info->bits_per_byte; 2665 else 2666 wordsize = 4; 2667 } 2668 2669 /* Find a candidate among extant architectures. */ 2670 for (arches = gdbarch_list_lookup_by_info (arches, &info); 2671 arches != NULL; 2672 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 2673 { 2674 /* Word size in the various PowerPC bfd_arch_info structs isn't 2675 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform 2676 separate word size check. */ 2677 tdep = gdbarch_tdep (arches->gdbarch); 2678 if (tdep && tdep->wordsize == wordsize) 2679 return arches->gdbarch; 2680 } 2681 2682 /* None found, create a new architecture from INFO, whose bfd_arch_info 2683 validity depends on the source: 2684 - executable useless 2685 - rs6000_host_arch() good 2686 - core file good 2687 - "set arch" trust blindly 2688 - GDB startup useless but harmless */ 2689 2690 if (!from_xcoff_exec) 2691 { 2692 arch = info.bfd_arch_info->arch; 2693 mach = info.bfd_arch_info->mach; 2694 } 2695 else 2696 { 2697 arch = bfd_arch_powerpc; 2698 bfd_default_set_arch_mach (&abfd, arch, 0); 2699 info.bfd_arch_info = bfd_get_arch_info (&abfd); 2700 mach = info.bfd_arch_info->mach; 2701 } 2702 tdep = xmalloc (sizeof (struct gdbarch_tdep)); 2703 tdep->wordsize = wordsize; 2704 2705 /* For e500 executables, the apuinfo section is of help here. Such 2706 section contains the identifier and revision number of each 2707 Application-specific Processing Unit that is present on the 2708 chip. The content of the section is determined by the assembler 2709 which looks at each instruction and determines which unit (and 2710 which version of it) can execute it. In our case we just look for 2711 the existance of the section. */ 2712 2713 if (info.abfd) 2714 { 2715 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); 2716 if (sect) 2717 { 2718 arch = info.bfd_arch_info->arch; 2719 mach = bfd_mach_ppc_e500; 2720 bfd_default_set_arch_mach (&abfd, arch, mach); 2721 info.bfd_arch_info = bfd_get_arch_info (&abfd); 2722 } 2723 } 2724 2725 gdbarch = gdbarch_alloc (&info, tdep); 2726 power = arch == bfd_arch_rs6000; 2727 2728 /* Initialize the number of real and pseudo registers in each variant. */ 2729 init_variants (); 2730 2731 /* Choose variant. */ 2732 v = find_variant_by_arch (arch, mach); 2733 if (!v) 2734 return NULL; 2735 2736 tdep->regs = v->regs; 2737 2738 tdep->ppc_gp0_regnum = 0; 2739 tdep->ppc_gplast_regnum = 31; 2740 tdep->ppc_toc_regnum = 2; 2741 tdep->ppc_ps_regnum = 65; 2742 tdep->ppc_cr_regnum = 66; 2743 tdep->ppc_lr_regnum = 67; 2744 tdep->ppc_ctr_regnum = 68; 2745 tdep->ppc_xer_regnum = 69; 2746 if (v->mach == bfd_mach_ppc_601) 2747 tdep->ppc_mq_regnum = 124; 2748 else if (power) 2749 tdep->ppc_mq_regnum = 70; 2750 else 2751 tdep->ppc_mq_regnum = -1; 2752 tdep->ppc_fpscr_regnum = power ? 71 : 70; 2753 2754 set_gdbarch_pc_regnum (gdbarch, 64); 2755 set_gdbarch_sp_regnum (gdbarch, 1); 2756 set_gdbarch_deprecated_fp_regnum (gdbarch, 1); 2757 if (sysv_abi && wordsize == 8) 2758 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); 2759 else if (sysv_abi && wordsize == 4) 2760 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); 2761 else 2762 { 2763 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value); 2764 set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value); 2765 } 2766 2767 if (v->arch == bfd_arch_powerpc) 2768 switch (v->mach) 2769 { 2770 case bfd_mach_ppc: 2771 tdep->ppc_vr0_regnum = 71; 2772 tdep->ppc_vrsave_regnum = 104; 2773 tdep->ppc_ev0_regnum = -1; 2774 tdep->ppc_ev31_regnum = -1; 2775 break; 2776 case bfd_mach_ppc_7400: 2777 tdep->ppc_vr0_regnum = 119; 2778 tdep->ppc_vrsave_regnum = 152; 2779 tdep->ppc_ev0_regnum = -1; 2780 tdep->ppc_ev31_regnum = -1; 2781 break; 2782 case bfd_mach_ppc_e500: 2783 tdep->ppc_gp0_regnum = 41; 2784 tdep->ppc_gplast_regnum = tdep->ppc_gp0_regnum + 32 - 1; 2785 tdep->ppc_toc_regnum = -1; 2786 tdep->ppc_ps_regnum = 1; 2787 tdep->ppc_cr_regnum = 2; 2788 tdep->ppc_lr_regnum = 3; 2789 tdep->ppc_ctr_regnum = 4; 2790 tdep->ppc_xer_regnum = 5; 2791 tdep->ppc_ev0_regnum = 7; 2792 tdep->ppc_ev31_regnum = 38; 2793 set_gdbarch_pc_regnum (gdbarch, 0); 2794 set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); 2795 set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); 2796 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, e500_dwarf2_reg_to_regnum); 2797 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); 2798 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); 2799 break; 2800 default: 2801 tdep->ppc_vr0_regnum = -1; 2802 tdep->ppc_vrsave_regnum = -1; 2803 tdep->ppc_ev0_regnum = -1; 2804 tdep->ppc_ev31_regnum = -1; 2805 break; 2806 } 2807 2808 /* Sanity check on registers. */ 2809 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); 2810 2811 /* Set lr_frame_offset. */ 2812 if (wordsize == 8) 2813 tdep->lr_frame_offset = 16; 2814 else if (sysv_abi) 2815 tdep->lr_frame_offset = 4; 2816 else 2817 tdep->lr_frame_offset = 8; 2818 2819 /* Calculate byte offsets in raw register array. */ 2820 tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int)); 2821 for (i = off = 0; i < v->num_tot_regs; i++) 2822 { 2823 tdep->regoff[i] = off; 2824 off += regsize (v->regs + i, wordsize); 2825 } 2826 2827 /* Select instruction printer. */ 2828 if (arch == power) 2829 set_gdbarch_print_insn (gdbarch, print_insn_rs6000); 2830 else 2831 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); 2832 2833 set_gdbarch_write_pc (gdbarch, generic_target_write_pc); 2834 2835 set_gdbarch_num_regs (gdbarch, v->nregs); 2836 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); 2837 set_gdbarch_register_name (gdbarch, rs6000_register_name); 2838 set_gdbarch_deprecated_register_size (gdbarch, wordsize); 2839 set_gdbarch_deprecated_register_bytes (gdbarch, off); 2840 set_gdbarch_deprecated_register_byte (gdbarch, rs6000_register_byte); 2841 set_gdbarch_deprecated_register_raw_size (gdbarch, rs6000_register_raw_size); 2842 set_gdbarch_deprecated_register_virtual_type (gdbarch, rs6000_register_virtual_type); 2843 2844 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 2845 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 2846 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2847 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 2848 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2849 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2850 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2851 if (sysv_abi) 2852 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); 2853 else 2854 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2855 set_gdbarch_char_signed (gdbarch, 0); 2856 2857 set_gdbarch_frame_align (gdbarch, rs6000_frame_align); 2858 if (sysv_abi && wordsize == 8) 2859 /* PPC64 SYSV. */ 2860 set_gdbarch_frame_red_zone_size (gdbarch, 288); 2861 else if (!sysv_abi && wordsize == 4) 2862 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of 2863 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. 2864 Problem is, 220 isn't frame (16 byte) aligned. Round it up to 2865 224. */ 2866 set_gdbarch_frame_red_zone_size (gdbarch, 224); 2867 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); 2868 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 2869 2870 set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible); 2871 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual); 2872 set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw); 2873 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); 2874 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() 2875 is correct for the SysV ABI when the wordsize is 8, but I'm also 2876 fairly certain that ppc_sysv_abi_push_arguments() will give even 2877 worse results since it only works for 32-bit code. So, for the moment, 2878 we're better off calling rs6000_push_arguments() since it works for 2879 64-bit code. At some point in the future, this matter needs to be 2880 revisited. */ 2881 if (sysv_abi && wordsize == 4) 2882 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); 2883 else if (sysv_abi && wordsize == 8) 2884 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); 2885 else 2886 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); 2887 2888 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); 2889 set_gdbarch_deprecated_pop_frame (gdbarch, rs6000_pop_frame); 2890 2891 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); 2892 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2893 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); 2894 2895 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" 2896 for the descriptor and ".FN" for the entry-point -- a user 2897 specifying "break FN" will unexpectedly end up with a breakpoint 2898 on the descriptor and not the function. This architecture method 2899 transforms any breakpoints on descriptors into breakpoints on the 2900 corresponding entry point. */ 2901 if (sysv_abi && wordsize == 8) 2902 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); 2903 2904 /* Not sure on this. FIXMEmgo */ 2905 set_gdbarch_frame_args_skip (gdbarch, 8); 2906 2907 if (!sysv_abi) 2908 set_gdbarch_use_struct_convention (gdbarch, 2909 rs6000_use_struct_convention); 2910 2911 set_gdbarch_deprecated_frameless_function_invocation (gdbarch, rs6000_frameless_function_invocation); 2912 set_gdbarch_deprecated_frame_chain (gdbarch, rs6000_frame_chain); 2913 set_gdbarch_deprecated_frame_saved_pc (gdbarch, rs6000_frame_saved_pc); 2914 2915 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, rs6000_frame_init_saved_regs); 2916 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, rs6000_init_extra_frame_info); 2917 2918 if (!sysv_abi) 2919 { 2920 /* Handle RS/6000 function pointers (which are really function 2921 descriptors). */ 2922 set_gdbarch_convert_from_func_ptr_addr (gdbarch, 2923 rs6000_convert_from_func_ptr_addr); 2924 } 2925 set_gdbarch_deprecated_frame_args_address (gdbarch, rs6000_frame_args_address); 2926 set_gdbarch_deprecated_frame_locals_address (gdbarch, rs6000_frame_args_address); 2927 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, rs6000_saved_pc_after_call); 2928 2929 /* Helpers for function argument information. */ 2930 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); 2931 2932 /* Hook in ABI-specific overrides, if they have been registered. */ 2933 gdbarch_init_osabi (info, gdbarch); 2934 2935 if (from_xcoff_exec) 2936 { 2937 /* NOTE: jimix/2003-06-09: This test should really check for 2938 GDB_OSABI_AIX when that is defined and becomes 2939 available. (Actually, once things are properly split apart, 2940 the test goes away.) */ 2941 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */ 2942 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step); 2943 } 2944 2945 return gdbarch; 2946} 2947 2948static void 2949rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) 2950{ 2951 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2952 2953 if (tdep == NULL) 2954 return; 2955 2956 /* FIXME: Dump gdbarch_tdep. */ 2957} 2958 2959static struct cmd_list_element *info_powerpc_cmdlist = NULL; 2960 2961static void 2962rs6000_info_powerpc_command (char *args, int from_tty) 2963{ 2964 help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout); 2965} 2966 2967/* Initialization code. */ 2968 2969extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ 2970 2971void 2972_initialize_rs6000_tdep (void) 2973{ 2974 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); 2975 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); 2976 2977 /* Add root prefix command for "info powerpc" commands */ 2978 add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, 2979 "Various POWERPC info specific commands.", 2980 &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); 2981} 2982