1/* tc-arm.c -- Assemble for the ARM 2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 3 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 6 Modified by David Taylor (dtaylor@armltd.co.uk) 7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) 8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com) 9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com) 10 11 This file is part of GAS, the GNU Assembler. 12 13 GAS is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 2, or (at your option) 16 any later version. 17 18 GAS is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with GAS; see the file COPYING. If not, write to the Free 25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 26 02110-1301, USA. */ 27 28#include <limits.h> 29#include <stdarg.h> 30#define NO_RELOC 0 31#include "as.h" 32#include "safe-ctype.h" 33#include "subsegs.h" 34#include "obstack.h" 35 36#include "opcode/arm.h" 37 38#ifdef OBJ_ELF 39#include "elf/arm.h" 40#include "dw2gencfi.h" 41#endif 42 43#include "dwarf2dbg.h" 44 45#define WARN_DEPRECATED 1 46 47#ifdef OBJ_ELF 48/* Must be at least the size of the largest unwind opcode (currently two). */ 49#define ARM_OPCODE_CHUNK_SIZE 8 50 51/* This structure holds the unwinding state. */ 52 53static struct 54{ 55 symbolS * proc_start; 56 symbolS * table_entry; 57 symbolS * personality_routine; 58 int personality_index; 59 /* The segment containing the function. */ 60 segT saved_seg; 61 subsegT saved_subseg; 62 /* Opcodes generated from this function. */ 63 unsigned char * opcodes; 64 int opcode_count; 65 int opcode_alloc; 66 /* The number of bytes pushed to the stack. */ 67 offsetT frame_size; 68 /* We don't add stack adjustment opcodes immediately so that we can merge 69 multiple adjustments. We can also omit the final adjustment 70 when using a frame pointer. */ 71 offsetT pending_offset; 72 /* These two fields are set by both unwind_movsp and unwind_setfp. They 73 hold the reg+offset to use when restoring sp from a frame pointer. */ 74 offsetT fp_offset; 75 int fp_reg; 76 /* Nonzero if an unwind_setfp directive has been seen. */ 77 unsigned fp_used:1; 78 /* Nonzero if the last opcode restores sp from fp_reg. */ 79 unsigned sp_restored:1; 80} unwind; 81 82/* Bit N indicates that an R_ARM_NONE relocation has been output for 83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be 84 emitted only once per section, to save unnecessary bloat. */ 85static unsigned int marked_pr_dependency = 0; 86 87#endif /* OBJ_ELF */ 88 89/* Results from operand parsing worker functions. */ 90 91typedef enum 92{ 93 PARSE_OPERAND_SUCCESS, 94 PARSE_OPERAND_FAIL, 95 PARSE_OPERAND_FAIL_NO_BACKTRACK 96} parse_operand_result; 97 98enum arm_float_abi 99{ 100 ARM_FLOAT_ABI_HARD, 101 ARM_FLOAT_ABI_SOFTFP, 102 ARM_FLOAT_ABI_SOFT 103}; 104 105/* Types of processor to assemble for. */ 106#ifndef CPU_DEFAULT 107#if defined __XSCALE__ 108#define CPU_DEFAULT ARM_ARCH_XSCALE 109#else 110#if defined __thumb__ 111#define CPU_DEFAULT ARM_ARCH_V5T 112#endif 113#endif 114#endif 115 116#ifndef FPU_DEFAULT 117# ifdef TE_LINUX 118# define FPU_DEFAULT FPU_ARCH_FPA 119# elif defined (TE_NetBSD) 120# ifdef OBJ_ELF 121# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */ 122# else 123 /* Legacy a.out format. */ 124# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */ 125# endif 126# elif defined (TE_VXWORKS) 127# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */ 128# else 129 /* For backwards compatibility, default to FPA. */ 130# define FPU_DEFAULT FPU_ARCH_FPA 131# endif 132#endif /* ifndef FPU_DEFAULT */ 133 134#define streq(a, b) (strcmp (a, b) == 0) 135 136static arm_feature_set cpu_variant; 137static arm_feature_set arm_arch_used; 138static arm_feature_set thumb_arch_used; 139 140/* Flags stored in private area of BFD structure. */ 141static int uses_apcs_26 = FALSE; 142static int atpcs = FALSE; 143static int support_interwork = FALSE; 144static int uses_apcs_float = FALSE; 145static int pic_code = FALSE; 146 147/* Variables that we set while parsing command-line options. Once all 148 options have been read we re-process these values to set the real 149 assembly flags. */ 150static const arm_feature_set *legacy_cpu = NULL; 151static const arm_feature_set *legacy_fpu = NULL; 152 153static const arm_feature_set *mcpu_cpu_opt = NULL; 154static const arm_feature_set *mcpu_fpu_opt = NULL; 155static const arm_feature_set *march_cpu_opt = NULL; 156static const arm_feature_set *march_fpu_opt = NULL; 157static const arm_feature_set *mfpu_opt = NULL; 158static const arm_feature_set *object_arch = NULL; 159 160/* Constants for known architecture features. */ 161static const arm_feature_set fpu_default = FPU_DEFAULT; 162static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1; 163static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2; 164static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3; 165static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1; 166static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA; 167static const arm_feature_set fpu_any_hard = FPU_ANY_HARD; 168static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK; 169static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE; 170 171#ifdef CPU_DEFAULT 172static const arm_feature_set cpu_default = CPU_DEFAULT; 173#endif 174 175static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0); 176static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0); 177static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0); 178static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0); 179static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0); 180static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0); 181static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0); 182static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0); 183static const arm_feature_set arm_ext_v4t_5 = 184 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0); 185static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0); 186static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0); 187static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0); 188static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0); 189static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0); 190static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0); 191static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0); 192static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0); 193static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0); 194static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0); 195static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0); 196static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0); 197static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0); 198static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0); 199 200static const arm_feature_set arm_arch_any = ARM_ANY; 201static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1); 202static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2; 203static const arm_feature_set arm_arch_none = ARM_ARCH_NONE; 204 205static const arm_feature_set arm_cext_iwmmxt2 = 206 ARM_FEATURE (0, ARM_CEXT_IWMMXT2); 207static const arm_feature_set arm_cext_iwmmxt = 208 ARM_FEATURE (0, ARM_CEXT_IWMMXT); 209static const arm_feature_set arm_cext_xscale = 210 ARM_FEATURE (0, ARM_CEXT_XSCALE); 211static const arm_feature_set arm_cext_maverick = 212 ARM_FEATURE (0, ARM_CEXT_MAVERICK); 213static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1); 214static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2); 215static const arm_feature_set fpu_vfp_ext_v1xd = 216 ARM_FEATURE (0, FPU_VFP_EXT_V1xD); 217static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1); 218static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2); 219static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3); 220static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); 221static const arm_feature_set fpu_vfp_v3_or_neon_ext = 222 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); 223 224static int mfloat_abi_opt = -1; 225/* Record user cpu selection for object attributes. */ 226static arm_feature_set selected_cpu = ARM_ARCH_NONE; 227/* Must be long enough to hold any of the names in arm_cpus. */ 228static char selected_cpu_name[16]; 229#ifdef OBJ_ELF 230# ifdef EABI_DEFAULT 231static int meabi_flags = EABI_DEFAULT; 232# else 233static int meabi_flags = EF_ARM_EABI_UNKNOWN; 234# endif 235 236bfd_boolean 237arm_is_eabi(void) 238{ 239 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4); 240} 241#endif 242 243#ifdef OBJ_ELF 244/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 245symbolS * GOT_symbol; 246#endif 247 248/* 0: assemble for ARM, 249 1: assemble for Thumb, 250 2: assemble for Thumb even though target CPU does not support thumb 251 instructions. */ 252static int thumb_mode = 0; 253 254/* If unified_syntax is true, we are processing the new unified 255 ARM/Thumb syntax. Important differences from the old ARM mode: 256 257 - Immediate operands do not require a # prefix. 258 - Conditional affixes always appear at the end of the 259 instruction. (For backward compatibility, those instructions 260 that formerly had them in the middle, continue to accept them 261 there.) 262 - The IT instruction may appear, and if it does is validated 263 against subsequent conditional affixes. It does not generate 264 machine code. 265 266 Important differences from the old Thumb mode: 267 268 - Immediate operands do not require a # prefix. 269 - Most of the V6T2 instructions are only available in unified mode. 270 - The .N and .W suffixes are recognized and honored (it is an error 271 if they cannot be honored). 272 - All instructions set the flags if and only if they have an 's' affix. 273 - Conditional affixes may be used. They are validated against 274 preceding IT instructions. Unlike ARM mode, you cannot use a 275 conditional affix except in the scope of an IT instruction. */ 276 277static bfd_boolean unified_syntax = FALSE; 278 279enum neon_el_type 280{ 281 NT_invtype, 282 NT_untyped, 283 NT_integer, 284 NT_float, 285 NT_poly, 286 NT_signed, 287 NT_unsigned 288}; 289 290struct neon_type_el 291{ 292 enum neon_el_type type; 293 unsigned size; 294}; 295 296#define NEON_MAX_TYPE_ELS 4 297 298struct neon_type 299{ 300 struct neon_type_el el[NEON_MAX_TYPE_ELS]; 301 unsigned elems; 302}; 303 304struct arm_it 305{ 306 const char * error; 307 unsigned long instruction; 308 int size; 309 int size_req; 310 int cond; 311 /* "uncond_value" is set to the value in place of the conditional field in 312 unconditional versions of the instruction, or -1 if nothing is 313 appropriate. */ 314 int uncond_value; 315 struct neon_type vectype; 316 /* Set to the opcode if the instruction needs relaxation. 317 Zero if the instruction is not relaxed. */ 318 unsigned long relax; 319 struct 320 { 321 bfd_reloc_code_real_type type; 322 expressionS exp; 323 int pc_rel; 324 } reloc; 325 326 struct 327 { 328 unsigned reg; 329 signed int imm; 330 struct neon_type_el vectype; 331 unsigned present : 1; /* Operand present. */ 332 unsigned isreg : 1; /* Operand was a register. */ 333 unsigned immisreg : 1; /* .imm field is a second register. */ 334 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */ 335 unsigned immisalign : 1; /* Immediate is an alignment specifier. */ 336 unsigned immisfloat : 1; /* Immediate was parsed as a float. */ 337 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV 338 instructions. This allows us to disambiguate ARM <-> vector insns. */ 339 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */ 340 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */ 341 unsigned isquad : 1; /* Operand is Neon quad-precision register. */ 342 unsigned issingle : 1; /* Operand is VFP single-precision register. */ 343 unsigned hasreloc : 1; /* Operand has relocation suffix. */ 344 unsigned writeback : 1; /* Operand has trailing ! */ 345 unsigned preind : 1; /* Preindexed address. */ 346 unsigned postind : 1; /* Postindexed address. */ 347 unsigned negative : 1; /* Index register was negated. */ 348 unsigned shifted : 1; /* Shift applied to operation. */ 349 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ 350 } operands[6]; 351}; 352 353static struct arm_it inst; 354 355#define NUM_FLOAT_VALS 8 356 357const char * fp_const[] = 358{ 359 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0 360}; 361 362/* Number of littlenums required to hold an extended precision number. */ 363#define MAX_LITTLENUMS 6 364 365LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS]; 366 367#define FAIL (-1) 368#define SUCCESS (0) 369 370#define SUFF_S 1 371#define SUFF_D 2 372#define SUFF_E 3 373#define SUFF_P 4 374 375#define CP_T_X 0x00008000 376#define CP_T_Y 0x00400000 377 378#define CONDS_BIT 0x00100000 379#define LOAD_BIT 0x00100000 380 381#define DOUBLE_LOAD_FLAG 0x00000001 382 383struct asm_cond 384{ 385 const char * template; 386 unsigned long value; 387}; 388 389#define COND_ALWAYS 0xE 390 391struct asm_psr 392{ 393 const char *template; 394 unsigned long field; 395}; 396 397struct asm_barrier_opt 398{ 399 const char *template; 400 unsigned long value; 401}; 402 403/* The bit that distinguishes CPSR and SPSR. */ 404#define SPSR_BIT (1 << 22) 405 406/* The individual PSR flag bits. */ 407#define PSR_c (1 << 16) 408#define PSR_x (1 << 17) 409#define PSR_s (1 << 18) 410#define PSR_f (1 << 19) 411 412struct reloc_entry 413{ 414 char *name; 415 bfd_reloc_code_real_type reloc; 416}; 417 418enum vfp_reg_pos 419{ 420 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, 421 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn 422}; 423 424enum vfp_ldstm_type 425{ 426 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX 427}; 428 429/* Bits for DEFINED field in neon_typed_alias. */ 430#define NTA_HASTYPE 1 431#define NTA_HASINDEX 2 432 433struct neon_typed_alias 434{ 435 unsigned char defined; 436 unsigned char index; 437 struct neon_type_el eltype; 438}; 439 440/* ARM register categories. This includes coprocessor numbers and various 441 architecture extensions' registers. */ 442enum arm_reg_type 443{ 444 REG_TYPE_RN, 445 REG_TYPE_CP, 446 REG_TYPE_CN, 447 REG_TYPE_FN, 448 REG_TYPE_VFS, 449 REG_TYPE_VFD, 450 REG_TYPE_NQ, 451 REG_TYPE_VFSD, 452 REG_TYPE_NDQ, 453 REG_TYPE_NSDQ, 454 REG_TYPE_VFC, 455 REG_TYPE_MVF, 456 REG_TYPE_MVD, 457 REG_TYPE_MVFX, 458 REG_TYPE_MVDX, 459 REG_TYPE_MVAX, 460 REG_TYPE_DSPSC, 461 REG_TYPE_MMXWR, 462 REG_TYPE_MMXWC, 463 REG_TYPE_MMXWCG, 464 REG_TYPE_XSCALE, 465}; 466 467/* Structure for a hash table entry for a register. 468 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra 469 information which states whether a vector type or index is specified (for a 470 register alias created with .dn or .qn). Otherwise NEON should be NULL. */ 471struct reg_entry 472{ 473 const char *name; 474 unsigned char number; 475 unsigned char type; 476 unsigned char builtin; 477 struct neon_typed_alias *neon; 478}; 479 480/* Diagnostics used when we don't get a register of the expected type. */ 481const char *const reg_expected_msgs[] = 482{ 483 N_("ARM register expected"), 484 N_("bad or missing co-processor number"), 485 N_("co-processor register expected"), 486 N_("FPA register expected"), 487 N_("VFP single precision register expected"), 488 N_("VFP/Neon double precision register expected"), 489 N_("Neon quad precision register expected"), 490 N_("VFP single or double precision register expected"), 491 N_("Neon double or quad precision register expected"), 492 N_("VFP single, double or Neon quad precision register expected"), 493 N_("VFP system register expected"), 494 N_("Maverick MVF register expected"), 495 N_("Maverick MVD register expected"), 496 N_("Maverick MVFX register expected"), 497 N_("Maverick MVDX register expected"), 498 N_("Maverick MVAX register expected"), 499 N_("Maverick DSPSC register expected"), 500 N_("iWMMXt data register expected"), 501 N_("iWMMXt control register expected"), 502 N_("iWMMXt scalar register expected"), 503 N_("XScale accumulator register expected"), 504}; 505 506/* Some well known registers that we refer to directly elsewhere. */ 507#define REG_SP 13 508#define REG_LR 14 509#define REG_PC 15 510 511/* ARM instructions take 4bytes in the object file, Thumb instructions 512 take 2: */ 513#define INSN_SIZE 4 514 515struct asm_opcode 516{ 517 /* Basic string to match. */ 518 const char *template; 519 520 /* Parameters to instruction. */ 521 unsigned char operands[8]; 522 523 /* Conditional tag - see opcode_lookup. */ 524 unsigned int tag : 4; 525 526 /* Basic instruction code. */ 527 unsigned int avalue : 28; 528 529 /* Thumb-format instruction code. */ 530 unsigned int tvalue; 531 532 /* Which architecture variant provides this instruction. */ 533 const arm_feature_set *avariant; 534 const arm_feature_set *tvariant; 535 536 /* Function to call to encode instruction in ARM format. */ 537 void (* aencode) (void); 538 539 /* Function to call to encode instruction in Thumb format. */ 540 void (* tencode) (void); 541}; 542 543/* Defines for various bits that we will want to toggle. */ 544#define INST_IMMEDIATE 0x02000000 545#define OFFSET_REG 0x02000000 546#define HWOFFSET_IMM 0x00400000 547#define SHIFT_BY_REG 0x00000010 548#define PRE_INDEX 0x01000000 549#define INDEX_UP 0x00800000 550#define WRITE_BACK 0x00200000 551#define LDM_TYPE_2_OR_3 0x00400000 552#define CPSI_MMOD 0x00020000 553 554#define LITERAL_MASK 0xf000f000 555#define OPCODE_MASK 0xfe1fffff 556#define V4_STR_BIT 0x00000020 557 558#define T2_SUBS_PC_LR 0xf3de8f00 559 560#define DATA_OP_SHIFT 21 561 562#define T2_OPCODE_MASK 0xfe1fffff 563#define T2_DATA_OP_SHIFT 21 564 565/* Codes to distinguish the arithmetic instructions. */ 566#define OPCODE_AND 0 567#define OPCODE_EOR 1 568#define OPCODE_SUB 2 569#define OPCODE_RSB 3 570#define OPCODE_ADD 4 571#define OPCODE_ADC 5 572#define OPCODE_SBC 6 573#define OPCODE_RSC 7 574#define OPCODE_TST 8 575#define OPCODE_TEQ 9 576#define OPCODE_CMP 10 577#define OPCODE_CMN 11 578#define OPCODE_ORR 12 579#define OPCODE_MOV 13 580#define OPCODE_BIC 14 581#define OPCODE_MVN 15 582 583#define T2_OPCODE_AND 0 584#define T2_OPCODE_BIC 1 585#define T2_OPCODE_ORR 2 586#define T2_OPCODE_ORN 3 587#define T2_OPCODE_EOR 4 588#define T2_OPCODE_ADD 8 589#define T2_OPCODE_ADC 10 590#define T2_OPCODE_SBC 11 591#define T2_OPCODE_SUB 13 592#define T2_OPCODE_RSB 14 593 594#define T_OPCODE_MUL 0x4340 595#define T_OPCODE_TST 0x4200 596#define T_OPCODE_CMN 0x42c0 597#define T_OPCODE_NEG 0x4240 598#define T_OPCODE_MVN 0x43c0 599 600#define T_OPCODE_ADD_R3 0x1800 601#define T_OPCODE_SUB_R3 0x1a00 602#define T_OPCODE_ADD_HI 0x4400 603#define T_OPCODE_ADD_ST 0xb000 604#define T_OPCODE_SUB_ST 0xb080 605#define T_OPCODE_ADD_SP 0xa800 606#define T_OPCODE_ADD_PC 0xa000 607#define T_OPCODE_ADD_I8 0x3000 608#define T_OPCODE_SUB_I8 0x3800 609#define T_OPCODE_ADD_I3 0x1c00 610#define T_OPCODE_SUB_I3 0x1e00 611 612#define T_OPCODE_ASR_R 0x4100 613#define T_OPCODE_LSL_R 0x4080 614#define T_OPCODE_LSR_R 0x40c0 615#define T_OPCODE_ROR_R 0x41c0 616#define T_OPCODE_ASR_I 0x1000 617#define T_OPCODE_LSL_I 0x0000 618#define T_OPCODE_LSR_I 0x0800 619 620#define T_OPCODE_MOV_I8 0x2000 621#define T_OPCODE_CMP_I8 0x2800 622#define T_OPCODE_CMP_LR 0x4280 623#define T_OPCODE_MOV_HR 0x4600 624#define T_OPCODE_CMP_HR 0x4500 625 626#define T_OPCODE_LDR_PC 0x4800 627#define T_OPCODE_LDR_SP 0x9800 628#define T_OPCODE_STR_SP 0x9000 629#define T_OPCODE_LDR_IW 0x6800 630#define T_OPCODE_STR_IW 0x6000 631#define T_OPCODE_LDR_IH 0x8800 632#define T_OPCODE_STR_IH 0x8000 633#define T_OPCODE_LDR_IB 0x7800 634#define T_OPCODE_STR_IB 0x7000 635#define T_OPCODE_LDR_RW 0x5800 636#define T_OPCODE_STR_RW 0x5000 637#define T_OPCODE_LDR_RH 0x5a00 638#define T_OPCODE_STR_RH 0x5200 639#define T_OPCODE_LDR_RB 0x5c00 640#define T_OPCODE_STR_RB 0x5400 641 642#define T_OPCODE_PUSH 0xb400 643#define T_OPCODE_POP 0xbc00 644 645#define T_OPCODE_BRANCH 0xe000 646 647#define THUMB_SIZE 2 /* Size of thumb instruction. */ 648#define THUMB_PP_PC_LR 0x0100 649#define THUMB_LOAD_BIT 0x0800 650#define THUMB2_LOAD_BIT 0x00100000 651 652#define BAD_ARGS _("bad arguments to instruction") 653#define BAD_PC _("r15 not allowed here") 654#define BAD_SP _("r13 not allowed here") 655#define BAD_COND _("instruction cannot be conditional") 656#define BAD_OVERLAP _("registers may not be the same") 657#define BAD_HIREG _("lo register required") 658#define BAD_THUMB32 _("instruction not supported in Thumb16 mode") 659#define BAD_ADDR_MODE _("instruction does not accept this addressing mode"); 660#define BAD_BRANCH _("branch must be last instruction in IT block") 661#define BAD_NOT_IT _("instruction not allowed in IT block") 662#define BAD_FPU _("selected FPU does not support instruction") 663#define BAD_VMRS _("APSR_nzcv may only be used with fpscr") 664 665static struct hash_control *arm_ops_hsh; 666static struct hash_control *arm_cond_hsh; 667static struct hash_control *arm_shift_hsh; 668static struct hash_control *arm_psr_hsh; 669static struct hash_control *arm_v7m_psr_hsh; 670static struct hash_control *arm_reg_hsh; 671static struct hash_control *arm_reloc_hsh; 672static struct hash_control *arm_barrier_opt_hsh; 673 674/* Stuff needed to resolve the label ambiguity 675 As: 676 ... 677 label: <insn> 678 may differ from: 679 ... 680 label: 681 <insn> 682*/ 683 684symbolS * last_label_seen; 685static int label_is_thumb_function_name = FALSE; 686 687/* Literal pool structure. Held on a per-section 688 and per-sub-section basis. */ 689 690#define MAX_LITERAL_POOL_SIZE 1024 691typedef struct literal_pool 692{ 693 expressionS literals [MAX_LITERAL_POOL_SIZE]; 694 unsigned int next_free_entry; 695 unsigned int id; 696 symbolS * symbol; 697 segT section; 698 subsegT sub_section; 699 struct literal_pool * next; 700} literal_pool; 701 702/* Pointer to a linked list of literal pools. */ 703literal_pool * list_of_pools = NULL; 704 705/* State variables for IT block handling. */ 706static bfd_boolean current_it_mask = 0; 707static int current_cc; 708 709 710/* Pure syntax. */ 711 712/* This array holds the chars that always start a comment. If the 713 pre-processor is disabled, these aren't very useful. */ 714const char comment_chars[] = "@"; 715 716/* This array holds the chars that only start a comment at the beginning of 717 a line. If the line seems to have the form '# 123 filename' 718 .line and .file directives will appear in the pre-processed output. */ 719/* Note that input_file.c hand checks for '#' at the beginning of the 720 first line of the input file. This is because the compiler outputs 721 #NO_APP at the beginning of its output. */ 722/* Also note that comments like this one will always work. */ 723const char line_comment_chars[] = "#"; 724 725const char line_separator_chars[] = ";"; 726 727/* Chars that can be used to separate mant 728 from exp in floating point numbers. */ 729const char EXP_CHARS[] = "eE"; 730 731/* Chars that mean this number is a floating point constant. */ 732/* As in 0f12.456 */ 733/* or 0d1.2345e12 */ 734 735const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 736 737/* Prefix characters that indicate the start of an immediate 738 value. */ 739#define is_immediate_prefix(C) ((C) == '#' || (C) == '$') 740 741/* Separator character handling. */ 742 743#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0) 744 745static inline int 746skip_past_char (char ** str, char c) 747{ 748 if (**str == c) 749 { 750 (*str)++; 751 return SUCCESS; 752 } 753 else 754 return FAIL; 755} 756#define skip_past_comma(str) skip_past_char (str, ',') 757 758/* Arithmetic expressions (possibly involving symbols). */ 759 760/* Return TRUE if anything in the expression is a bignum. */ 761 762static int 763walk_no_bignums (symbolS * sp) 764{ 765 if (symbol_get_value_expression (sp)->X_op == O_big) 766 return 1; 767 768 if (symbol_get_value_expression (sp)->X_add_symbol) 769 { 770 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol) 771 || (symbol_get_value_expression (sp)->X_op_symbol 772 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol))); 773 } 774 775 return 0; 776} 777 778static int in_my_get_expression = 0; 779 780/* Third argument to my_get_expression. */ 781#define GE_NO_PREFIX 0 782#define GE_IMM_PREFIX 1 783#define GE_OPT_PREFIX 2 784/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit) 785 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */ 786#define GE_OPT_PREFIX_BIG 3 787 788static int 789my_get_expression (expressionS * ep, char ** str, int prefix_mode) 790{ 791 char * save_in; 792 segT seg; 793 794 /* In unified syntax, all prefixes are optional. */ 795 if (unified_syntax) 796 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode 797 : GE_OPT_PREFIX; 798 799 switch (prefix_mode) 800 { 801 case GE_NO_PREFIX: break; 802 case GE_IMM_PREFIX: 803 if (!is_immediate_prefix (**str)) 804 { 805 inst.error = _("immediate expression requires a # prefix"); 806 return FAIL; 807 } 808 (*str)++; 809 break; 810 case GE_OPT_PREFIX: 811 case GE_OPT_PREFIX_BIG: 812 if (is_immediate_prefix (**str)) 813 (*str)++; 814 break; 815 default: abort (); 816 } 817 818 memset (ep, 0, sizeof (expressionS)); 819 820 save_in = input_line_pointer; 821 input_line_pointer = *str; 822 in_my_get_expression = 1; 823 seg = expression (ep); 824 in_my_get_expression = 0; 825 826 if (ep->X_op == O_illegal) 827 { 828 /* We found a bad expression in md_operand(). */ 829 *str = input_line_pointer; 830 input_line_pointer = save_in; 831 if (inst.error == NULL) 832 inst.error = _("bad expression"); 833 return 1; 834 } 835 836#ifdef OBJ_AOUT 837 if (seg != absolute_section 838 && seg != text_section 839 && seg != data_section 840 && seg != bss_section 841 && seg != undefined_section) 842 { 843 inst.error = _("bad segment"); 844 *str = input_line_pointer; 845 input_line_pointer = save_in; 846 return 1; 847 } 848#endif 849 850 /* Get rid of any bignums now, so that we don't generate an error for which 851 we can't establish a line number later on. Big numbers are never valid 852 in instructions, which is where this routine is always called. */ 853 if (prefix_mode != GE_OPT_PREFIX_BIG 854 && (ep->X_op == O_big 855 || (ep->X_add_symbol 856 && (walk_no_bignums (ep->X_add_symbol) 857 || (ep->X_op_symbol 858 && walk_no_bignums (ep->X_op_symbol)))))) 859 { 860 inst.error = _("invalid constant"); 861 *str = input_line_pointer; 862 input_line_pointer = save_in; 863 return 1; 864 } 865 866 *str = input_line_pointer; 867 input_line_pointer = save_in; 868 return 0; 869} 870 871/* Turn a string in input_line_pointer into a floating point constant 872 of type TYPE, and store the appropriate bytes in *LITP. The number 873 of LITTLENUMS emitted is stored in *SIZEP. An error message is 874 returned, or NULL on OK. 875 876 Note that fp constants aren't represent in the normal way on the ARM. 877 In big endian mode, things are as expected. However, in little endian 878 mode fp constants are big-endian word-wise, and little-endian byte-wise 879 within the words. For example, (double) 1.1 in big endian mode is 880 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is 881 the byte sequence 99 99 f1 3f 9a 99 99 99. 882 883 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */ 884 885char * 886md_atof (int type, char * litP, int * sizeP) 887{ 888 int prec; 889 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 890 char *t; 891 int i; 892 893 switch (type) 894 { 895 case 'f': 896 case 'F': 897 case 's': 898 case 'S': 899 prec = 2; 900 break; 901 902 case 'd': 903 case 'D': 904 case 'r': 905 case 'R': 906 prec = 4; 907 break; 908 909 case 'x': 910 case 'X': 911 prec = 6; 912 break; 913 914 case 'p': 915 case 'P': 916 prec = 6; 917 break; 918 919 default: 920 *sizeP = 0; 921 return _("bad call to MD_ATOF()"); 922 } 923 924 t = atof_ieee (input_line_pointer, type, words); 925 if (t) 926 input_line_pointer = t; 927 *sizeP = prec * 2; 928 929 if (target_big_endian) 930 { 931 for (i = 0; i < prec; i++) 932 { 933 md_number_to_chars (litP, (valueT) words[i], 2); 934 litP += 2; 935 } 936 } 937 else 938 { 939 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 940 for (i = prec - 1; i >= 0; i--) 941 { 942 md_number_to_chars (litP, (valueT) words[i], 2); 943 litP += 2; 944 } 945 else 946 /* For a 4 byte float the order of elements in `words' is 1 0. 947 For an 8 byte float the order is 1 0 3 2. */ 948 for (i = 0; i < prec; i += 2) 949 { 950 md_number_to_chars (litP, (valueT) words[i + 1], 2); 951 md_number_to_chars (litP + 2, (valueT) words[i], 2); 952 litP += 4; 953 } 954 } 955 956 return 0; 957} 958 959/* We handle all bad expressions here, so that we can report the faulty 960 instruction in the error message. */ 961void 962md_operand (expressionS * expr) 963{ 964 if (in_my_get_expression) 965 expr->X_op = O_illegal; 966} 967 968/* Immediate values. */ 969 970/* Generic immediate-value read function for use in directives. 971 Accepts anything that 'expression' can fold to a constant. 972 *val receives the number. */ 973#ifdef OBJ_ELF 974static int 975immediate_for_directive (int *val) 976{ 977 expressionS exp; 978 exp.X_op = O_illegal; 979 980 if (is_immediate_prefix (*input_line_pointer)) 981 { 982 input_line_pointer++; 983 expression (&exp); 984 } 985 986 if (exp.X_op != O_constant) 987 { 988 as_bad (_("expected #constant")); 989 ignore_rest_of_line (); 990 return FAIL; 991 } 992 *val = exp.X_add_number; 993 return SUCCESS; 994} 995#endif 996 997/* Register parsing. */ 998 999/* Generic register parser. CCP points to what should be the 1000 beginning of a register name. If it is indeed a valid register 1001 name, advance CCP over it and return the reg_entry structure; 1002 otherwise return NULL. Does not issue diagnostics. */ 1003 1004static struct reg_entry * 1005arm_reg_parse_multi (char **ccp) 1006{ 1007 char *start = *ccp; 1008 char *p; 1009 struct reg_entry *reg; 1010 1011#ifdef REGISTER_PREFIX 1012 if (*start != REGISTER_PREFIX) 1013 return NULL; 1014 start++; 1015#endif 1016#ifdef OPTIONAL_REGISTER_PREFIX 1017 if (*start == OPTIONAL_REGISTER_PREFIX) 1018 start++; 1019#endif 1020 1021 p = start; 1022 if (!ISALPHA (*p) || !is_name_beginner (*p)) 1023 return NULL; 1024 1025 do 1026 p++; 1027 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_'); 1028 1029 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start); 1030 1031 if (!reg) 1032 return NULL; 1033 1034 *ccp = p; 1035 return reg; 1036} 1037 1038static int 1039arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, 1040 enum arm_reg_type type) 1041{ 1042 /* Alternative syntaxes are accepted for a few register classes. */ 1043 switch (type) 1044 { 1045 case REG_TYPE_MVF: 1046 case REG_TYPE_MVD: 1047 case REG_TYPE_MVFX: 1048 case REG_TYPE_MVDX: 1049 /* Generic coprocessor register names are allowed for these. */ 1050 if (reg && reg->type == REG_TYPE_CN) 1051 return reg->number; 1052 break; 1053 1054 case REG_TYPE_CP: 1055 /* For backward compatibility, a bare number is valid here. */ 1056 { 1057 unsigned long processor = strtoul (start, ccp, 10); 1058 if (*ccp != start && processor <= 15) 1059 return processor; 1060 } 1061 1062 case REG_TYPE_MMXWC: 1063 /* WC includes WCG. ??? I'm not sure this is true for all 1064 instructions that take WC registers. */ 1065 if (reg && reg->type == REG_TYPE_MMXWCG) 1066 return reg->number; 1067 break; 1068 1069 default: 1070 break; 1071 } 1072 1073 return FAIL; 1074} 1075 1076/* As arm_reg_parse_multi, but the register must be of type TYPE, and the 1077 return value is the register number or FAIL. */ 1078 1079static int 1080arm_reg_parse (char **ccp, enum arm_reg_type type) 1081{ 1082 char *start = *ccp; 1083 struct reg_entry *reg = arm_reg_parse_multi (ccp); 1084 int ret; 1085 1086 /* Do not allow a scalar (reg+index) to parse as a register. */ 1087 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX)) 1088 return FAIL; 1089 1090 if (reg && reg->type == type) 1091 return reg->number; 1092 1093 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL) 1094 return ret; 1095 1096 *ccp = start; 1097 return FAIL; 1098} 1099 1100/* Parse a Neon type specifier. *STR should point at the leading '.' 1101 character. Does no verification at this stage that the type fits the opcode 1102 properly. E.g., 1103 1104 .i32.i32.s16 1105 .s32.f32 1106 .u16 1107 1108 Can all be legally parsed by this function. 1109 1110 Fills in neon_type struct pointer with parsed information, and updates STR 1111 to point after the parsed type specifier. Returns SUCCESS if this was a legal 1112 type, FAIL if not. */ 1113 1114static int 1115parse_neon_type (struct neon_type *type, char **str) 1116{ 1117 char *ptr = *str; 1118 1119 if (type) 1120 type->elems = 0; 1121 1122 while (type->elems < NEON_MAX_TYPE_ELS) 1123 { 1124 enum neon_el_type thistype = NT_untyped; 1125 unsigned thissize = -1u; 1126 1127 if (*ptr != '.') 1128 break; 1129 1130 ptr++; 1131 1132 /* Just a size without an explicit type. */ 1133 if (ISDIGIT (*ptr)) 1134 goto parsesize; 1135 1136 switch (TOLOWER (*ptr)) 1137 { 1138 case 'i': thistype = NT_integer; break; 1139 case 'f': thistype = NT_float; break; 1140 case 'p': thistype = NT_poly; break; 1141 case 's': thistype = NT_signed; break; 1142 case 'u': thistype = NT_unsigned; break; 1143 case 'd': 1144 thistype = NT_float; 1145 thissize = 64; 1146 ptr++; 1147 goto done; 1148 default: 1149 as_bad (_("unexpected character `%c' in type specifier"), *ptr); 1150 return FAIL; 1151 } 1152 1153 ptr++; 1154 1155 /* .f is an abbreviation for .f32. */ 1156 if (thistype == NT_float && !ISDIGIT (*ptr)) 1157 thissize = 32; 1158 else 1159 { 1160 parsesize: 1161 thissize = strtoul (ptr, &ptr, 10); 1162 1163 if (thissize != 8 && thissize != 16 && thissize != 32 1164 && thissize != 64) 1165 { 1166 as_bad (_("bad size %d in type specifier"), thissize); 1167 return FAIL; 1168 } 1169 } 1170 1171 done: 1172 if (type) 1173 { 1174 type->el[type->elems].type = thistype; 1175 type->el[type->elems].size = thissize; 1176 type->elems++; 1177 } 1178 } 1179 1180 /* Empty/missing type is not a successful parse. */ 1181 if (type->elems == 0) 1182 return FAIL; 1183 1184 *str = ptr; 1185 1186 return SUCCESS; 1187} 1188 1189/* Errors may be set multiple times during parsing or bit encoding 1190 (particularly in the Neon bits), but usually the earliest error which is set 1191 will be the most meaningful. Avoid overwriting it with later (cascading) 1192 errors by calling this function. */ 1193 1194static void 1195first_error (const char *err) 1196{ 1197 if (!inst.error) 1198 inst.error = err; 1199} 1200 1201/* Parse a single type, e.g. ".s32", leading period included. */ 1202static int 1203parse_neon_operand_type (struct neon_type_el *vectype, char **ccp) 1204{ 1205 char *str = *ccp; 1206 struct neon_type optype; 1207 1208 if (*str == '.') 1209 { 1210 if (parse_neon_type (&optype, &str) == SUCCESS) 1211 { 1212 if (optype.elems == 1) 1213 *vectype = optype.el[0]; 1214 else 1215 { 1216 first_error (_("only one type should be specified for operand")); 1217 return FAIL; 1218 } 1219 } 1220 else 1221 { 1222 first_error (_("vector type expected")); 1223 return FAIL; 1224 } 1225 } 1226 else 1227 return FAIL; 1228 1229 *ccp = str; 1230 1231 return SUCCESS; 1232} 1233 1234/* Special meanings for indices (which have a range of 0-7), which will fit into 1235 a 4-bit integer. */ 1236 1237#define NEON_ALL_LANES 15 1238#define NEON_INTERLEAVE_LANES 14 1239 1240/* Parse either a register or a scalar, with an optional type. Return the 1241 register number, and optionally fill in the actual type of the register 1242 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and 1243 type/index information in *TYPEINFO. */ 1244 1245static int 1246parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, 1247 enum arm_reg_type *rtype, 1248 struct neon_typed_alias *typeinfo) 1249{ 1250 char *str = *ccp; 1251 struct reg_entry *reg = arm_reg_parse_multi (&str); 1252 struct neon_typed_alias atype; 1253 struct neon_type_el parsetype; 1254 1255 atype.defined = 0; 1256 atype.index = -1; 1257 atype.eltype.type = NT_invtype; 1258 atype.eltype.size = -1; 1259 1260 /* Try alternate syntax for some types of register. Note these are mutually 1261 exclusive with the Neon syntax extensions. */ 1262 if (reg == NULL) 1263 { 1264 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type); 1265 if (altreg != FAIL) 1266 *ccp = str; 1267 if (typeinfo) 1268 *typeinfo = atype; 1269 return altreg; 1270 } 1271 1272 /* Undo polymorphism when a set of register types may be accepted. */ 1273 if ((type == REG_TYPE_NDQ 1274 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD)) 1275 || (type == REG_TYPE_VFSD 1276 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD)) 1277 || (type == REG_TYPE_NSDQ 1278 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD 1279 || reg->type == REG_TYPE_NQ)) 1280 || (type == REG_TYPE_MMXWC 1281 && (reg->type == REG_TYPE_MMXWCG))) 1282 type = reg->type; 1283 1284 if (type != reg->type) 1285 return FAIL; 1286 1287 if (reg->neon) 1288 atype = *reg->neon; 1289 1290 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS) 1291 { 1292 if ((atype.defined & NTA_HASTYPE) != 0) 1293 { 1294 first_error (_("can't redefine type for operand")); 1295 return FAIL; 1296 } 1297 atype.defined |= NTA_HASTYPE; 1298 atype.eltype = parsetype; 1299 } 1300 1301 if (skip_past_char (&str, '[') == SUCCESS) 1302 { 1303 if (type != REG_TYPE_VFD) 1304 { 1305 first_error (_("only D registers may be indexed")); 1306 return FAIL; 1307 } 1308 1309 if ((atype.defined & NTA_HASINDEX) != 0) 1310 { 1311 first_error (_("can't change index for operand")); 1312 return FAIL; 1313 } 1314 1315 atype.defined |= NTA_HASINDEX; 1316 1317 if (skip_past_char (&str, ']') == SUCCESS) 1318 atype.index = NEON_ALL_LANES; 1319 else 1320 { 1321 expressionS exp; 1322 1323 my_get_expression (&exp, &str, GE_NO_PREFIX); 1324 1325 if (exp.X_op != O_constant) 1326 { 1327 first_error (_("constant expression required")); 1328 return FAIL; 1329 } 1330 1331 if (skip_past_char (&str, ']') == FAIL) 1332 return FAIL; 1333 1334 atype.index = exp.X_add_number; 1335 } 1336 } 1337 1338 if (typeinfo) 1339 *typeinfo = atype; 1340 1341 if (rtype) 1342 *rtype = type; 1343 1344 *ccp = str; 1345 1346 return reg->number; 1347} 1348 1349/* Like arm_reg_parse, but allow allow the following extra features: 1350 - If RTYPE is non-zero, return the (possibly restricted) type of the 1351 register (e.g. Neon double or quad reg when either has been requested). 1352 - If this is a Neon vector type with additional type information, fill 1353 in the struct pointed to by VECTYPE (if non-NULL). 1354 This function will fault on encountering a scalar. 1355*/ 1356 1357static int 1358arm_typed_reg_parse (char **ccp, enum arm_reg_type type, 1359 enum arm_reg_type *rtype, struct neon_type_el *vectype) 1360{ 1361 struct neon_typed_alias atype; 1362 char *str = *ccp; 1363 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype); 1364 1365 if (reg == FAIL) 1366 return FAIL; 1367 1368 /* Do not allow a scalar (reg+index) to parse as a register. */ 1369 if ((atype.defined & NTA_HASINDEX) != 0) 1370 { 1371 first_error (_("register operand expected, but got scalar")); 1372 return FAIL; 1373 } 1374 1375 if (vectype) 1376 *vectype = atype.eltype; 1377 1378 *ccp = str; 1379 1380 return reg; 1381} 1382 1383#define NEON_SCALAR_REG(X) ((X) >> 4) 1384#define NEON_SCALAR_INDEX(X) ((X) & 15) 1385 1386/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't 1387 have enough information to be able to do a good job bounds-checking. So, we 1388 just do easy checks here, and do further checks later. */ 1389 1390static int 1391parse_scalar (char **ccp, int elsize, struct neon_type_el *type) 1392{ 1393 int reg; 1394 char *str = *ccp; 1395 struct neon_typed_alias atype; 1396 1397 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype); 1398 1399 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0) 1400 return FAIL; 1401 1402 if (atype.index == NEON_ALL_LANES) 1403 { 1404 first_error (_("scalar must have an index")); 1405 return FAIL; 1406 } 1407 else if (atype.index >= 64 / elsize) 1408 { 1409 first_error (_("scalar index out of range")); 1410 return FAIL; 1411 } 1412 1413 if (type) 1414 *type = atype.eltype; 1415 1416 *ccp = str; 1417 1418 return reg * 16 + atype.index; 1419} 1420 1421/* Parse an ARM register list. Returns the bitmask, or FAIL. */ 1422static long 1423parse_reg_list (char ** strp) 1424{ 1425 char * str = * strp; 1426 long range = 0; 1427 int another_range; 1428 1429 /* We come back here if we get ranges concatenated by '+' or '|'. */ 1430 do 1431 { 1432 another_range = 0; 1433 1434 if (*str == '{') 1435 { 1436 int in_range = 0; 1437 int cur_reg = -1; 1438 1439 str++; 1440 do 1441 { 1442 int reg; 1443 1444 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL) 1445 { 1446 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 1447 return FAIL; 1448 } 1449 1450 if (in_range) 1451 { 1452 int i; 1453 1454 if (reg <= cur_reg) 1455 { 1456 first_error (_("bad range in register list")); 1457 return FAIL; 1458 } 1459 1460 for (i = cur_reg + 1; i < reg; i++) 1461 { 1462 if (range & (1 << i)) 1463 as_tsktsk 1464 (_("Warning: duplicated register (r%d) in register list"), 1465 i); 1466 else 1467 range |= 1 << i; 1468 } 1469 in_range = 0; 1470 } 1471 1472 if (range & (1 << reg)) 1473 as_tsktsk (_("Warning: duplicated register (r%d) in register list"), 1474 reg); 1475 else if (reg <= cur_reg) 1476 as_tsktsk (_("Warning: register range not in ascending order")); 1477 1478 range |= 1 << reg; 1479 cur_reg = reg; 1480 } 1481 while (skip_past_comma (&str) != FAIL 1482 || (in_range = 1, *str++ == '-')); 1483 str--; 1484 1485 if (*str++ != '}') 1486 { 1487 first_error (_("missing `}'")); 1488 return FAIL; 1489 } 1490 } 1491 else 1492 { 1493 expressionS expr; 1494 1495 if (my_get_expression (&expr, &str, GE_NO_PREFIX)) 1496 return FAIL; 1497 1498 if (expr.X_op == O_constant) 1499 { 1500 if (expr.X_add_number 1501 != (expr.X_add_number & 0x0000ffff)) 1502 { 1503 inst.error = _("invalid register mask"); 1504 return FAIL; 1505 } 1506 1507 if ((range & expr.X_add_number) != 0) 1508 { 1509 int regno = range & expr.X_add_number; 1510 1511 regno &= -regno; 1512 regno = (1 << regno) - 1; 1513 as_tsktsk 1514 (_("Warning: duplicated register (r%d) in register list"), 1515 regno); 1516 } 1517 1518 range |= expr.X_add_number; 1519 } 1520 else 1521 { 1522 if (inst.reloc.type != 0) 1523 { 1524 inst.error = _("expression too complex"); 1525 return FAIL; 1526 } 1527 1528 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS)); 1529 inst.reloc.type = BFD_RELOC_ARM_MULTI; 1530 inst.reloc.pc_rel = 0; 1531 } 1532 } 1533 1534 if (*str == '|' || *str == '+') 1535 { 1536 str++; 1537 another_range = 1; 1538 } 1539 } 1540 while (another_range); 1541 1542 *strp = str; 1543 return range; 1544} 1545 1546/* Types of registers in a list. */ 1547 1548enum reg_list_els 1549{ 1550 REGLIST_VFP_S, 1551 REGLIST_VFP_D, 1552 REGLIST_NEON_D 1553}; 1554 1555/* Parse a VFP register list. If the string is invalid return FAIL. 1556 Otherwise return the number of registers, and set PBASE to the first 1557 register. Parses registers of type ETYPE. 1558 If REGLIST_NEON_D is used, several syntax enhancements are enabled: 1559 - Q registers can be used to specify pairs of D registers 1560 - { } can be omitted from around a singleton register list 1561 FIXME: This is not implemented, as it would require backtracking in 1562 some cases, e.g.: 1563 vtbl.8 d3,d4,d5 1564 This could be done (the meaning isn't really ambiguous), but doesn't 1565 fit in well with the current parsing framework. 1566 - 32 D registers may be used (also true for VFPv3). 1567 FIXME: Types are ignored in these register lists, which is probably a 1568 bug. */ 1569 1570static int 1571parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype) 1572{ 1573 char *str = *ccp; 1574 int base_reg; 1575 int new_base; 1576 enum arm_reg_type regtype = 0; 1577 int max_regs = 0; 1578 int count = 0; 1579 int warned = 0; 1580 unsigned long mask = 0; 1581 int i; 1582 1583 if (*str != '{') 1584 { 1585 inst.error = _("expecting {"); 1586 return FAIL; 1587 } 1588 1589 str++; 1590 1591 switch (etype) 1592 { 1593 case REGLIST_VFP_S: 1594 regtype = REG_TYPE_VFS; 1595 max_regs = 32; 1596 break; 1597 1598 case REGLIST_VFP_D: 1599 regtype = REG_TYPE_VFD; 1600 break; 1601 1602 case REGLIST_NEON_D: 1603 regtype = REG_TYPE_NDQ; 1604 break; 1605 } 1606 1607 if (etype != REGLIST_VFP_S) 1608 { 1609 /* VFPv3 allows 32 D registers. */ 1610 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 1611 { 1612 max_regs = 32; 1613 if (thumb_mode) 1614 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 1615 fpu_vfp_ext_v3); 1616 else 1617 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 1618 fpu_vfp_ext_v3); 1619 } 1620 else 1621 max_regs = 16; 1622 } 1623 1624 base_reg = max_regs; 1625 1626 do 1627 { 1628 int setmask = 1, addregs = 1; 1629 1630 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL); 1631 1632 if (new_base == FAIL) 1633 { 1634 first_error (_(reg_expected_msgs[regtype])); 1635 return FAIL; 1636 } 1637 1638 if (new_base >= max_regs) 1639 { 1640 first_error (_("register out of range in list")); 1641 return FAIL; 1642 } 1643 1644 /* Note: a value of 2 * n is returned for the register Q<n>. */ 1645 if (regtype == REG_TYPE_NQ) 1646 { 1647 setmask = 3; 1648 addregs = 2; 1649 } 1650 1651 if (new_base < base_reg) 1652 base_reg = new_base; 1653 1654 if (mask & (setmask << new_base)) 1655 { 1656 first_error (_("invalid register list")); 1657 return FAIL; 1658 } 1659 1660 if ((mask >> new_base) != 0 && ! warned) 1661 { 1662 as_tsktsk (_("register list not in ascending order")); 1663 warned = 1; 1664 } 1665 1666 mask |= setmask << new_base; 1667 count += addregs; 1668 1669 if (*str == '-') /* We have the start of a range expression */ 1670 { 1671 int high_range; 1672 1673 str++; 1674 1675 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL)) 1676 == FAIL) 1677 { 1678 inst.error = gettext (reg_expected_msgs[regtype]); 1679 return FAIL; 1680 } 1681 1682 if (high_range >= max_regs) 1683 { 1684 first_error (_("register out of range in list")); 1685 return FAIL; 1686 } 1687 1688 if (regtype == REG_TYPE_NQ) 1689 high_range = high_range + 1; 1690 1691 if (high_range <= new_base) 1692 { 1693 inst.error = _("register range not in ascending order"); 1694 return FAIL; 1695 } 1696 1697 for (new_base += addregs; new_base <= high_range; new_base += addregs) 1698 { 1699 if (mask & (setmask << new_base)) 1700 { 1701 inst.error = _("invalid register list"); 1702 return FAIL; 1703 } 1704 1705 mask |= setmask << new_base; 1706 count += addregs; 1707 } 1708 } 1709 } 1710 while (skip_past_comma (&str) != FAIL); 1711 1712 str++; 1713 1714 /* Sanity check -- should have raised a parse error above. */ 1715 if (count == 0 || count > max_regs) 1716 abort (); 1717 1718 *pbase = base_reg; 1719 1720 /* Final test -- the registers must be consecutive. */ 1721 mask >>= base_reg; 1722 for (i = 0; i < count; i++) 1723 { 1724 if ((mask & (1u << i)) == 0) 1725 { 1726 inst.error = _("non-contiguous register range"); 1727 return FAIL; 1728 } 1729 } 1730 1731 *ccp = str; 1732 1733 return count; 1734} 1735 1736/* True if two alias types are the same. */ 1737 1738static int 1739neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b) 1740{ 1741 if (!a && !b) 1742 return 1; 1743 1744 if (!a || !b) 1745 return 0; 1746 1747 if (a->defined != b->defined) 1748 return 0; 1749 1750 if ((a->defined & NTA_HASTYPE) != 0 1751 && (a->eltype.type != b->eltype.type 1752 || a->eltype.size != b->eltype.size)) 1753 return 0; 1754 1755 if ((a->defined & NTA_HASINDEX) != 0 1756 && (a->index != b->index)) 1757 return 0; 1758 1759 return 1; 1760} 1761 1762/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions. 1763 The base register is put in *PBASE. 1764 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of 1765 the return value. 1766 The register stride (minus one) is put in bit 4 of the return value. 1767 Bits [6:5] encode the list length (minus one). 1768 The type of the list elements is put in *ELTYPE, if non-NULL. */ 1769 1770#define NEON_LANE(X) ((X) & 0xf) 1771#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1) 1772#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1) 1773 1774static int 1775parse_neon_el_struct_list (char **str, unsigned *pbase, 1776 struct neon_type_el *eltype) 1777{ 1778 char *ptr = *str; 1779 int base_reg = -1; 1780 int reg_incr = -1; 1781 int count = 0; 1782 int lane = -1; 1783 int leading_brace = 0; 1784 enum arm_reg_type rtype = REG_TYPE_NDQ; 1785 int addregs = 1; 1786 const char *const incr_error = "register stride must be 1 or 2"; 1787 const char *const type_error = "mismatched element/structure types in list"; 1788 struct neon_typed_alias firsttype; 1789 1790 if (skip_past_char (&ptr, '{') == SUCCESS) 1791 leading_brace = 1; 1792 1793 do 1794 { 1795 struct neon_typed_alias atype; 1796 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype); 1797 1798 if (getreg == FAIL) 1799 { 1800 first_error (_(reg_expected_msgs[rtype])); 1801 return FAIL; 1802 } 1803 1804 if (base_reg == -1) 1805 { 1806 base_reg = getreg; 1807 if (rtype == REG_TYPE_NQ) 1808 { 1809 reg_incr = 1; 1810 addregs = 2; 1811 } 1812 firsttype = atype; 1813 } 1814 else if (reg_incr == -1) 1815 { 1816 reg_incr = getreg - base_reg; 1817 if (reg_incr < 1 || reg_incr > 2) 1818 { 1819 first_error (_(incr_error)); 1820 return FAIL; 1821 } 1822 } 1823 else if (getreg != base_reg + reg_incr * count) 1824 { 1825 first_error (_(incr_error)); 1826 return FAIL; 1827 } 1828 1829 if (!neon_alias_types_same (&atype, &firsttype)) 1830 { 1831 first_error (_(type_error)); 1832 return FAIL; 1833 } 1834 1835 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list 1836 modes. */ 1837 if (ptr[0] == '-') 1838 { 1839 struct neon_typed_alias htype; 1840 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1; 1841 if (lane == -1) 1842 lane = NEON_INTERLEAVE_LANES; 1843 else if (lane != NEON_INTERLEAVE_LANES) 1844 { 1845 first_error (_(type_error)); 1846 return FAIL; 1847 } 1848 if (reg_incr == -1) 1849 reg_incr = 1; 1850 else if (reg_incr != 1) 1851 { 1852 first_error (_("don't use Rn-Rm syntax with non-unit stride")); 1853 return FAIL; 1854 } 1855 ptr++; 1856 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype); 1857 if (hireg == FAIL) 1858 { 1859 first_error (_(reg_expected_msgs[rtype])); 1860 return FAIL; 1861 } 1862 if (!neon_alias_types_same (&htype, &firsttype)) 1863 { 1864 first_error (_(type_error)); 1865 return FAIL; 1866 } 1867 count += hireg + dregs - getreg; 1868 continue; 1869 } 1870 1871 /* If we're using Q registers, we can't use [] or [n] syntax. */ 1872 if (rtype == REG_TYPE_NQ) 1873 { 1874 count += 2; 1875 continue; 1876 } 1877 1878 if ((atype.defined & NTA_HASINDEX) != 0) 1879 { 1880 if (lane == -1) 1881 lane = atype.index; 1882 else if (lane != atype.index) 1883 { 1884 first_error (_(type_error)); 1885 return FAIL; 1886 } 1887 } 1888 else if (lane == -1) 1889 lane = NEON_INTERLEAVE_LANES; 1890 else if (lane != NEON_INTERLEAVE_LANES) 1891 { 1892 first_error (_(type_error)); 1893 return FAIL; 1894 } 1895 count++; 1896 } 1897 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL); 1898 1899 /* No lane set by [x]. We must be interleaving structures. */ 1900 if (lane == -1) 1901 lane = NEON_INTERLEAVE_LANES; 1902 1903 /* Sanity check. */ 1904 if (lane == -1 || base_reg == -1 || count < 1 || count > 4 1905 || (count > 1 && reg_incr == -1)) 1906 { 1907 first_error (_("error parsing element/structure list")); 1908 return FAIL; 1909 } 1910 1911 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL) 1912 { 1913 first_error (_("expected }")); 1914 return FAIL; 1915 } 1916 1917 if (reg_incr == -1) 1918 reg_incr = 1; 1919 1920 if (eltype) 1921 *eltype = firsttype.eltype; 1922 1923 *pbase = base_reg; 1924 *str = ptr; 1925 1926 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5); 1927} 1928 1929/* Parse an explicit relocation suffix on an expression. This is 1930 either nothing, or a word in parentheses. Note that if !OBJ_ELF, 1931 arm_reloc_hsh contains no entries, so this function can only 1932 succeed if there is no () after the word. Returns -1 on error, 1933 BFD_RELOC_UNUSED if there wasn't any suffix. */ 1934static int 1935parse_reloc (char **str) 1936{ 1937 struct reloc_entry *r; 1938 char *p, *q; 1939 1940 if (**str != '(') 1941 return BFD_RELOC_UNUSED; 1942 1943 p = *str + 1; 1944 q = p; 1945 1946 while (*q && *q != ')' && *q != ',') 1947 q++; 1948 if (*q != ')') 1949 return -1; 1950 1951 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL) 1952 return -1; 1953 1954 *str = q + 1; 1955 return r->reloc; 1956} 1957 1958/* Directives: register aliases. */ 1959 1960static struct reg_entry * 1961insert_reg_alias (char *str, int number, int type) 1962{ 1963 struct reg_entry *new; 1964 const char *name; 1965 1966 if ((new = hash_find (arm_reg_hsh, str)) != 0) 1967 { 1968 if (new->builtin) 1969 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str); 1970 1971 /* Only warn about a redefinition if it's not defined as the 1972 same register. */ 1973 else if (new->number != number || new->type != type) 1974 as_warn (_("ignoring redefinition of register alias '%s'"), str); 1975 1976 return 0; 1977 } 1978 1979 name = xstrdup (str); 1980 new = xmalloc (sizeof (struct reg_entry)); 1981 1982 new->name = name; 1983 new->number = number; 1984 new->type = type; 1985 new->builtin = FALSE; 1986 new->neon = NULL; 1987 1988 if (hash_insert (arm_reg_hsh, name, (PTR) new)) 1989 abort (); 1990 1991 return new; 1992} 1993 1994static void 1995insert_neon_reg_alias (char *str, int number, int type, 1996 struct neon_typed_alias *atype) 1997{ 1998 struct reg_entry *reg = insert_reg_alias (str, number, type); 1999 2000 if (!reg) 2001 { 2002 first_error (_("attempt to redefine typed alias")); 2003 return; 2004 } 2005 2006 if (atype) 2007 { 2008 reg->neon = xmalloc (sizeof (struct neon_typed_alias)); 2009 *reg->neon = *atype; 2010 } 2011} 2012 2013/* Look for the .req directive. This is of the form: 2014 2015 new_register_name .req existing_register_name 2016 2017 If we find one, or if it looks sufficiently like one that we want to 2018 handle any error here, return non-zero. Otherwise return zero. */ 2019 2020static int 2021create_register_alias (char * newname, char *p) 2022{ 2023 struct reg_entry *old; 2024 char *oldname, *nbuf; 2025 size_t nlen; 2026 2027 /* The input scrubber ensures that whitespace after the mnemonic is 2028 collapsed to single spaces. */ 2029 oldname = p; 2030 if (strncmp (oldname, " .req ", 6) != 0) 2031 return 0; 2032 2033 oldname += 6; 2034 if (*oldname == '\0') 2035 return 0; 2036 2037 old = hash_find (arm_reg_hsh, oldname); 2038 if (!old) 2039 { 2040 as_warn (_("unknown register '%s' -- .req ignored"), oldname); 2041 return 1; 2042 } 2043 2044 /* If TC_CASE_SENSITIVE is defined, then newname already points to 2045 the desired alias name, and p points to its end. If not, then 2046 the desired alias name is in the global original_case_string. */ 2047#ifdef TC_CASE_SENSITIVE 2048 nlen = p - newname; 2049#else 2050 newname = original_case_string; 2051 nlen = strlen (newname); 2052#endif 2053 2054 nbuf = alloca (nlen + 1); 2055 memcpy (nbuf, newname, nlen); 2056 nbuf[nlen] = '\0'; 2057 2058 /* Create aliases under the new name as stated; an all-lowercase 2059 version of the new name; and an all-uppercase version of the new 2060 name. */ 2061 insert_reg_alias (nbuf, old->number, old->type); 2062 2063 for (p = nbuf; *p; p++) 2064 *p = TOUPPER (*p); 2065 2066 if (strncmp (nbuf, newname, nlen)) 2067 insert_reg_alias (nbuf, old->number, old->type); 2068 2069 for (p = nbuf; *p; p++) 2070 *p = TOLOWER (*p); 2071 2072 if (strncmp (nbuf, newname, nlen)) 2073 insert_reg_alias (nbuf, old->number, old->type); 2074 2075 return 1; 2076} 2077 2078/* Create a Neon typed/indexed register alias using directives, e.g.: 2079 X .dn d5.s32[1] 2080 Y .qn 6.s16 2081 Z .dn d7 2082 T .dn Z[0] 2083 These typed registers can be used instead of the types specified after the 2084 Neon mnemonic, so long as all operands given have types. Types can also be 2085 specified directly, e.g.: 2086 vadd d0.s32, d1.s32, d2.s32 2087*/ 2088 2089static int 2090create_neon_reg_alias (char *newname, char *p) 2091{ 2092 enum arm_reg_type basetype; 2093 struct reg_entry *basereg; 2094 struct reg_entry mybasereg; 2095 struct neon_type ntype; 2096 struct neon_typed_alias typeinfo; 2097 char *namebuf, *nameend; 2098 int namelen; 2099 2100 typeinfo.defined = 0; 2101 typeinfo.eltype.type = NT_invtype; 2102 typeinfo.eltype.size = -1; 2103 typeinfo.index = -1; 2104 2105 nameend = p; 2106 2107 if (strncmp (p, " .dn ", 5) == 0) 2108 basetype = REG_TYPE_VFD; 2109 else if (strncmp (p, " .qn ", 5) == 0) 2110 basetype = REG_TYPE_NQ; 2111 else 2112 return 0; 2113 2114 p += 5; 2115 2116 if (*p == '\0') 2117 return 0; 2118 2119 basereg = arm_reg_parse_multi (&p); 2120 2121 if (basereg && basereg->type != basetype) 2122 { 2123 as_bad (_("bad type for register")); 2124 return 0; 2125 } 2126 2127 if (basereg == NULL) 2128 { 2129 expressionS exp; 2130 /* Try parsing as an integer. */ 2131 my_get_expression (&exp, &p, GE_NO_PREFIX); 2132 if (exp.X_op != O_constant) 2133 { 2134 as_bad (_("expression must be constant")); 2135 return 0; 2136 } 2137 basereg = &mybasereg; 2138 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2 2139 : exp.X_add_number; 2140 basereg->neon = 0; 2141 } 2142 2143 if (basereg->neon) 2144 typeinfo = *basereg->neon; 2145 2146 if (parse_neon_type (&ntype, &p) == SUCCESS) 2147 { 2148 /* We got a type. */ 2149 if (typeinfo.defined & NTA_HASTYPE) 2150 { 2151 as_bad (_("can't redefine the type of a register alias")); 2152 return 0; 2153 } 2154 2155 typeinfo.defined |= NTA_HASTYPE; 2156 if (ntype.elems != 1) 2157 { 2158 as_bad (_("you must specify a single type only")); 2159 return 0; 2160 } 2161 typeinfo.eltype = ntype.el[0]; 2162 } 2163 2164 if (skip_past_char (&p, '[') == SUCCESS) 2165 { 2166 expressionS exp; 2167 /* We got a scalar index. */ 2168 2169 if (typeinfo.defined & NTA_HASINDEX) 2170 { 2171 as_bad (_("can't redefine the index of a scalar alias")); 2172 return 0; 2173 } 2174 2175 my_get_expression (&exp, &p, GE_NO_PREFIX); 2176 2177 if (exp.X_op != O_constant) 2178 { 2179 as_bad (_("scalar index must be constant")); 2180 return 0; 2181 } 2182 2183 typeinfo.defined |= NTA_HASINDEX; 2184 typeinfo.index = exp.X_add_number; 2185 2186 if (skip_past_char (&p, ']') == FAIL) 2187 { 2188 as_bad (_("expecting ]")); 2189 return 0; 2190 } 2191 } 2192 2193 namelen = nameend - newname; 2194 namebuf = alloca (namelen + 1); 2195 strncpy (namebuf, newname, namelen); 2196 namebuf[namelen] = '\0'; 2197 2198 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2199 typeinfo.defined != 0 ? &typeinfo : NULL); 2200 2201 /* Insert name in all uppercase. */ 2202 for (p = namebuf; *p; p++) 2203 *p = TOUPPER (*p); 2204 2205 if (strncmp (namebuf, newname, namelen)) 2206 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2207 typeinfo.defined != 0 ? &typeinfo : NULL); 2208 2209 /* Insert name in all lowercase. */ 2210 for (p = namebuf; *p; p++) 2211 *p = TOLOWER (*p); 2212 2213 if (strncmp (namebuf, newname, namelen)) 2214 insert_neon_reg_alias (namebuf, basereg->number, basetype, 2215 typeinfo.defined != 0 ? &typeinfo : NULL); 2216 2217 return 1; 2218} 2219 2220/* Should never be called, as .req goes between the alias and the 2221 register name, not at the beginning of the line. */ 2222static void 2223s_req (int a ATTRIBUTE_UNUSED) 2224{ 2225 as_bad (_("invalid syntax for .req directive")); 2226} 2227 2228static void 2229s_dn (int a ATTRIBUTE_UNUSED) 2230{ 2231 as_bad (_("invalid syntax for .dn directive")); 2232} 2233 2234static void 2235s_qn (int a ATTRIBUTE_UNUSED) 2236{ 2237 as_bad (_("invalid syntax for .qn directive")); 2238} 2239 2240/* The .unreq directive deletes an alias which was previously defined 2241 by .req. For example: 2242 2243 my_alias .req r11 2244 .unreq my_alias */ 2245 2246static void 2247s_unreq (int a ATTRIBUTE_UNUSED) 2248{ 2249 char * name; 2250 char saved_char; 2251 2252 name = input_line_pointer; 2253 2254 while (*input_line_pointer != 0 2255 && *input_line_pointer != ' ' 2256 && *input_line_pointer != '\n') 2257 ++input_line_pointer; 2258 2259 saved_char = *input_line_pointer; 2260 *input_line_pointer = 0; 2261 2262 if (!*name) 2263 as_bad (_("invalid syntax for .unreq directive")); 2264 else 2265 { 2266 struct reg_entry *reg = hash_find (arm_reg_hsh, name); 2267 2268 if (!reg) 2269 as_bad (_("unknown register alias '%s'"), name); 2270 else if (reg->builtin) 2271 as_warn (_("ignoring attempt to undefine built-in register '%s'"), 2272 name); 2273 else 2274 { 2275 hash_delete (arm_reg_hsh, name); 2276 free ((char *) reg->name); 2277 if (reg->neon) 2278 free (reg->neon); 2279 free (reg); 2280 } 2281 } 2282 2283 *input_line_pointer = saved_char; 2284 demand_empty_rest_of_line (); 2285} 2286 2287static void 2288s_inst(int unused ATTRIBUTE_UNUSED) 2289{ 2290 expressionS exp; 2291 2292 if (thumb_mode) { 2293 as_bad(".inst not implemented for Thumb mode"); 2294 ignore_rest_of_line(); 2295 return; 2296 } 2297 2298 if (is_it_end_of_statement()) { 2299 demand_empty_rest_of_line(); 2300 return; 2301 } 2302 2303 do { 2304 expression(&exp); 2305 2306 if (exp.X_op != O_constant) 2307 as_bad("constant expression required"); 2308 else 2309 emit_expr(&exp, 4); 2310 2311 } while (*input_line_pointer++ == ','); 2312 2313 /* Put terminator back into stream. */ 2314 input_line_pointer--; 2315 demand_empty_rest_of_line(); 2316} 2317 2318/* Directives: Instruction set selection. */ 2319 2320#ifdef OBJ_ELF 2321/* This code is to handle mapping symbols as defined in the ARM ELF spec. 2322 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0). 2323 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag), 2324 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */ 2325 2326static enum mstate mapstate = MAP_UNDEFINED; 2327 2328void 2329mapping_state (enum mstate state) 2330{ 2331 symbolS * symbolP; 2332 const char * symname; 2333 int type; 2334 2335 if (mapstate == state) 2336 /* The mapping symbol has already been emitted. 2337 There is nothing else to do. */ 2338 return; 2339 2340 mapstate = state; 2341 2342 switch (state) 2343 { 2344 case MAP_DATA: 2345 symname = "$d"; 2346 type = BSF_NO_FLAGS; 2347 break; 2348 case MAP_ARM: 2349 symname = "$a"; 2350 type = BSF_NO_FLAGS; 2351 break; 2352 case MAP_THUMB: 2353 symname = "$t"; 2354 type = BSF_NO_FLAGS; 2355 break; 2356 case MAP_UNDEFINED: 2357 return; 2358 default: 2359 abort (); 2360 } 2361 2362 seg_info (now_seg)->tc_segment_info_data.mapstate = state; 2363 2364 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now); 2365 symbol_table_insert (symbolP); 2366 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; 2367 2368 switch (state) 2369 { 2370 case MAP_ARM: 2371 THUMB_SET_FUNC (symbolP, 0); 2372 ARM_SET_THUMB (symbolP, 0); 2373 ARM_SET_INTERWORK (symbolP, support_interwork); 2374 break; 2375 2376 case MAP_THUMB: 2377 THUMB_SET_FUNC (symbolP, 1); 2378 ARM_SET_THUMB (symbolP, 1); 2379 ARM_SET_INTERWORK (symbolP, support_interwork); 2380 break; 2381 2382 case MAP_DATA: 2383 default: 2384 return; 2385 } 2386} 2387#else 2388#define mapping_state(x) /* nothing */ 2389#endif 2390 2391/* Find the real, Thumb encoded start of a Thumb function. */ 2392 2393static symbolS * 2394find_real_start (symbolS * symbolP) 2395{ 2396 char * real_start; 2397 const char * name = S_GET_NAME (symbolP); 2398 symbolS * new_target; 2399 2400 /* This definition must agree with the one in gcc/config/arm/thumb.c. */ 2401#define STUB_NAME ".real_start_of" 2402 2403 if (name == NULL) 2404 abort (); 2405 2406 /* The compiler may generate BL instructions to local labels because 2407 it needs to perform a branch to a far away location. These labels 2408 do not have a corresponding ".real_start_of" label. We check 2409 both for S_IS_LOCAL and for a leading dot, to give a way to bypass 2410 the ".real_start_of" convention for nonlocal branches. */ 2411 if (S_IS_LOCAL (symbolP) || name[0] == '.') 2412 return symbolP; 2413 2414 real_start = ACONCAT ((STUB_NAME, name, NULL)); 2415 new_target = symbol_find (real_start); 2416 2417 if (new_target == NULL) 2418 { 2419 as_warn ("Failed to find real start of function: %s\n", name); 2420 new_target = symbolP; 2421 } 2422 2423 return new_target; 2424} 2425 2426static void 2427opcode_select (int width) 2428{ 2429 switch (width) 2430 { 2431 case 16: 2432 if (! thumb_mode) 2433 { 2434 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 2435 as_bad (_("selected processor does not support THUMB opcodes")); 2436 2437 thumb_mode = 1; 2438 /* No need to force the alignment, since we will have been 2439 coming from ARM mode, which is word-aligned. */ 2440 record_alignment (now_seg, 1); 2441 } 2442 mapping_state (MAP_THUMB); 2443 break; 2444 2445 case 32: 2446 if (thumb_mode) 2447 { 2448 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 2449 as_bad (_("selected processor does not support ARM opcodes")); 2450 2451 thumb_mode = 0; 2452 2453 if (!need_pass_2) 2454 frag_align (2, 0, 0); 2455 2456 record_alignment (now_seg, 1); 2457 } 2458 mapping_state (MAP_ARM); 2459 break; 2460 2461 default: 2462 as_bad (_("invalid instruction size selected (%d)"), width); 2463 } 2464} 2465 2466static void 2467s_arm (int ignore ATTRIBUTE_UNUSED) 2468{ 2469 opcode_select (32); 2470 demand_empty_rest_of_line (); 2471} 2472 2473static void 2474s_thumb (int ignore ATTRIBUTE_UNUSED) 2475{ 2476 opcode_select (16); 2477 demand_empty_rest_of_line (); 2478} 2479 2480static void 2481s_code (int unused ATTRIBUTE_UNUSED) 2482{ 2483 int temp; 2484 2485 temp = get_absolute_expression (); 2486 switch (temp) 2487 { 2488 case 16: 2489 case 32: 2490 opcode_select (temp); 2491 break; 2492 2493 default: 2494 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp); 2495 } 2496} 2497 2498static void 2499s_force_thumb (int ignore ATTRIBUTE_UNUSED) 2500{ 2501 /* If we are not already in thumb mode go into it, EVEN if 2502 the target processor does not support thumb instructions. 2503 This is used by gcc/config/arm/lib1funcs.asm for example 2504 to compile interworking support functions even if the 2505 target processor should not support interworking. */ 2506 if (! thumb_mode) 2507 { 2508 thumb_mode = 2; 2509 record_alignment (now_seg, 1); 2510 } 2511 2512 demand_empty_rest_of_line (); 2513} 2514 2515static void 2516s_thumb_func (int ignore ATTRIBUTE_UNUSED) 2517{ 2518 s_thumb (0); 2519 2520 /* The following label is the name/address of the start of a Thumb function. 2521 We need to know this for the interworking support. */ 2522 label_is_thumb_function_name = TRUE; 2523} 2524 2525/* Perform a .set directive, but also mark the alias as 2526 being a thumb function. */ 2527 2528static void 2529s_thumb_set (int equiv) 2530{ 2531 /* XXX the following is a duplicate of the code for s_set() in read.c 2532 We cannot just call that code as we need to get at the symbol that 2533 is created. */ 2534 char * name; 2535 char delim; 2536 char * end_name; 2537 symbolS * symbolP; 2538 2539 /* Especial apologies for the random logic: 2540 This just grew, and could be parsed much more simply! 2541 Dean - in haste. */ 2542 name = input_line_pointer; 2543 delim = get_symbol_end (); 2544 end_name = input_line_pointer; 2545 *end_name = delim; 2546 2547 if (*input_line_pointer != ',') 2548 { 2549 *end_name = 0; 2550 as_bad (_("expected comma after name \"%s\""), name); 2551 *end_name = delim; 2552 ignore_rest_of_line (); 2553 return; 2554 } 2555 2556 input_line_pointer++; 2557 *end_name = 0; 2558 2559 if (name[0] == '.' && name[1] == '\0') 2560 { 2561 /* XXX - this should not happen to .thumb_set. */ 2562 abort (); 2563 } 2564 2565 if ((symbolP = symbol_find (name)) == NULL 2566 && (symbolP = md_undefined_symbol (name)) == NULL) 2567 { 2568#ifndef NO_LISTING 2569 /* When doing symbol listings, play games with dummy fragments living 2570 outside the normal fragment chain to record the file and line info 2571 for this symbol. */ 2572 if (listing & LISTING_SYMBOLS) 2573 { 2574 extern struct list_info_struct * listing_tail; 2575 fragS * dummy_frag = xmalloc (sizeof (fragS)); 2576 2577 memset (dummy_frag, 0, sizeof (fragS)); 2578 dummy_frag->fr_type = rs_fill; 2579 dummy_frag->line = listing_tail; 2580 symbolP = symbol_new (name, undefined_section, 0, dummy_frag); 2581 dummy_frag->fr_symbol = symbolP; 2582 } 2583 else 2584#endif 2585 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); 2586 2587#ifdef OBJ_COFF 2588 /* "set" symbols are local unless otherwise specified. */ 2589 SF_SET_LOCAL (symbolP); 2590#endif /* OBJ_COFF */ 2591 } /* Make a new symbol. */ 2592 2593 symbol_table_insert (symbolP); 2594 2595 * end_name = delim; 2596 2597 if (equiv 2598 && S_IS_DEFINED (symbolP) 2599 && S_GET_SEGMENT (symbolP) != reg_section) 2600 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); 2601 2602 pseudo_set (symbolP); 2603 2604 demand_empty_rest_of_line (); 2605 2606 /* XXX Now we come to the Thumb specific bit of code. */ 2607 2608 THUMB_SET_FUNC (symbolP, 1); 2609 ARM_SET_THUMB (symbolP, 1); 2610#if defined OBJ_ELF || defined OBJ_COFF 2611 ARM_SET_INTERWORK (symbolP, support_interwork); 2612#endif 2613} 2614 2615/* Directives: Mode selection. */ 2616 2617/* .syntax [unified|divided] - choose the new unified syntax 2618 (same for Arm and Thumb encoding, modulo slight differences in what 2619 can be represented) or the old divergent syntax for each mode. */ 2620static void 2621s_syntax (int unused ATTRIBUTE_UNUSED) 2622{ 2623 char *name, delim; 2624 2625 name = input_line_pointer; 2626 delim = get_symbol_end (); 2627 2628 if (!strcasecmp (name, "unified")) 2629 unified_syntax = TRUE; 2630 else if (!strcasecmp (name, "divided")) 2631 unified_syntax = FALSE; 2632 else 2633 { 2634 as_bad (_("unrecognized syntax mode \"%s\""), name); 2635 return; 2636 } 2637 *input_line_pointer = delim; 2638 demand_empty_rest_of_line (); 2639} 2640 2641/* Directives: sectioning and alignment. */ 2642 2643/* Same as s_align_ptwo but align 0 => align 2. */ 2644 2645static void 2646s_align (int unused ATTRIBUTE_UNUSED) 2647{ 2648 int temp; 2649 bfd_boolean fill_p; 2650 long temp_fill; 2651 long max_alignment = 15; 2652 2653 temp = get_absolute_expression (); 2654 if (temp > max_alignment) 2655 as_bad (_("alignment too large: %d assumed"), temp = max_alignment); 2656 else if (temp < 0) 2657 { 2658 as_bad (_("alignment negative. 0 assumed.")); 2659 temp = 0; 2660 } 2661 2662 if (*input_line_pointer == ',') 2663 { 2664 input_line_pointer++; 2665 temp_fill = get_absolute_expression (); 2666 fill_p = TRUE; 2667 } 2668 else 2669 { 2670 fill_p = FALSE; 2671 temp_fill = 0; 2672 } 2673 2674 if (!temp) 2675 temp = 2; 2676 2677 /* Only make a frag if we HAVE to. */ 2678 if (temp && !need_pass_2) 2679 { 2680 if (!fill_p && subseg_text_p (now_seg)) 2681 frag_align_code (temp, 0); 2682 else 2683 frag_align (temp, (int) temp_fill, 0); 2684 } 2685 demand_empty_rest_of_line (); 2686 2687 record_alignment (now_seg, temp); 2688} 2689 2690static void 2691s_bss (int ignore ATTRIBUTE_UNUSED) 2692{ 2693 /* We don't support putting frags in the BSS segment, we fake it by 2694 marking in_bss, then looking at s_skip for clues. */ 2695 subseg_set (bss_section, 0); 2696 demand_empty_rest_of_line (); 2697 mapping_state (MAP_DATA); 2698} 2699 2700static void 2701s_even (int ignore ATTRIBUTE_UNUSED) 2702{ 2703 /* Never make frag if expect extra pass. */ 2704 if (!need_pass_2) 2705 frag_align (1, 0, 0); 2706 2707 record_alignment (now_seg, 1); 2708 2709 demand_empty_rest_of_line (); 2710} 2711 2712/* Directives: Literal pools. */ 2713 2714static literal_pool * 2715find_literal_pool (void) 2716{ 2717 literal_pool * pool; 2718 2719 for (pool = list_of_pools; pool != NULL; pool = pool->next) 2720 { 2721 if (pool->section == now_seg 2722 && pool->sub_section == now_subseg) 2723 break; 2724 } 2725 2726 return pool; 2727} 2728 2729static literal_pool * 2730find_or_make_literal_pool (void) 2731{ 2732 /* Next literal pool ID number. */ 2733 static unsigned int latest_pool_num = 1; 2734 literal_pool * pool; 2735 2736 pool = find_literal_pool (); 2737 2738 if (pool == NULL) 2739 { 2740 /* Create a new pool. */ 2741 pool = xmalloc (sizeof (* pool)); 2742 if (! pool) 2743 return NULL; 2744 2745 pool->next_free_entry = 0; 2746 pool->section = now_seg; 2747 pool->sub_section = now_subseg; 2748 pool->next = list_of_pools; 2749 pool->symbol = NULL; 2750 2751 /* Add it to the list. */ 2752 list_of_pools = pool; 2753 } 2754 2755 /* New pools, and emptied pools, will have a NULL symbol. */ 2756 if (pool->symbol == NULL) 2757 { 2758 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section, 2759 (valueT) 0, &zero_address_frag); 2760 pool->id = latest_pool_num ++; 2761 } 2762 2763 /* Done. */ 2764 return pool; 2765} 2766 2767/* Add the literal in the global 'inst' 2768 structure to the relevent literal pool. */ 2769 2770static int 2771add_to_lit_pool (void) 2772{ 2773 literal_pool * pool; 2774 unsigned int entry; 2775 2776 pool = find_or_make_literal_pool (); 2777 2778 /* Check if this literal value is already in the pool. */ 2779 for (entry = 0; entry < pool->next_free_entry; entry ++) 2780 { 2781 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2782 && (inst.reloc.exp.X_op == O_constant) 2783 && (pool->literals[entry].X_add_number 2784 == inst.reloc.exp.X_add_number) 2785 && (pool->literals[entry].X_unsigned 2786 == inst.reloc.exp.X_unsigned)) 2787 break; 2788 2789 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op) 2790 && (inst.reloc.exp.X_op == O_symbol) 2791 && (pool->literals[entry].X_add_number 2792 == inst.reloc.exp.X_add_number) 2793 && (pool->literals[entry].X_add_symbol 2794 == inst.reloc.exp.X_add_symbol) 2795 && (pool->literals[entry].X_op_symbol 2796 == inst.reloc.exp.X_op_symbol)) 2797 break; 2798 } 2799 2800 /* Do we need to create a new entry? */ 2801 if (entry == pool->next_free_entry) 2802 { 2803 if (entry >= MAX_LITERAL_POOL_SIZE) 2804 { 2805 inst.error = _("literal pool overflow"); 2806 return FAIL; 2807 } 2808 2809 pool->literals[entry] = inst.reloc.exp; 2810 pool->next_free_entry += 1; 2811 } 2812 2813 inst.reloc.exp.X_op = O_symbol; 2814 inst.reloc.exp.X_add_number = ((int) entry) * 4; 2815 inst.reloc.exp.X_add_symbol = pool->symbol; 2816 2817 return SUCCESS; 2818} 2819 2820/* Can't use symbol_new here, so have to create a symbol and then at 2821 a later date assign it a value. Thats what these functions do. */ 2822 2823static void 2824symbol_locate (symbolS * symbolP, 2825 const char * name, /* It is copied, the caller can modify. */ 2826 segT segment, /* Segment identifier (SEG_<something>). */ 2827 valueT valu, /* Symbol value. */ 2828 fragS * frag) /* Associated fragment. */ 2829{ 2830 unsigned int name_length; 2831 char * preserved_copy_of_name; 2832 2833 name_length = strlen (name) + 1; /* +1 for \0. */ 2834 obstack_grow (¬es, name, name_length); 2835 preserved_copy_of_name = obstack_finish (¬es); 2836 2837#ifdef tc_canonicalize_symbol_name 2838 preserved_copy_of_name = 2839 tc_canonicalize_symbol_name (preserved_copy_of_name); 2840#endif 2841 2842 S_SET_NAME (symbolP, preserved_copy_of_name); 2843 2844 S_SET_SEGMENT (symbolP, segment); 2845 S_SET_VALUE (symbolP, valu); 2846 symbol_clear_list_pointers (symbolP); 2847 2848 symbol_set_frag (symbolP, frag); 2849 2850 /* Link to end of symbol chain. */ 2851 { 2852 extern int symbol_table_frozen; 2853 2854 if (symbol_table_frozen) 2855 abort (); 2856 } 2857 2858 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP); 2859 2860 obj_symbol_new_hook (symbolP); 2861 2862#ifdef tc_symbol_new_hook 2863 tc_symbol_new_hook (symbolP); 2864#endif 2865 2866#ifdef DEBUG_SYMS 2867 verify_symbol_chain (symbol_rootP, symbol_lastP); 2868#endif /* DEBUG_SYMS */ 2869} 2870 2871 2872static void 2873s_ltorg (int ignored ATTRIBUTE_UNUSED) 2874{ 2875 unsigned int entry; 2876 literal_pool * pool; 2877 char sym_name[20]; 2878 2879 pool = find_literal_pool (); 2880 if (pool == NULL 2881 || pool->symbol == NULL 2882 || pool->next_free_entry == 0) 2883 return; 2884 2885 mapping_state (MAP_DATA); 2886 2887 /* Align pool as you have word accesses. 2888 Only make a frag if we have to. */ 2889 if (!need_pass_2) 2890 frag_align (2, 0, 0); 2891 2892 record_alignment (now_seg, 2); 2893 2894 sprintf (sym_name, "$$lit_\002%x", pool->id); 2895 2896 symbol_locate (pool->symbol, sym_name, now_seg, 2897 (valueT) frag_now_fix (), frag_now); 2898 symbol_table_insert (pool->symbol); 2899 2900 ARM_SET_THUMB (pool->symbol, thumb_mode); 2901 2902#if defined OBJ_COFF || defined OBJ_ELF 2903 ARM_SET_INTERWORK (pool->symbol, support_interwork); 2904#endif 2905 2906 for (entry = 0; entry < pool->next_free_entry; entry ++) 2907 /* First output the expression in the instruction to the pool. */ 2908 emit_expr (&(pool->literals[entry]), 4); /* .word */ 2909 2910 /* Mark the pool as empty. */ 2911 pool->next_free_entry = 0; 2912 pool->symbol = NULL; 2913} 2914 2915#ifdef OBJ_ELF 2916/* Forward declarations for functions below, in the MD interface 2917 section. */ 2918static void fix_new_arm (fragS *, int, short, expressionS *, int, int); 2919static valueT create_unwind_entry (int); 2920static void start_unwind_section (const segT, int); 2921static void add_unwind_opcode (valueT, int); 2922static void flush_pending_unwind (void); 2923 2924/* Directives: Data. */ 2925 2926static void 2927s_arm_elf_cons (int nbytes) 2928{ 2929 expressionS exp; 2930 2931#ifdef md_flush_pending_output 2932 md_flush_pending_output (); 2933#endif 2934 2935 if (is_it_end_of_statement ()) 2936 { 2937 demand_empty_rest_of_line (); 2938 return; 2939 } 2940 2941#ifdef md_cons_align 2942 md_cons_align (nbytes); 2943#endif 2944 2945 mapping_state (MAP_DATA); 2946 do 2947 { 2948 int reloc; 2949 char *base = input_line_pointer; 2950 2951 expression (& exp); 2952 2953 if (exp.X_op != O_symbol) 2954 emit_expr (&exp, (unsigned int) nbytes); 2955 else 2956 { 2957 char *before_reloc = input_line_pointer; 2958 reloc = parse_reloc (&input_line_pointer); 2959 if (reloc == -1) 2960 { 2961 as_bad (_("unrecognized relocation suffix")); 2962 ignore_rest_of_line (); 2963 return; 2964 } 2965 else if (reloc == BFD_RELOC_UNUSED) 2966 emit_expr (&exp, (unsigned int) nbytes); 2967 else 2968 { 2969 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); 2970 int size = bfd_get_reloc_size (howto); 2971 2972 if (reloc == BFD_RELOC_ARM_PLT32) 2973 { 2974 as_bad (_("(plt) is only valid on branch targets")); 2975 reloc = BFD_RELOC_UNUSED; 2976 size = 0; 2977 } 2978 2979 if (size > nbytes) 2980 as_bad (_("%s relocations do not fit in %d bytes"), 2981 howto->name, nbytes); 2982 else 2983 { 2984 /* We've parsed an expression stopping at O_symbol. 2985 But there may be more expression left now that we 2986 have parsed the relocation marker. Parse it again. 2987 XXX Surely there is a cleaner way to do this. */ 2988 char *p = input_line_pointer; 2989 int offset; 2990 char *save_buf = alloca (input_line_pointer - base); 2991 memcpy (save_buf, base, input_line_pointer - base); 2992 memmove (base + (input_line_pointer - before_reloc), 2993 base, before_reloc - base); 2994 2995 input_line_pointer = base + (input_line_pointer-before_reloc); 2996 expression (&exp); 2997 memcpy (base, save_buf, p - base); 2998 2999 offset = nbytes - size; 3000 p = frag_more ((int) nbytes); 3001 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, 3002 size, &exp, 0, reloc); 3003 } 3004 } 3005 } 3006 } 3007 while (*input_line_pointer++ == ','); 3008 3009 /* Put terminator back into stream. */ 3010 input_line_pointer --; 3011 demand_empty_rest_of_line (); 3012} 3013 3014 3015/* Parse a .rel31 directive. */ 3016 3017static void 3018s_arm_rel31 (int ignored ATTRIBUTE_UNUSED) 3019{ 3020 expressionS exp; 3021 char *p; 3022 valueT highbit; 3023 3024 highbit = 0; 3025 if (*input_line_pointer == '1') 3026 highbit = 0x80000000; 3027 else if (*input_line_pointer != '0') 3028 as_bad (_("expected 0 or 1")); 3029 3030 input_line_pointer++; 3031 if (*input_line_pointer != ',') 3032 as_bad (_("missing comma")); 3033 input_line_pointer++; 3034 3035#ifdef md_flush_pending_output 3036 md_flush_pending_output (); 3037#endif 3038 3039#ifdef md_cons_align 3040 md_cons_align (4); 3041#endif 3042 3043 mapping_state (MAP_DATA); 3044 3045 expression (&exp); 3046 3047 p = frag_more (4); 3048 md_number_to_chars (p, highbit, 4); 3049 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1, 3050 BFD_RELOC_ARM_PREL31); 3051 3052 demand_empty_rest_of_line (); 3053} 3054 3055/* Directives: AEABI stack-unwind tables. */ 3056 3057/* Parse an unwind_fnstart directive. Simply records the current location. */ 3058 3059static void 3060s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED) 3061{ 3062 demand_empty_rest_of_line (); 3063 /* Mark the start of the function. */ 3064 unwind.proc_start = expr_build_dot (); 3065 3066 /* Reset the rest of the unwind info. */ 3067 unwind.opcode_count = 0; 3068 unwind.table_entry = NULL; 3069 unwind.personality_routine = NULL; 3070 unwind.personality_index = -1; 3071 unwind.frame_size = 0; 3072 unwind.fp_offset = 0; 3073 unwind.fp_reg = 13; 3074 unwind.fp_used = 0; 3075 unwind.sp_restored = 0; 3076} 3077 3078 3079/* Parse a handlerdata directive. Creates the exception handling table entry 3080 for the function. */ 3081 3082static void 3083s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED) 3084{ 3085 demand_empty_rest_of_line (); 3086 if (unwind.table_entry) 3087 as_bad (_("dupicate .handlerdata directive")); 3088 3089 create_unwind_entry (1); 3090} 3091 3092/* Parse an unwind_fnend directive. Generates the index table entry. */ 3093 3094static void 3095s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED) 3096{ 3097 long where; 3098 char *ptr; 3099 valueT val; 3100 3101 demand_empty_rest_of_line (); 3102 3103 /* Add eh table entry. */ 3104 if (unwind.table_entry == NULL) 3105 val = create_unwind_entry (0); 3106 else 3107 val = 0; 3108 3109 /* Add index table entry. This is two words. */ 3110 start_unwind_section (unwind.saved_seg, 1); 3111 frag_align (2, 0, 0); 3112 record_alignment (now_seg, 2); 3113 3114 ptr = frag_more (8); 3115 memset(ptr, 0, 8); 3116 where = frag_now_fix () - 8; 3117 3118 /* Self relative offset of the function start. */ 3119 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1, 3120 BFD_RELOC_ARM_PREL31); 3121 3122 /* Indicate dependency on EHABI-defined personality routines to the 3123 linker, if it hasn't been done already. */ 3124 if (unwind.personality_index >= 0 && unwind.personality_index < 3 3125 && !(marked_pr_dependency & (1 << unwind.personality_index))) 3126 { 3127 static const char *const name[] = { 3128 "__aeabi_unwind_cpp_pr0", 3129 "__aeabi_unwind_cpp_pr1", 3130 "__aeabi_unwind_cpp_pr2" 3131 }; 3132 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]); 3133 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE); 3134 marked_pr_dependency |= 1 << unwind.personality_index; 3135 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency 3136 = marked_pr_dependency; 3137 } 3138 3139 if (val) 3140 /* Inline exception table entry. */ 3141 md_number_to_chars (ptr + 4, val, 4); 3142 else 3143 /* Self relative offset of the table entry. */ 3144 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1, 3145 BFD_RELOC_ARM_PREL31); 3146 3147 /* Restore the original section. */ 3148 subseg_set (unwind.saved_seg, unwind.saved_subseg); 3149} 3150 3151 3152/* Parse an unwind_cantunwind directive. */ 3153 3154static void 3155s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED) 3156{ 3157 demand_empty_rest_of_line (); 3158 if (unwind.personality_routine || unwind.personality_index != -1) 3159 as_bad (_("personality routine specified for cantunwind frame")); 3160 3161 unwind.personality_index = -2; 3162} 3163 3164 3165/* Parse a personalityindex directive. */ 3166 3167static void 3168s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED) 3169{ 3170 expressionS exp; 3171 3172 if (unwind.personality_routine || unwind.personality_index != -1) 3173 as_bad (_("duplicate .personalityindex directive")); 3174 3175 expression (&exp); 3176 3177 if (exp.X_op != O_constant 3178 || exp.X_add_number < 0 || exp.X_add_number > 15) 3179 { 3180 as_bad (_("bad personality routine number")); 3181 ignore_rest_of_line (); 3182 return; 3183 } 3184 3185 unwind.personality_index = exp.X_add_number; 3186 3187 demand_empty_rest_of_line (); 3188} 3189 3190 3191/* Parse a personality directive. */ 3192 3193static void 3194s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED) 3195{ 3196 char *name, *p, c; 3197 3198 if (unwind.personality_routine || unwind.personality_index != -1) 3199 as_bad (_("duplicate .personality directive")); 3200 3201 name = input_line_pointer; 3202 c = get_symbol_end (); 3203 p = input_line_pointer; 3204 unwind.personality_routine = symbol_find_or_make (name); 3205 *p = c; 3206 demand_empty_rest_of_line (); 3207} 3208 3209 3210/* Parse a directive saving core registers. */ 3211 3212static void 3213s_arm_unwind_save_core (void) 3214{ 3215 valueT op; 3216 long range; 3217 int n; 3218 3219 range = parse_reg_list (&input_line_pointer); 3220 if (range == FAIL) 3221 { 3222 as_bad (_("expected register list")); 3223 ignore_rest_of_line (); 3224 return; 3225 } 3226 3227 demand_empty_rest_of_line (); 3228 3229 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...} 3230 into .unwind_save {..., sp...}. We aren't bothered about the value of 3231 ip because it is clobbered by calls. */ 3232 if (unwind.sp_restored && unwind.fp_reg == 12 3233 && (range & 0x3000) == 0x1000) 3234 { 3235 unwind.opcode_count--; 3236 unwind.sp_restored = 0; 3237 range = (range | 0x2000) & ~0x1000; 3238 unwind.pending_offset = 0; 3239 } 3240 3241 /* Pop r4-r15. */ 3242 if (range & 0xfff0) 3243 { 3244 /* See if we can use the short opcodes. These pop a block of up to 8 3245 registers starting with r4, plus maybe r14. */ 3246 for (n = 0; n < 8; n++) 3247 { 3248 /* Break at the first non-saved register. */ 3249 if ((range & (1 << (n + 4))) == 0) 3250 break; 3251 } 3252 /* See if there are any other bits set. */ 3253 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0) 3254 { 3255 /* Use the long form. */ 3256 op = 0x8000 | ((range >> 4) & 0xfff); 3257 add_unwind_opcode (op, 2); 3258 } 3259 else 3260 { 3261 /* Use the short form. */ 3262 if (range & 0x4000) 3263 op = 0xa8; /* Pop r14. */ 3264 else 3265 op = 0xa0; /* Do not pop r14. */ 3266 op |= (n - 1); 3267 add_unwind_opcode (op, 1); 3268 } 3269 } 3270 3271 /* Pop r0-r3. */ 3272 if (range & 0xf) 3273 { 3274 op = 0xb100 | (range & 0xf); 3275 add_unwind_opcode (op, 2); 3276 } 3277 3278 /* Record the number of bytes pushed. */ 3279 for (n = 0; n < 16; n++) 3280 { 3281 if (range & (1 << n)) 3282 unwind.frame_size += 4; 3283 } 3284} 3285 3286 3287/* Parse a directive saving FPA registers. */ 3288 3289static void 3290s_arm_unwind_save_fpa (int reg) 3291{ 3292 expressionS exp; 3293 int num_regs; 3294 valueT op; 3295 3296 /* Get Number of registers to transfer. */ 3297 if (skip_past_comma (&input_line_pointer) != FAIL) 3298 expression (&exp); 3299 else 3300 exp.X_op = O_illegal; 3301 3302 if (exp.X_op != O_constant) 3303 { 3304 as_bad (_("expected , <constant>")); 3305 ignore_rest_of_line (); 3306 return; 3307 } 3308 3309 num_regs = exp.X_add_number; 3310 3311 if (num_regs < 1 || num_regs > 4) 3312 { 3313 as_bad (_("number of registers must be in the range [1:4]")); 3314 ignore_rest_of_line (); 3315 return; 3316 } 3317 3318 demand_empty_rest_of_line (); 3319 3320 if (reg == 4) 3321 { 3322 /* Short form. */ 3323 op = 0xb4 | (num_regs - 1); 3324 add_unwind_opcode (op, 1); 3325 } 3326 else 3327 { 3328 /* Long form. */ 3329 op = 0xc800 | (reg << 4) | (num_regs - 1); 3330 add_unwind_opcode (op, 2); 3331 } 3332 unwind.frame_size += num_regs * 12; 3333} 3334 3335 3336/* Parse a directive saving VFP registers for ARMv6 and above. */ 3337 3338static void 3339s_arm_unwind_save_vfp_armv6 (void) 3340{ 3341 int count; 3342 unsigned int start; 3343 valueT op; 3344 int num_vfpv3_regs = 0; 3345 int num_regs_below_16; 3346 3347 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D); 3348 if (count == FAIL) 3349 { 3350 as_bad (_("expected register list")); 3351 ignore_rest_of_line (); 3352 return; 3353 } 3354 3355 demand_empty_rest_of_line (); 3356 3357 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather 3358 than FSTMX/FLDMX-style ones). */ 3359 3360 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */ 3361 if (start >= 16) 3362 num_vfpv3_regs = count; 3363 else if (start + count > 16) 3364 num_vfpv3_regs = start + count - 16; 3365 3366 if (num_vfpv3_regs > 0) 3367 { 3368 int start_offset = start > 16 ? start - 16 : 0; 3369 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1); 3370 add_unwind_opcode (op, 2); 3371 } 3372 3373 /* Generate opcode for registers numbered in the range 0 .. 15. */ 3374 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count; 3375 assert (num_regs_below_16 + num_vfpv3_regs == count); 3376 if (num_regs_below_16 > 0) 3377 { 3378 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1); 3379 add_unwind_opcode (op, 2); 3380 } 3381 3382 unwind.frame_size += count * 8; 3383} 3384 3385 3386/* Parse a directive saving VFP registers for pre-ARMv6. */ 3387 3388static void 3389s_arm_unwind_save_vfp (void) 3390{ 3391 int count; 3392 unsigned int reg; 3393 valueT op; 3394 3395 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D); 3396 if (count == FAIL) 3397 { 3398 as_bad (_("expected register list")); 3399 ignore_rest_of_line (); 3400 return; 3401 } 3402 3403 demand_empty_rest_of_line (); 3404 3405 if (reg == 8) 3406 { 3407 /* Short form. */ 3408 op = 0xb8 | (count - 1); 3409 add_unwind_opcode (op, 1); 3410 } 3411 else 3412 { 3413 /* Long form. */ 3414 op = 0xb300 | (reg << 4) | (count - 1); 3415 add_unwind_opcode (op, 2); 3416 } 3417 unwind.frame_size += count * 8 + 4; 3418} 3419 3420 3421/* Parse a directive saving iWMMXt data registers. */ 3422 3423static void 3424s_arm_unwind_save_mmxwr (void) 3425{ 3426 int reg; 3427 int hi_reg; 3428 int i; 3429 unsigned mask = 0; 3430 valueT op; 3431 3432 if (*input_line_pointer == '{') 3433 input_line_pointer++; 3434 3435 do 3436 { 3437 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3438 3439 if (reg == FAIL) 3440 { 3441 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3442 goto error; 3443 } 3444 3445 if (mask >> reg) 3446 as_tsktsk (_("register list not in ascending order")); 3447 mask |= 1 << reg; 3448 3449 if (*input_line_pointer == '-') 3450 { 3451 input_line_pointer++; 3452 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR); 3453 if (hi_reg == FAIL) 3454 { 3455 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR])); 3456 goto error; 3457 } 3458 else if (reg >= hi_reg) 3459 { 3460 as_bad (_("bad register range")); 3461 goto error; 3462 } 3463 for (; reg < hi_reg; reg++) 3464 mask |= 1 << reg; 3465 } 3466 } 3467 while (skip_past_comma (&input_line_pointer) != FAIL); 3468 3469 if (*input_line_pointer == '}') 3470 input_line_pointer++; 3471 3472 demand_empty_rest_of_line (); 3473 3474 /* Generate any deferred opcodes because we're going to be looking at 3475 the list. */ 3476 flush_pending_unwind (); 3477 3478 for (i = 0; i < 16; i++) 3479 { 3480 if (mask & (1 << i)) 3481 unwind.frame_size += 8; 3482 } 3483 3484 /* Attempt to combine with a previous opcode. We do this because gcc 3485 likes to output separate unwind directives for a single block of 3486 registers. */ 3487 if (unwind.opcode_count > 0) 3488 { 3489 i = unwind.opcodes[unwind.opcode_count - 1]; 3490 if ((i & 0xf8) == 0xc0) 3491 { 3492 i &= 7; 3493 /* Only merge if the blocks are contiguous. */ 3494 if (i < 6) 3495 { 3496 if ((mask & 0xfe00) == (1 << 9)) 3497 { 3498 mask |= ((1 << (i + 11)) - 1) & 0xfc00; 3499 unwind.opcode_count--; 3500 } 3501 } 3502 else if (i == 6 && unwind.opcode_count >= 2) 3503 { 3504 i = unwind.opcodes[unwind.opcode_count - 2]; 3505 reg = i >> 4; 3506 i &= 0xf; 3507 3508 op = 0xffff << (reg - 1); 3509 if (reg > 0 3510 && ((mask & op) == (1u << (reg - 1)))) 3511 { 3512 op = (1 << (reg + i + 1)) - 1; 3513 op &= ~((1 << reg) - 1); 3514 mask |= op; 3515 unwind.opcode_count -= 2; 3516 } 3517 } 3518 } 3519 } 3520 3521 hi_reg = 15; 3522 /* We want to generate opcodes in the order the registers have been 3523 saved, ie. descending order. */ 3524 for (reg = 15; reg >= -1; reg--) 3525 { 3526 /* Save registers in blocks. */ 3527 if (reg < 0 3528 || !(mask & (1 << reg))) 3529 { 3530 /* We found an unsaved reg. Generate opcodes to save the 3531 preceeding block. */ 3532 if (reg != hi_reg) 3533 { 3534 if (reg == 9) 3535 { 3536 /* Short form. */ 3537 op = 0xc0 | (hi_reg - 10); 3538 add_unwind_opcode (op, 1); 3539 } 3540 else 3541 { 3542 /* Long form. */ 3543 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1); 3544 add_unwind_opcode (op, 2); 3545 } 3546 } 3547 hi_reg = reg - 1; 3548 } 3549 } 3550 3551 return; 3552error: 3553 ignore_rest_of_line (); 3554} 3555 3556static void 3557s_arm_unwind_save_mmxwcg (void) 3558{ 3559 int reg; 3560 int hi_reg; 3561 unsigned mask = 0; 3562 valueT op; 3563 3564 if (*input_line_pointer == '{') 3565 input_line_pointer++; 3566 3567 do 3568 { 3569 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3570 3571 if (reg == FAIL) 3572 { 3573 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3574 goto error; 3575 } 3576 3577 reg -= 8; 3578 if (mask >> reg) 3579 as_tsktsk (_("register list not in ascending order")); 3580 mask |= 1 << reg; 3581 3582 if (*input_line_pointer == '-') 3583 { 3584 input_line_pointer++; 3585 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG); 3586 if (hi_reg == FAIL) 3587 { 3588 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG])); 3589 goto error; 3590 } 3591 else if (reg >= hi_reg) 3592 { 3593 as_bad (_("bad register range")); 3594 goto error; 3595 } 3596 for (; reg < hi_reg; reg++) 3597 mask |= 1 << reg; 3598 } 3599 } 3600 while (skip_past_comma (&input_line_pointer) != FAIL); 3601 3602 if (*input_line_pointer == '}') 3603 input_line_pointer++; 3604 3605 demand_empty_rest_of_line (); 3606 3607 /* Generate any deferred opcodes because we're going to be looking at 3608 the list. */ 3609 flush_pending_unwind (); 3610 3611 for (reg = 0; reg < 16; reg++) 3612 { 3613 if (mask & (1 << reg)) 3614 unwind.frame_size += 4; 3615 } 3616 op = 0xc700 | mask; 3617 add_unwind_opcode (op, 2); 3618 return; 3619error: 3620 ignore_rest_of_line (); 3621} 3622 3623 3624/* Parse an unwind_save directive. 3625 If the argument is non-zero, this is a .vsave directive. */ 3626 3627static void 3628s_arm_unwind_save (int arch_v6) 3629{ 3630 char *peek; 3631 struct reg_entry *reg; 3632 bfd_boolean had_brace = FALSE; 3633 3634 /* Figure out what sort of save we have. */ 3635 peek = input_line_pointer; 3636 3637 if (*peek == '{') 3638 { 3639 had_brace = TRUE; 3640 peek++; 3641 } 3642 3643 reg = arm_reg_parse_multi (&peek); 3644 3645 if (!reg) 3646 { 3647 as_bad (_("register expected")); 3648 ignore_rest_of_line (); 3649 return; 3650 } 3651 3652 switch (reg->type) 3653 { 3654 case REG_TYPE_FN: 3655 if (had_brace) 3656 { 3657 as_bad (_("FPA .unwind_save does not take a register list")); 3658 ignore_rest_of_line (); 3659 return; 3660 } 3661 s_arm_unwind_save_fpa (reg->number); 3662 return; 3663 3664 case REG_TYPE_RN: s_arm_unwind_save_core (); return; 3665 case REG_TYPE_VFD: 3666 if (arch_v6) 3667 s_arm_unwind_save_vfp_armv6 (); 3668 else 3669 s_arm_unwind_save_vfp (); 3670 return; 3671 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; 3672 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; 3673 3674 default: 3675 as_bad (_(".unwind_save does not support this kind of register")); 3676 ignore_rest_of_line (); 3677 } 3678} 3679 3680 3681/* Parse an unwind_movsp directive. */ 3682 3683static void 3684s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED) 3685{ 3686 int reg; 3687 valueT op; 3688 int offset; 3689 3690 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3691 if (reg == FAIL) 3692 { 3693 as_bad (_(reg_expected_msgs[REG_TYPE_RN])); 3694 ignore_rest_of_line (); 3695 return; 3696 } 3697 3698 /* Optional constant. */ 3699 if (skip_past_comma (&input_line_pointer) != FAIL) 3700 { 3701 if (immediate_for_directive (&offset) == FAIL) 3702 return; 3703 } 3704 else 3705 offset = 0; 3706 3707 demand_empty_rest_of_line (); 3708 3709 if (reg == REG_SP || reg == REG_PC) 3710 { 3711 as_bad (_("SP and PC not permitted in .unwind_movsp directive")); 3712 return; 3713 } 3714 3715 if (unwind.fp_reg != REG_SP) 3716 as_bad (_("unexpected .unwind_movsp directive")); 3717 3718 /* Generate opcode to restore the value. */ 3719 op = 0x90 | reg; 3720 add_unwind_opcode (op, 1); 3721 3722 /* Record the information for later. */ 3723 unwind.fp_reg = reg; 3724 unwind.fp_offset = unwind.frame_size - offset; 3725 unwind.sp_restored = 1; 3726} 3727 3728/* Parse an unwind_pad directive. */ 3729 3730static void 3731s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED) 3732{ 3733 int offset; 3734 3735 if (immediate_for_directive (&offset) == FAIL) 3736 return; 3737 3738 if (offset & 3) 3739 { 3740 as_bad (_("stack increment must be multiple of 4")); 3741 ignore_rest_of_line (); 3742 return; 3743 } 3744 3745 /* Don't generate any opcodes, just record the details for later. */ 3746 unwind.frame_size += offset; 3747 unwind.pending_offset += offset; 3748 3749 demand_empty_rest_of_line (); 3750} 3751 3752/* Parse an unwind_setfp directive. */ 3753 3754static void 3755s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED) 3756{ 3757 int sp_reg; 3758 int fp_reg; 3759 int offset; 3760 3761 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3762 if (skip_past_comma (&input_line_pointer) == FAIL) 3763 sp_reg = FAIL; 3764 else 3765 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN); 3766 3767 if (fp_reg == FAIL || sp_reg == FAIL) 3768 { 3769 as_bad (_("expected <reg>, <reg>")); 3770 ignore_rest_of_line (); 3771 return; 3772 } 3773 3774 /* Optional constant. */ 3775 if (skip_past_comma (&input_line_pointer) != FAIL) 3776 { 3777 if (immediate_for_directive (&offset) == FAIL) 3778 return; 3779 } 3780 else 3781 offset = 0; 3782 3783 demand_empty_rest_of_line (); 3784 3785 if (sp_reg != 13 && sp_reg != unwind.fp_reg) 3786 { 3787 as_bad (_("register must be either sp or set by a previous" 3788 "unwind_movsp directive")); 3789 return; 3790 } 3791 3792 /* Don't generate any opcodes, just record the information for later. */ 3793 unwind.fp_reg = fp_reg; 3794 unwind.fp_used = 1; 3795 if (sp_reg == 13) 3796 unwind.fp_offset = unwind.frame_size - offset; 3797 else 3798 unwind.fp_offset -= offset; 3799} 3800 3801/* Parse an unwind_raw directive. */ 3802 3803static void 3804s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED) 3805{ 3806 expressionS exp; 3807 /* This is an arbitrary limit. */ 3808 unsigned char op[16]; 3809 int count; 3810 3811 expression (&exp); 3812 if (exp.X_op == O_constant 3813 && skip_past_comma (&input_line_pointer) != FAIL) 3814 { 3815 unwind.frame_size += exp.X_add_number; 3816 expression (&exp); 3817 } 3818 else 3819 exp.X_op = O_illegal; 3820 3821 if (exp.X_op != O_constant) 3822 { 3823 as_bad (_("expected <offset>, <opcode>")); 3824 ignore_rest_of_line (); 3825 return; 3826 } 3827 3828 count = 0; 3829 3830 /* Parse the opcode. */ 3831 for (;;) 3832 { 3833 if (count >= 16) 3834 { 3835 as_bad (_("unwind opcode too long")); 3836 ignore_rest_of_line (); 3837 } 3838 if (exp.X_op != O_constant || exp.X_add_number & ~0xff) 3839 { 3840 as_bad (_("invalid unwind opcode")); 3841 ignore_rest_of_line (); 3842 return; 3843 } 3844 op[count++] = exp.X_add_number; 3845 3846 /* Parse the next byte. */ 3847 if (skip_past_comma (&input_line_pointer) == FAIL) 3848 break; 3849 3850 expression (&exp); 3851 } 3852 3853 /* Add the opcode bytes in reverse order. */ 3854 while (count--) 3855 add_unwind_opcode (op[count], 1); 3856 3857 demand_empty_rest_of_line (); 3858} 3859 3860 3861/* Parse a .eabi_attribute directive. */ 3862 3863static void 3864s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED) 3865{ 3866 s_vendor_attribute (OBJ_ATTR_PROC); 3867} 3868#endif /* OBJ_ELF */ 3869 3870static void s_arm_arch (int); 3871static void s_arm_object_arch (int); 3872static void s_arm_cpu (int); 3873static void s_arm_fpu (int); 3874static void s_arm_arch_extension (int); 3875 3876#ifdef TE_PE 3877 3878static void 3879pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 3880{ 3881 expressionS exp; 3882 3883 do 3884 { 3885 expression (&exp); 3886 if (exp.X_op == O_symbol) 3887 exp.X_op = O_secrel; 3888 3889 emit_expr (&exp, 4); 3890 } 3891 while (*input_line_pointer++ == ','); 3892 3893 input_line_pointer--; 3894 demand_empty_rest_of_line (); 3895} 3896#endif /* TE_PE */ 3897 3898/* This table describes all the machine specific pseudo-ops the assembler 3899 has to support. The fields are: 3900 pseudo-op name without dot 3901 function to call to execute this pseudo-op 3902 Integer arg to pass to the function. */ 3903 3904const pseudo_typeS md_pseudo_table[] = 3905{ 3906 /* Never called because '.req' does not start a line. */ 3907 { "req", s_req, 0 }, 3908 /* Following two are likewise never called. */ 3909 { "dn", s_dn, 0 }, 3910 { "qn", s_qn, 0 }, 3911 { "unreq", s_unreq, 0 }, 3912 { "bss", s_bss, 0 }, 3913 { "align", s_align, 0 }, 3914 { "arm", s_arm, 0 }, 3915 { "thumb", s_thumb, 0 }, 3916 { "code", s_code, 0 }, 3917 { "force_thumb", s_force_thumb, 0 }, 3918 { "thumb_func", s_thumb_func, 0 }, 3919 { "thumb_set", s_thumb_set, 0 }, 3920 { "even", s_even, 0 }, 3921 { "ltorg", s_ltorg, 0 }, 3922 { "pool", s_ltorg, 0 }, 3923 { "syntax", s_syntax, 0 }, 3924 { "cpu", s_arm_cpu, 0 }, 3925 { "arch", s_arm_arch, 0 }, 3926 { "object_arch", s_arm_object_arch, 0 }, 3927 { "fpu", s_arm_fpu, 0 }, 3928 { "arch_extension", s_arm_arch_extension, 0 }, 3929 { "inst", s_inst, 0 }, 3930#ifdef OBJ_ELF 3931 { "word", s_arm_elf_cons, 4 }, 3932 { "long", s_arm_elf_cons, 4 }, 3933 { "rel31", s_arm_rel31, 0 }, 3934 { "fnstart", s_arm_unwind_fnstart, 0 }, 3935 { "fnend", s_arm_unwind_fnend, 0 }, 3936 { "cantunwind", s_arm_unwind_cantunwind, 0 }, 3937 { "personality", s_arm_unwind_personality, 0 }, 3938 { "personalityindex", s_arm_unwind_personalityindex, 0 }, 3939 { "handlerdata", s_arm_unwind_handlerdata, 0 }, 3940 { "save", s_arm_unwind_save, 0 }, 3941 { "vsave", s_arm_unwind_save, 1 }, 3942 { "movsp", s_arm_unwind_movsp, 0 }, 3943 { "pad", s_arm_unwind_pad, 0 }, 3944 { "setfp", s_arm_unwind_setfp, 0 }, 3945 { "unwind_raw", s_arm_unwind_raw, 0 }, 3946 { "eabi_attribute", s_arm_eabi_attribute, 0 }, 3947#else 3948 { "word", cons, 4}, 3949 3950 /* These are used for dwarf. */ 3951 {"2byte", cons, 2}, 3952 {"4byte", cons, 4}, 3953 {"8byte", cons, 8}, 3954 /* These are used for dwarf2. */ 3955 { "file", (void (*) (int)) dwarf2_directive_file, 0 }, 3956 { "loc", dwarf2_directive_loc, 0 }, 3957 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 }, 3958#endif 3959 { "extend", float_cons, 'x' }, 3960 { "ldouble", float_cons, 'x' }, 3961 { "packed", float_cons, 'p' }, 3962#ifdef TE_PE 3963 {"secrel32", pe_directive_secrel, 0}, 3964#endif 3965 { 0, 0, 0 } 3966}; 3967 3968/* Parser functions used exclusively in instruction operands. */ 3969 3970/* Generic immediate-value read function for use in insn parsing. 3971 STR points to the beginning of the immediate (the leading #); 3972 VAL receives the value; if the value is outside [MIN, MAX] 3973 issue an error. PREFIX_OPT is true if the immediate prefix is 3974 optional. */ 3975 3976static int 3977parse_immediate (char **str, int *val, int min, int max, 3978 bfd_boolean prefix_opt) 3979{ 3980 expressionS exp; 3981 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX); 3982 if (exp.X_op != O_constant) 3983 { 3984 inst.error = _("constant expression required"); 3985 return FAIL; 3986 } 3987 3988 if (exp.X_add_number < min || exp.X_add_number > max) 3989 { 3990 inst.error = _("immediate value out of range"); 3991 return FAIL; 3992 } 3993 3994 *val = exp.X_add_number; 3995 return SUCCESS; 3996} 3997 3998/* Less-generic immediate-value read function with the possibility of loading a 3999 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate 4000 instructions. Puts the result directly in inst.operands[i]. */ 4001 4002static int 4003parse_big_immediate (char **str, int i) 4004{ 4005 expressionS exp; 4006 char *ptr = *str; 4007 4008 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG); 4009 4010 if (exp.X_op == O_constant) 4011 { 4012 inst.operands[i].imm = exp.X_add_number & 0xffffffff; 4013 /* If we're on a 64-bit host, then a 64-bit number can be returned using 4014 O_constant. We have to be careful not to break compilation for 4015 32-bit X_add_number, though. */ 4016 if ((exp.X_add_number & ~0xffffffffl) != 0) 4017 { 4018 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */ 4019 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff; 4020 inst.operands[i].regisimm = 1; 4021 } 4022 } 4023 else if (exp.X_op == O_big 4024 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32 4025 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64) 4026 { 4027 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0; 4028 /* Bignums have their least significant bits in 4029 generic_bignum[0]. Make sure we put 32 bits in imm and 4030 32 bits in reg, in a (hopefully) portable way. */ 4031 assert (parts != 0); 4032 inst.operands[i].imm = 0; 4033 for (j = 0; j < parts; j++, idx++) 4034 inst.operands[i].imm |= generic_bignum[idx] 4035 << (LITTLENUM_NUMBER_OF_BITS * j); 4036 inst.operands[i].reg = 0; 4037 for (j = 0; j < parts; j++, idx++) 4038 inst.operands[i].reg |= generic_bignum[idx] 4039 << (LITTLENUM_NUMBER_OF_BITS * j); 4040 inst.operands[i].regisimm = 1; 4041 } 4042 else 4043 return FAIL; 4044 4045 *str = ptr; 4046 4047 return SUCCESS; 4048} 4049 4050/* Returns the pseudo-register number of an FPA immediate constant, 4051 or FAIL if there isn't a valid constant here. */ 4052 4053static int 4054parse_fpa_immediate (char ** str) 4055{ 4056 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4057 char * save_in; 4058 expressionS exp; 4059 int i; 4060 int j; 4061 4062 /* First try and match exact strings, this is to guarantee 4063 that some formats will work even for cross assembly. */ 4064 4065 for (i = 0; fp_const[i]; i++) 4066 { 4067 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0) 4068 { 4069 char *start = *str; 4070 4071 *str += strlen (fp_const[i]); 4072 if (is_end_of_line[(unsigned char) **str]) 4073 return i + 8; 4074 *str = start; 4075 } 4076 } 4077 4078 /* Just because we didn't get a match doesn't mean that the constant 4079 isn't valid, just that it is in a format that we don't 4080 automatically recognize. Try parsing it with the standard 4081 expression routines. */ 4082 4083 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE)); 4084 4085 /* Look for a raw floating point number. */ 4086 if ((save_in = atof_ieee (*str, 'x', words)) != NULL 4087 && is_end_of_line[(unsigned char) *save_in]) 4088 { 4089 for (i = 0; i < NUM_FLOAT_VALS; i++) 4090 { 4091 for (j = 0; j < MAX_LITTLENUMS; j++) 4092 { 4093 if (words[j] != fp_values[i][j]) 4094 break; 4095 } 4096 4097 if (j == MAX_LITTLENUMS) 4098 { 4099 *str = save_in; 4100 return i + 8; 4101 } 4102 } 4103 } 4104 4105 /* Try and parse a more complex expression, this will probably fail 4106 unless the code uses a floating point prefix (eg "0f"). */ 4107 save_in = input_line_pointer; 4108 input_line_pointer = *str; 4109 if (expression (&exp) == absolute_section 4110 && exp.X_op == O_big 4111 && exp.X_add_number < 0) 4112 { 4113 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it. 4114 Ditto for 15. */ 4115 if (gen_to_words (words, 5, (long) 15) == 0) 4116 { 4117 for (i = 0; i < NUM_FLOAT_VALS; i++) 4118 { 4119 for (j = 0; j < MAX_LITTLENUMS; j++) 4120 { 4121 if (words[j] != fp_values[i][j]) 4122 break; 4123 } 4124 4125 if (j == MAX_LITTLENUMS) 4126 { 4127 *str = input_line_pointer; 4128 input_line_pointer = save_in; 4129 return i + 8; 4130 } 4131 } 4132 } 4133 } 4134 4135 *str = input_line_pointer; 4136 input_line_pointer = save_in; 4137 inst.error = _("invalid FPA immediate expression"); 4138 return FAIL; 4139} 4140 4141/* Returns 1 if a number has "quarter-precision" float format 4142 0baBbbbbbc defgh000 00000000 00000000. */ 4143 4144static int 4145is_quarter_float (unsigned imm) 4146{ 4147 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000; 4148 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0; 4149} 4150 4151/* Parse an 8-bit "quarter-precision" floating point number of the form: 4152 0baBbbbbbc defgh000 00000000 00000000. 4153 The zero and minus-zero cases need special handling, since they can't be 4154 encoded in the "quarter-precision" float format, but can nonetheless be 4155 loaded as integer constants. */ 4156 4157static unsigned 4158parse_qfloat_immediate (char **ccp, int *immed) 4159{ 4160 char *str = *ccp; 4161 char *fpnum; 4162 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4163 int found_fpchar = 0; 4164 4165 skip_past_char (&str, '#'); 4166 4167 /* We must not accidentally parse an integer as a floating-point number. Make 4168 sure that the value we parse is not an integer by checking for special 4169 characters '.' or 'e'. 4170 FIXME: This is a horrible hack, but doing better is tricky because type 4171 information isn't in a very usable state at parse time. */ 4172 fpnum = str; 4173 skip_whitespace (fpnum); 4174 4175 if (strncmp (fpnum, "0x", 2) == 0) 4176 return FAIL; 4177 else 4178 { 4179 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++) 4180 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E') 4181 { 4182 found_fpchar = 1; 4183 break; 4184 } 4185 4186 if (!found_fpchar) 4187 return FAIL; 4188 } 4189 4190 if ((str = atof_ieee (str, 's', words)) != NULL) 4191 { 4192 unsigned fpword = 0; 4193 int i; 4194 4195 /* Our FP word must be 32 bits (single-precision FP). */ 4196 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++) 4197 { 4198 fpword <<= LITTLENUM_NUMBER_OF_BITS; 4199 fpword |= words[i]; 4200 } 4201 4202 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0) 4203 *immed = fpword; 4204 else 4205 return FAIL; 4206 4207 *ccp = str; 4208 4209 return SUCCESS; 4210 } 4211 4212 return FAIL; 4213} 4214 4215/* Shift operands. */ 4216enum shift_kind 4217{ 4218 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX 4219}; 4220 4221struct asm_shift_name 4222{ 4223 const char *name; 4224 enum shift_kind kind; 4225}; 4226 4227/* Third argument to parse_shift. */ 4228enum parse_shift_mode 4229{ 4230 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */ 4231 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */ 4232 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */ 4233 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */ 4234 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */ 4235}; 4236 4237/* Parse a <shift> specifier on an ARM data processing instruction. 4238 This has three forms: 4239 4240 (LSL|LSR|ASL|ASR|ROR) Rs 4241 (LSL|LSR|ASL|ASR|ROR) #imm 4242 RRX 4243 4244 Note that ASL is assimilated to LSL in the instruction encoding, and 4245 RRX to ROR #0 (which cannot be written as such). */ 4246 4247static int 4248parse_shift (char **str, int i, enum parse_shift_mode mode) 4249{ 4250 const struct asm_shift_name *shift_name; 4251 enum shift_kind shift; 4252 char *s = *str; 4253 char *p = s; 4254 int reg; 4255 4256 for (p = *str; ISALPHA (*p); p++) 4257 ; 4258 4259 if (p == *str) 4260 { 4261 inst.error = _("shift expression expected"); 4262 return FAIL; 4263 } 4264 4265 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str); 4266 4267 if (shift_name == NULL) 4268 { 4269 inst.error = _("shift expression expected"); 4270 return FAIL; 4271 } 4272 4273 shift = shift_name->kind; 4274 4275 switch (mode) 4276 { 4277 case NO_SHIFT_RESTRICT: 4278 case SHIFT_IMMEDIATE: break; 4279 4280 case SHIFT_LSL_OR_ASR_IMMEDIATE: 4281 if (shift != SHIFT_LSL && shift != SHIFT_ASR) 4282 { 4283 inst.error = _("'LSL' or 'ASR' required"); 4284 return FAIL; 4285 } 4286 break; 4287 4288 case SHIFT_LSL_IMMEDIATE: 4289 if (shift != SHIFT_LSL) 4290 { 4291 inst.error = _("'LSL' required"); 4292 return FAIL; 4293 } 4294 break; 4295 4296 case SHIFT_ASR_IMMEDIATE: 4297 if (shift != SHIFT_ASR) 4298 { 4299 inst.error = _("'ASR' required"); 4300 return FAIL; 4301 } 4302 break; 4303 4304 default: abort (); 4305 } 4306 4307 if (shift != SHIFT_RRX) 4308 { 4309 /* Whitespace can appear here if the next thing is a bare digit. */ 4310 skip_whitespace (p); 4311 4312 if (mode == NO_SHIFT_RESTRICT 4313 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4314 { 4315 inst.operands[i].imm = reg; 4316 inst.operands[i].immisreg = 1; 4317 } 4318 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4319 return FAIL; 4320 } 4321 inst.operands[i].shift_kind = shift; 4322 inst.operands[i].shifted = 1; 4323 *str = p; 4324 return SUCCESS; 4325} 4326 4327/* Parse a <shifter_operand> for an ARM data processing instruction: 4328 4329 #<immediate> 4330 #<immediate>, <rotate> 4331 <Rm> 4332 <Rm>, <shift> 4333 4334 where <shift> is defined by parse_shift above, and <rotate> is a 4335 multiple of 2 between 0 and 30. Validation of immediate operands 4336 is deferred to md_apply_fix. */ 4337 4338static int 4339parse_shifter_operand (char **str, int i) 4340{ 4341 int value; 4342 expressionS expr; 4343 4344 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL) 4345 { 4346 inst.operands[i].reg = value; 4347 inst.operands[i].isreg = 1; 4348 4349 /* parse_shift will override this if appropriate */ 4350 inst.reloc.exp.X_op = O_constant; 4351 inst.reloc.exp.X_add_number = 0; 4352 4353 if (skip_past_comma (str) == FAIL) 4354 return SUCCESS; 4355 4356 /* Shift operation on register. */ 4357 return parse_shift (str, i, NO_SHIFT_RESTRICT); 4358 } 4359 4360 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX)) 4361 return FAIL; 4362 4363 if (skip_past_comma (str) == SUCCESS) 4364 { 4365 /* #x, y -- ie explicit rotation by Y. */ 4366 if (my_get_expression (&expr, str, GE_NO_PREFIX)) 4367 return FAIL; 4368 4369 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant) 4370 { 4371 inst.error = _("constant expression expected"); 4372 return FAIL; 4373 } 4374 4375 value = expr.X_add_number; 4376 if (value < 0 || value > 30 || value % 2 != 0) 4377 { 4378 inst.error = _("invalid rotation"); 4379 return FAIL; 4380 } 4381 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255) 4382 { 4383 inst.error = _("invalid constant"); 4384 return FAIL; 4385 } 4386 4387 /* Convert to decoded value. md_apply_fix will put it back. */ 4388 inst.reloc.exp.X_add_number 4389 = (((inst.reloc.exp.X_add_number << (32 - value)) 4390 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff); 4391 } 4392 4393 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 4394 inst.reloc.pc_rel = 0; 4395 return SUCCESS; 4396} 4397 4398/* Group relocation information. Each entry in the table contains the 4399 textual name of the relocation as may appear in assembler source 4400 and must end with a colon. 4401 Along with this textual name are the relocation codes to be used if 4402 the corresponding instruction is an ALU instruction (ADD or SUB only), 4403 an LDR, an LDRS, or an LDC. */ 4404 4405struct group_reloc_table_entry 4406{ 4407 const char *name; 4408 int alu_code; 4409 int ldr_code; 4410 int ldrs_code; 4411 int ldc_code; 4412}; 4413 4414typedef enum 4415{ 4416 /* Varieties of non-ALU group relocation. */ 4417 4418 GROUP_LDR, 4419 GROUP_LDRS, 4420 GROUP_LDC 4421} group_reloc_type; 4422 4423static struct group_reloc_table_entry group_reloc_table[] = 4424 { /* Program counter relative: */ 4425 { "pc_g0_nc", 4426 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */ 4427 0, /* LDR */ 4428 0, /* LDRS */ 4429 0 }, /* LDC */ 4430 { "pc_g0", 4431 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */ 4432 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */ 4433 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */ 4434 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */ 4435 { "pc_g1_nc", 4436 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */ 4437 0, /* LDR */ 4438 0, /* LDRS */ 4439 0 }, /* LDC */ 4440 { "pc_g1", 4441 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */ 4442 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */ 4443 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */ 4444 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */ 4445 { "pc_g2", 4446 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */ 4447 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */ 4448 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */ 4449 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */ 4450 /* Section base relative */ 4451 { "sb_g0_nc", 4452 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */ 4453 0, /* LDR */ 4454 0, /* LDRS */ 4455 0 }, /* LDC */ 4456 { "sb_g0", 4457 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */ 4458 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */ 4459 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */ 4460 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */ 4461 { "sb_g1_nc", 4462 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */ 4463 0, /* LDR */ 4464 0, /* LDRS */ 4465 0 }, /* LDC */ 4466 { "sb_g1", 4467 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */ 4468 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */ 4469 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */ 4470 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */ 4471 { "sb_g2", 4472 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */ 4473 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */ 4474 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */ 4475 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */ 4476 4477/* Given the address of a pointer pointing to the textual name of a group 4478 relocation as may appear in assembler source, attempt to find its details 4479 in group_reloc_table. The pointer will be updated to the character after 4480 the trailing colon. On failure, FAIL will be returned; SUCCESS 4481 otherwise. On success, *entry will be updated to point at the relevant 4482 group_reloc_table entry. */ 4483 4484static int 4485find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out) 4486{ 4487 unsigned int i; 4488 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++) 4489 { 4490 int length = strlen (group_reloc_table[i].name); 4491 4492 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 && 4493 (*str)[length] == ':') 4494 { 4495 *out = &group_reloc_table[i]; 4496 *str += (length + 1); 4497 return SUCCESS; 4498 } 4499 } 4500 4501 return FAIL; 4502} 4503 4504/* Parse a <shifter_operand> for an ARM data processing instruction 4505 (as for parse_shifter_operand) where group relocations are allowed: 4506 4507 #<immediate> 4508 #<immediate>, <rotate> 4509 #:<group_reloc>:<expression> 4510 <Rm> 4511 <Rm>, <shift> 4512 4513 where <group_reloc> is one of the strings defined in group_reloc_table. 4514 The hashes are optional. 4515 4516 Everything else is as for parse_shifter_operand. */ 4517 4518static parse_operand_result 4519parse_shifter_operand_group_reloc (char **str, int i) 4520{ 4521 /* Determine if we have the sequence of characters #: or just : 4522 coming next. If we do, then we check for a group relocation. 4523 If we don't, punt the whole lot to parse_shifter_operand. */ 4524 4525 if (((*str)[0] == '#' && (*str)[1] == ':') 4526 || (*str)[0] == ':') 4527 { 4528 struct group_reloc_table_entry *entry; 4529 4530 if ((*str)[0] == '#') 4531 (*str) += 2; 4532 else 4533 (*str)++; 4534 4535 /* Try to parse a group relocation. Anything else is an error. */ 4536 if (find_group_reloc_table_entry (str, &entry) == FAIL) 4537 { 4538 inst.error = _("unknown group relocation"); 4539 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4540 } 4541 4542 /* We now have the group relocation table entry corresponding to 4543 the name in the assembler source. Next, we parse the expression. */ 4544 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX)) 4545 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4546 4547 /* Record the relocation type (always the ALU variant here). */ 4548 inst.reloc.type = entry->alu_code; 4549 assert (inst.reloc.type != 0); 4550 4551 return PARSE_OPERAND_SUCCESS; 4552 } 4553 else 4554 return parse_shifter_operand (str, i) == SUCCESS 4555 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL; 4556 4557 /* Never reached. */ 4558} 4559 4560/* Parse all forms of an ARM address expression. Information is written 4561 to inst.operands[i] and/or inst.reloc. 4562 4563 Preindexed addressing (.preind=1): 4564 4565 [Rn, #offset] .reg=Rn .reloc.exp=offset 4566 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4567 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4568 .shift_kind=shift .reloc.exp=shift_imm 4569 4570 These three may have a trailing ! which causes .writeback to be set also. 4571 4572 Postindexed addressing (.postind=1, .writeback=1): 4573 4574 [Rn], #offset .reg=Rn .reloc.exp=offset 4575 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4576 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1 4577 .shift_kind=shift .reloc.exp=shift_imm 4578 4579 Unindexed addressing (.preind=0, .postind=0): 4580 4581 [Rn], {option} .reg=Rn .imm=option .immisreg=0 4582 4583 Other: 4584 4585 [Rn]{!} shorthand for [Rn,#0]{!} 4586 =immediate .isreg=0 .reloc.exp=immediate 4587 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label 4588 4589 It is the caller's responsibility to check for addressing modes not 4590 supported by the instruction, and to set inst.reloc.type. */ 4591 4592static parse_operand_result 4593parse_address_main (char **str, int i, int group_relocations, 4594 group_reloc_type group_type) 4595{ 4596 char *p = *str; 4597 int reg; 4598 4599 if (skip_past_char (&p, '[') == FAIL) 4600 { 4601 if (skip_past_char (&p, '=') == FAIL) 4602 { 4603 /* bare address - translate to PC-relative offset */ 4604 inst.reloc.pc_rel = 1; 4605 inst.operands[i].reg = REG_PC; 4606 inst.operands[i].isreg = 1; 4607 inst.operands[i].preind = 1; 4608 } 4609 /* else a load-constant pseudo op, no special treatment needed here */ 4610 4611 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4612 return PARSE_OPERAND_FAIL; 4613 4614 *str = p; 4615 return PARSE_OPERAND_SUCCESS; 4616 } 4617 4618 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 4619 { 4620 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 4621 return PARSE_OPERAND_FAIL; 4622 } 4623 inst.operands[i].reg = reg; 4624 inst.operands[i].isreg = 1; 4625 4626 if (skip_past_comma (&p) == SUCCESS) 4627 { 4628 inst.operands[i].preind = 1; 4629 4630 if (*p == '+') p++; 4631 else if (*p == '-') p++, inst.operands[i].negative = 1; 4632 4633 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4634 { 4635 inst.operands[i].imm = reg; 4636 inst.operands[i].immisreg = 1; 4637 4638 if (skip_past_comma (&p) == SUCCESS) 4639 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4640 return PARSE_OPERAND_FAIL; 4641 } 4642 else if (skip_past_char (&p, ':') == SUCCESS) 4643 { 4644 /* FIXME: '@' should be used here, but it's filtered out by generic 4645 code before we get to see it here. This may be subject to 4646 change. */ 4647 expressionS exp; 4648 my_get_expression (&exp, &p, GE_NO_PREFIX); 4649 if (exp.X_op != O_constant) 4650 { 4651 inst.error = _("alignment must be constant"); 4652 return PARSE_OPERAND_FAIL; 4653 } 4654 inst.operands[i].imm = exp.X_add_number << 8; 4655 inst.operands[i].immisalign = 1; 4656 /* Alignments are not pre-indexes. */ 4657 inst.operands[i].preind = 0; 4658 } 4659 else 4660 { 4661 if (inst.operands[i].negative) 4662 { 4663 inst.operands[i].negative = 0; 4664 p--; 4665 } 4666 4667 if (group_relocations && 4668 ((*p == '#' && *(p + 1) == ':') || *p == ':')) 4669 4670 { 4671 struct group_reloc_table_entry *entry; 4672 4673 /* Skip over the #: or : sequence. */ 4674 if (*p == '#') 4675 p += 2; 4676 else 4677 p++; 4678 4679 /* Try to parse a group relocation. Anything else is an 4680 error. */ 4681 if (find_group_reloc_table_entry (&p, &entry) == FAIL) 4682 { 4683 inst.error = _("unknown group relocation"); 4684 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4685 } 4686 4687 /* We now have the group relocation table entry corresponding to 4688 the name in the assembler source. Next, we parse the 4689 expression. */ 4690 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4691 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4692 4693 /* Record the relocation type. */ 4694 switch (group_type) 4695 { 4696 case GROUP_LDR: 4697 inst.reloc.type = entry->ldr_code; 4698 break; 4699 4700 case GROUP_LDRS: 4701 inst.reloc.type = entry->ldrs_code; 4702 break; 4703 4704 case GROUP_LDC: 4705 inst.reloc.type = entry->ldc_code; 4706 break; 4707 4708 default: 4709 assert (0); 4710 } 4711 4712 if (inst.reloc.type == 0) 4713 { 4714 inst.error = _("this group relocation is not allowed on this instruction"); 4715 return PARSE_OPERAND_FAIL_NO_BACKTRACK; 4716 } 4717 } 4718 else 4719 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4720 return PARSE_OPERAND_FAIL; 4721 } 4722 } 4723 4724 if (skip_past_char (&p, ']') == FAIL) 4725 { 4726 inst.error = _("']' expected"); 4727 return PARSE_OPERAND_FAIL; 4728 } 4729 4730 if (skip_past_char (&p, '!') == SUCCESS) 4731 inst.operands[i].writeback = 1; 4732 4733 else if (skip_past_comma (&p) == SUCCESS) 4734 { 4735 if (skip_past_char (&p, '{') == SUCCESS) 4736 { 4737 /* [Rn], {expr} - unindexed, with option */ 4738 if (parse_immediate (&p, &inst.operands[i].imm, 4739 0, 255, TRUE) == FAIL) 4740 return PARSE_OPERAND_FAIL; 4741 4742 if (skip_past_char (&p, '}') == FAIL) 4743 { 4744 inst.error = _("'}' expected at end of 'option' field"); 4745 return PARSE_OPERAND_FAIL; 4746 } 4747 if (inst.operands[i].preind) 4748 { 4749 inst.error = _("cannot combine index with option"); 4750 return PARSE_OPERAND_FAIL; 4751 } 4752 *str = p; 4753 return PARSE_OPERAND_SUCCESS; 4754 } 4755 else 4756 { 4757 inst.operands[i].postind = 1; 4758 inst.operands[i].writeback = 1; 4759 4760 if (inst.operands[i].preind) 4761 { 4762 inst.error = _("cannot combine pre- and post-indexing"); 4763 return PARSE_OPERAND_FAIL; 4764 } 4765 4766 if (*p == '+') p++; 4767 else if (*p == '-') p++, inst.operands[i].negative = 1; 4768 4769 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL) 4770 { 4771 /* We might be using the immediate for alignment already. If we 4772 are, OR the register number into the low-order bits. */ 4773 if (inst.operands[i].immisalign) 4774 inst.operands[i].imm |= reg; 4775 else 4776 inst.operands[i].imm = reg; 4777 inst.operands[i].immisreg = 1; 4778 4779 if (skip_past_comma (&p) == SUCCESS) 4780 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL) 4781 return PARSE_OPERAND_FAIL; 4782 } 4783 else 4784 { 4785 if (inst.operands[i].negative) 4786 { 4787 inst.operands[i].negative = 0; 4788 p--; 4789 } 4790 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX)) 4791 return PARSE_OPERAND_FAIL; 4792 } 4793 } 4794 } 4795 4796 /* If at this point neither .preind nor .postind is set, we have a 4797 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */ 4798 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0) 4799 { 4800 inst.operands[i].preind = 1; 4801 inst.reloc.exp.X_op = O_constant; 4802 inst.reloc.exp.X_add_number = 0; 4803 } 4804 *str = p; 4805 return PARSE_OPERAND_SUCCESS; 4806} 4807 4808static int 4809parse_address (char **str, int i) 4810{ 4811 return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS 4812 ? SUCCESS : FAIL; 4813} 4814 4815static parse_operand_result 4816parse_address_group_reloc (char **str, int i, group_reloc_type type) 4817{ 4818 return parse_address_main (str, i, 1, type); 4819} 4820 4821/* Parse an operand for a MOVW or MOVT instruction. */ 4822static int 4823parse_half (char **str) 4824{ 4825 char * p; 4826 4827 p = *str; 4828 skip_past_char (&p, '#'); 4829 if (strncasecmp (p, ":lower16:", 9) == 0) 4830 inst.reloc.type = BFD_RELOC_ARM_MOVW; 4831 else if (strncasecmp (p, ":upper16:", 9) == 0) 4832 inst.reloc.type = BFD_RELOC_ARM_MOVT; 4833 4834 if (inst.reloc.type != BFD_RELOC_UNUSED) 4835 { 4836 p += 9; 4837 skip_whitespace(p); 4838 } 4839 4840 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX)) 4841 return FAIL; 4842 4843 if (inst.reloc.type == BFD_RELOC_UNUSED) 4844 { 4845 if (inst.reloc.exp.X_op != O_constant) 4846 { 4847 inst.error = _("constant expression expected"); 4848 return FAIL; 4849 } 4850 if (inst.reloc.exp.X_add_number < 0 4851 || inst.reloc.exp.X_add_number > 0xffff) 4852 { 4853 inst.error = _("immediate value out of range"); 4854 return FAIL; 4855 } 4856 } 4857 *str = p; 4858 return SUCCESS; 4859} 4860 4861/* Miscellaneous. */ 4862 4863/* Parse a PSR flag operand. The value returned is FAIL on syntax error, 4864 or a bitmask suitable to be or-ed into the ARM msr instruction. */ 4865static int 4866parse_psr (char **str) 4867{ 4868 char *p; 4869 unsigned long psr_field; 4870 const struct asm_psr *psr; 4871 char *start; 4872 4873 /* CPSR's and SPSR's can now be lowercase. This is just a convenience 4874 feature for ease of use and backwards compatibility. */ 4875 p = *str; 4876 if (strncasecmp (p, "SPSR", 4) == 0) 4877 psr_field = SPSR_BIT; 4878 else if (strncasecmp (p, "CPSR", 4) == 0) 4879 psr_field = 0; 4880 else 4881 { 4882 start = p; 4883 do 4884 p++; 4885 while (ISALNUM (*p) || *p == '_'); 4886 4887 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start); 4888 if (!psr) 4889 return FAIL; 4890 4891 *str = p; 4892 return psr->field; 4893 } 4894 4895 p += 4; 4896 if (*p == '_') 4897 { 4898 /* A suffix follows. */ 4899 p++; 4900 start = p; 4901 4902 do 4903 p++; 4904 while (ISALNUM (*p) || *p == '_'); 4905 4906 psr = hash_find_n (arm_psr_hsh, start, p - start); 4907 if (!psr) 4908 goto error; 4909 4910 psr_field |= psr->field; 4911 } 4912 else 4913 { 4914 if (ISALNUM (*p)) 4915 goto error; /* Garbage after "[CS]PSR". */ 4916 4917 psr_field |= (PSR_c | PSR_f); 4918 } 4919 *str = p; 4920 return psr_field; 4921 4922 error: 4923 inst.error = _("flag for {c}psr instruction expected"); 4924 return FAIL; 4925} 4926 4927/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a 4928 value suitable for splatting into the AIF field of the instruction. */ 4929 4930static int 4931parse_cps_flags (char **str) 4932{ 4933 int val = 0; 4934 int saw_a_flag = 0; 4935 char *s = *str; 4936 4937 for (;;) 4938 switch (*s++) 4939 { 4940 case '\0': case ',': 4941 goto done; 4942 4943 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break; 4944 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break; 4945 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break; 4946 4947 default: 4948 inst.error = _("unrecognized CPS flag"); 4949 return FAIL; 4950 } 4951 4952 done: 4953 if (saw_a_flag == 0) 4954 { 4955 inst.error = _("missing CPS flags"); 4956 return FAIL; 4957 } 4958 4959 *str = s - 1; 4960 return val; 4961} 4962 4963/* Parse an endian specifier ("BE" or "LE", case insensitive); 4964 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */ 4965 4966static int 4967parse_endian_specifier (char **str) 4968{ 4969 int little_endian; 4970 char *s = *str; 4971 4972 if (strncasecmp (s, "BE", 2)) 4973 little_endian = 0; 4974 else if (strncasecmp (s, "LE", 2)) 4975 little_endian = 1; 4976 else 4977 { 4978 inst.error = _("valid endian specifiers are be or le"); 4979 return FAIL; 4980 } 4981 4982 if (ISALNUM (s[2]) || s[2] == '_') 4983 { 4984 inst.error = _("valid endian specifiers are be or le"); 4985 return FAIL; 4986 } 4987 4988 *str = s + 2; 4989 return little_endian; 4990} 4991 4992/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a 4993 value suitable for poking into the rotate field of an sxt or sxta 4994 instruction, or FAIL on error. */ 4995 4996static int 4997parse_ror (char **str) 4998{ 4999 int rot; 5000 char *s = *str; 5001 5002 if (strncasecmp (s, "ROR", 3) == 0) 5003 s += 3; 5004 else 5005 { 5006 inst.error = _("missing rotation field after comma"); 5007 return FAIL; 5008 } 5009 5010 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL) 5011 return FAIL; 5012 5013 switch (rot) 5014 { 5015 case 0: *str = s; return 0x0; 5016 case 8: *str = s; return 0x1; 5017 case 16: *str = s; return 0x2; 5018 case 24: *str = s; return 0x3; 5019 5020 default: 5021 inst.error = _("rotation can only be 0, 8, 16, or 24"); 5022 return FAIL; 5023 } 5024} 5025 5026/* Parse a conditional code (from conds[] below). The value returned is in the 5027 range 0 .. 14, or FAIL. */ 5028static int 5029parse_cond (char **str) 5030{ 5031 char *p, *q; 5032 const struct asm_cond *c; 5033 5034 p = q = *str; 5035 while (ISALPHA (*q)) 5036 q++; 5037 5038 c = hash_find_n (arm_cond_hsh, p, q - p); 5039 if (!c) 5040 { 5041 inst.error = _("condition required"); 5042 return FAIL; 5043 } 5044 5045 *str = q; 5046 return c->value; 5047} 5048 5049/* Parse an option for a barrier instruction. Returns the encoding for the 5050 option, or FAIL. */ 5051static int 5052parse_barrier (char **str) 5053{ 5054 char *p, *q; 5055 const struct asm_barrier_opt *o; 5056 5057 p = q = *str; 5058 while (ISALPHA (*q)) 5059 q++; 5060 5061 o = hash_find_n (arm_barrier_opt_hsh, p, q - p); 5062 if (!o) 5063 return FAIL; 5064 5065 *str = q; 5066 return o->value; 5067} 5068 5069/* Parse the operands of a table branch instruction. Similar to a memory 5070 operand. */ 5071static int 5072parse_tb (char **str) 5073{ 5074 char * p = *str; 5075 int reg; 5076 5077 if (skip_past_char (&p, '[') == FAIL) 5078 { 5079 inst.error = _("'[' expected"); 5080 return FAIL; 5081 } 5082 5083 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5084 { 5085 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5086 return FAIL; 5087 } 5088 inst.operands[0].reg = reg; 5089 5090 if (skip_past_comma (&p) == FAIL) 5091 { 5092 inst.error = _("',' expected"); 5093 return FAIL; 5094 } 5095 5096 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) 5097 { 5098 inst.error = _(reg_expected_msgs[REG_TYPE_RN]); 5099 return FAIL; 5100 } 5101 inst.operands[0].imm = reg; 5102 5103 if (skip_past_comma (&p) == SUCCESS) 5104 { 5105 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) 5106 return FAIL; 5107 if (inst.reloc.exp.X_add_number != 1) 5108 { 5109 inst.error = _("invalid shift"); 5110 return FAIL; 5111 } 5112 inst.operands[0].shifted = 1; 5113 } 5114 5115 if (skip_past_char (&p, ']') == FAIL) 5116 { 5117 inst.error = _("']' expected"); 5118 return FAIL; 5119 } 5120 *str = p; 5121 return SUCCESS; 5122} 5123 5124/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more 5125 information on the types the operands can take and how they are encoded. 5126 Up to four operands may be read; this function handles setting the 5127 ".present" field for each read operand itself. 5128 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS, 5129 else returns FAIL. */ 5130 5131static int 5132parse_neon_mov (char **str, int *which_operand) 5133{ 5134 int i = *which_operand, val; 5135 enum arm_reg_type rtype; 5136 char *ptr = *str; 5137 struct neon_type_el optype; 5138 5139 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5140 { 5141 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */ 5142 inst.operands[i].reg = val; 5143 inst.operands[i].isscalar = 1; 5144 inst.operands[i].vectype = optype; 5145 inst.operands[i++].present = 1; 5146 5147 if (skip_past_comma (&ptr) == FAIL) 5148 goto wanted_comma; 5149 5150 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5151 goto wanted_arm; 5152 5153 inst.operands[i].reg = val; 5154 inst.operands[i].isreg = 1; 5155 inst.operands[i].present = 1; 5156 } 5157 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype)) 5158 != FAIL) 5159 { 5160 /* Cases 0, 1, 2, 3, 5 (D only). */ 5161 if (skip_past_comma (&ptr) == FAIL) 5162 goto wanted_comma; 5163 5164 inst.operands[i].reg = val; 5165 inst.operands[i].isreg = 1; 5166 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5167 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5168 inst.operands[i].isvec = 1; 5169 inst.operands[i].vectype = optype; 5170 inst.operands[i++].present = 1; 5171 5172 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5173 { 5174 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>. 5175 Case 13: VMOV <Sd>, <Rm> */ 5176 inst.operands[i].reg = val; 5177 inst.operands[i].isreg = 1; 5178 inst.operands[i].present = 1; 5179 5180 if (rtype == REG_TYPE_NQ) 5181 { 5182 first_error (_("can't use Neon quad register here")); 5183 return FAIL; 5184 } 5185 else if (rtype != REG_TYPE_VFS) 5186 { 5187 i++; 5188 if (skip_past_comma (&ptr) == FAIL) 5189 goto wanted_comma; 5190 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5191 goto wanted_arm; 5192 inst.operands[i].reg = val; 5193 inst.operands[i].isreg = 1; 5194 inst.operands[i].present = 1; 5195 } 5196 } 5197 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS) 5198 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm> 5199 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm> 5200 Case 10: VMOV.F32 <Sd>, #<imm> 5201 Case 11: VMOV.F64 <Dd>, #<imm> */ 5202 inst.operands[i].immisfloat = 1; 5203 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, 5204 &optype)) != FAIL) 5205 { 5206 /* Case 0: VMOV<c><q> <Qd>, <Qm> 5207 Case 1: VMOV<c><q> <Dd>, <Dm> 5208 Case 8: VMOV.F32 <Sd>, <Sm> 5209 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */ 5210 5211 inst.operands[i].reg = val; 5212 inst.operands[i].isreg = 1; 5213 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); 5214 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5215 inst.operands[i].isvec = 1; 5216 inst.operands[i].vectype = optype; 5217 inst.operands[i].present = 1; 5218 5219 if (skip_past_comma (&ptr) == SUCCESS) 5220 { 5221 /* Case 15. */ 5222 i++; 5223 5224 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5225 goto wanted_arm; 5226 5227 inst.operands[i].reg = val; 5228 inst.operands[i].isreg = 1; 5229 inst.operands[i++].present = 1; 5230 5231 if (skip_past_comma (&ptr) == FAIL) 5232 goto wanted_comma; 5233 5234 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL) 5235 goto wanted_arm; 5236 5237 inst.operands[i].reg = val; 5238 inst.operands[i].isreg = 1; 5239 inst.operands[i++].present = 1; 5240 } 5241 } 5242 else if (parse_big_immediate (&ptr, i) == SUCCESS) 5243 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm> 5244 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */ 5245 ; 5246 else 5247 { 5248 first_error (_("expected <Rm> or <Dm> or <Qm> operand")); 5249 return FAIL; 5250 } 5251 } 5252 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5253 { 5254 /* Cases 6, 7. */ 5255 inst.operands[i].reg = val; 5256 inst.operands[i].isreg = 1; 5257 inst.operands[i++].present = 1; 5258 5259 if (skip_past_comma (&ptr) == FAIL) 5260 goto wanted_comma; 5261 5262 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL) 5263 { 5264 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */ 5265 inst.operands[i].reg = val; 5266 inst.operands[i].isscalar = 1; 5267 inst.operands[i].present = 1; 5268 inst.operands[i].vectype = optype; 5269 } 5270 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL) 5271 { 5272 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */ 5273 inst.operands[i].reg = val; 5274 inst.operands[i].isreg = 1; 5275 inst.operands[i++].present = 1; 5276 5277 if (skip_past_comma (&ptr) == FAIL) 5278 goto wanted_comma; 5279 5280 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype)) 5281 == FAIL) 5282 { 5283 first_error (_(reg_expected_msgs[REG_TYPE_VFSD])); 5284 return FAIL; 5285 } 5286 5287 inst.operands[i].reg = val; 5288 inst.operands[i].isreg = 1; 5289 inst.operands[i].isvec = 1; 5290 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); 5291 inst.operands[i].vectype = optype; 5292 inst.operands[i].present = 1; 5293 5294 if (rtype == REG_TYPE_VFS) 5295 { 5296 /* Case 14. */ 5297 i++; 5298 if (skip_past_comma (&ptr) == FAIL) 5299 goto wanted_comma; 5300 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, 5301 &optype)) == FAIL) 5302 { 5303 first_error (_(reg_expected_msgs[REG_TYPE_VFS])); 5304 return FAIL; 5305 } 5306 inst.operands[i].reg = val; 5307 inst.operands[i].isreg = 1; 5308 inst.operands[i].isvec = 1; 5309 inst.operands[i].issingle = 1; 5310 inst.operands[i].vectype = optype; 5311 inst.operands[i].present = 1; 5312 } 5313 } 5314 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype)) 5315 != FAIL) 5316 { 5317 /* Case 13. */ 5318 inst.operands[i].reg = val; 5319 inst.operands[i].isreg = 1; 5320 inst.operands[i].isvec = 1; 5321 inst.operands[i].issingle = 1; 5322 inst.operands[i].vectype = optype; 5323 inst.operands[i++].present = 1; 5324 } 5325 } 5326 else 5327 { 5328 first_error (_("parse error")); 5329 return FAIL; 5330 } 5331 5332 /* Successfully parsed the operands. Update args. */ 5333 *which_operand = i; 5334 *str = ptr; 5335 return SUCCESS; 5336 5337 wanted_comma: 5338 first_error (_("expected comma")); 5339 return FAIL; 5340 5341 wanted_arm: 5342 first_error (_(reg_expected_msgs[REG_TYPE_RN])); 5343 return FAIL; 5344} 5345 5346/* Matcher codes for parse_operands. */ 5347enum operand_parse_code 5348{ 5349 OP_stop, /* end of line */ 5350 5351 OP_RR, /* ARM register */ 5352 OP_RRnpc, /* ARM register, not r15 */ 5353 OP_RRnpcb, /* ARM register, not r15, in square brackets */ 5354 OP_RRw, /* ARM register, not r15, optional trailing ! */ 5355 OP_RCP, /* Coprocessor number */ 5356 OP_RCN, /* Coprocessor register */ 5357 OP_RF, /* FPA register */ 5358 OP_RVS, /* VFP single precision register */ 5359 OP_RVD, /* VFP double precision register (0..15) */ 5360 OP_RND, /* Neon double precision register (0..31) */ 5361 OP_RNQ, /* Neon quad precision register */ 5362 OP_RVSD, /* VFP single or double precision register */ 5363 OP_RNDQ, /* Neon double or quad precision register */ 5364 OP_RNSDQ, /* Neon single, double or quad precision register */ 5365 OP_RNSC, /* Neon scalar D[X] */ 5366 OP_RVC, /* VFP control register */ 5367 OP_RMF, /* Maverick F register */ 5368 OP_RMD, /* Maverick D register */ 5369 OP_RMFX, /* Maverick FX register */ 5370 OP_RMDX, /* Maverick DX register */ 5371 OP_RMAX, /* Maverick AX register */ 5372 OP_RMDS, /* Maverick DSPSC register */ 5373 OP_RIWR, /* iWMMXt wR register */ 5374 OP_RIWC, /* iWMMXt wC register */ 5375 OP_RIWG, /* iWMMXt wCG register */ 5376 OP_RXA, /* XScale accumulator register */ 5377 5378 OP_REGLST, /* ARM register list */ 5379 OP_VRSLST, /* VFP single-precision register list */ 5380 OP_VRDLST, /* VFP double-precision register list */ 5381 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */ 5382 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */ 5383 OP_NSTRLST, /* Neon element/structure list */ 5384 5385 OP_NILO, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */ 5386 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */ 5387 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */ 5388 OP_RR_RNSC, /* ARM reg or Neon scalar. */ 5389 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */ 5390 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */ 5391 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */ 5392 OP_VMOV, /* Neon VMOV operands. */ 5393 OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN. */ 5394 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */ 5395 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */ 5396 5397 OP_I0, /* immediate zero */ 5398 OP_I7, /* immediate value 0 .. 7 */ 5399 OP_I15, /* 0 .. 15 */ 5400 OP_I16, /* 1 .. 16 */ 5401 OP_I16z, /* 0 .. 16 */ 5402 OP_I31, /* 0 .. 31 */ 5403 OP_I31w, /* 0 .. 31, optional trailing ! */ 5404 OP_I32, /* 1 .. 32 */ 5405 OP_I32z, /* 0 .. 32 */ 5406 OP_I63, /* 0 .. 63 */ 5407 OP_I63s, /* -64 .. 63 */ 5408 OP_I64, /* 1 .. 64 */ 5409 OP_I64z, /* 0 .. 64 */ 5410 OP_I255, /* 0 .. 255 */ 5411 5412 OP_I4b, /* immediate, prefix optional, 1 .. 4 */ 5413 OP_I7b, /* 0 .. 7 */ 5414 OP_I15b, /* 0 .. 15 */ 5415 OP_I31b, /* 0 .. 31 */ 5416 5417 OP_SH, /* shifter operand */ 5418 OP_SHG, /* shifter operand with possible group relocation */ 5419 OP_ADDR, /* Memory address expression (any mode) */ 5420 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */ 5421 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */ 5422 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */ 5423 OP_EXP, /* arbitrary expression */ 5424 OP_EXPi, /* same, with optional immediate prefix */ 5425 OP_EXPr, /* same, with optional relocation suffix */ 5426 OP_HALF, /* 0 .. 65535 or low/high reloc. */ 5427 5428 OP_CPSF, /* CPS flags */ 5429 OP_ENDI, /* Endianness specifier */ 5430 OP_PSR, /* CPSR/SPSR mask for msr */ 5431 OP_COND, /* conditional code */ 5432 OP_TB, /* Table branch. */ 5433 5434 OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */ 5435 OP_APSR_RR, /* ARM register or "APSR_nzcv". */ 5436 5437 OP_RRnpc_I0, /* ARM register or literal 0 */ 5438 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ 5439 OP_RR_EXi, /* ARM register or expression with imm prefix */ 5440 OP_RF_IF, /* FPA register or immediate */ 5441 OP_RIWR_RIWC, /* iWMMXt R or C reg */ 5442 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */ 5443 5444 /* Optional operands. */ 5445 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */ 5446 OP_oI31b, /* 0 .. 31 */ 5447 OP_oI32b, /* 1 .. 32 */ 5448 OP_oIffffb, /* 0 .. 65535 */ 5449 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */ 5450 5451 OP_oRR, /* ARM register */ 5452 OP_oRRnpc, /* ARM register, not the PC */ 5453 OP_oRRw, /* ARM register, not r15, optional trailing ! */ 5454 OP_oRND, /* Optional Neon double precision register */ 5455 OP_oRNQ, /* Optional Neon quad precision register */ 5456 OP_oRNDQ, /* Optional Neon double or quad precision register */ 5457 OP_oRNSDQ, /* Optional single, double or quad precision vector register */ 5458 OP_oSHll, /* LSL immediate */ 5459 OP_oSHar, /* ASR immediate */ 5460 OP_oSHllar, /* LSL or ASR immediate */ 5461 OP_oROR, /* ROR 0/8/16/24 */ 5462 OP_oBARRIER, /* Option argument for a barrier instruction. */ 5463 5464 OP_FIRST_OPTIONAL = OP_oI7b 5465}; 5466 5467/* Generic instruction operand parser. This does no encoding and no 5468 semantic validation; it merely squirrels values away in the inst 5469 structure. Returns SUCCESS or FAIL depending on whether the 5470 specified grammar matched. */ 5471static int 5472parse_operands (char *str, const unsigned char *pattern) 5473{ 5474 unsigned const char *upat = pattern; 5475 char *backtrack_pos = 0; 5476 const char *backtrack_error = 0; 5477 int i, val, backtrack_index = 0; 5478 enum arm_reg_type rtype; 5479 parse_operand_result result; 5480 5481#define po_char_or_fail(chr) do { \ 5482 if (skip_past_char (&str, chr) == FAIL) \ 5483 goto bad_args; \ 5484} while (0) 5485 5486#define po_reg_or_fail(regtype) do { \ 5487 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5488 &inst.operands[i].vectype); \ 5489 if (val == FAIL) \ 5490 { \ 5491 first_error (_(reg_expected_msgs[regtype])); \ 5492 goto failure; \ 5493 } \ 5494 inst.operands[i].reg = val; \ 5495 inst.operands[i].isreg = 1; \ 5496 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5497 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5498 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5499 || rtype == REG_TYPE_VFD \ 5500 || rtype == REG_TYPE_NQ); \ 5501} while (0) 5502 5503#define po_reg_or_goto(regtype, label) do { \ 5504 val = arm_typed_reg_parse (&str, regtype, &rtype, \ 5505 &inst.operands[i].vectype); \ 5506 if (val == FAIL) \ 5507 goto label; \ 5508 \ 5509 inst.operands[i].reg = val; \ 5510 inst.operands[i].isreg = 1; \ 5511 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \ 5512 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \ 5513 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \ 5514 || rtype == REG_TYPE_VFD \ 5515 || rtype == REG_TYPE_NQ); \ 5516} while (0) 5517 5518#define po_imm_or_fail(min, max, popt) do { \ 5519 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \ 5520 goto failure; \ 5521 inst.operands[i].imm = val; \ 5522} while (0) 5523 5524#define po_scalar_or_goto(elsz, label) do { \ 5525 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \ 5526 if (val == FAIL) \ 5527 goto label; \ 5528 inst.operands[i].reg = val; \ 5529 inst.operands[i].isscalar = 1; \ 5530} while (0) 5531 5532#define po_misc_or_fail(expr) do { \ 5533 if (expr) \ 5534 goto failure; \ 5535} while (0) 5536 5537#define po_misc_or_fail_no_backtrack(expr) do { \ 5538 result = expr; \ 5539 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\ 5540 backtrack_pos = 0; \ 5541 if (result != PARSE_OPERAND_SUCCESS) \ 5542 goto failure; \ 5543} while (0) 5544 5545 skip_whitespace (str); 5546 5547 for (i = 0; upat[i] != OP_stop; i++) 5548 { 5549 if (upat[i] >= OP_FIRST_OPTIONAL) 5550 { 5551 /* Remember where we are in case we need to backtrack. */ 5552 assert (!backtrack_pos); 5553 backtrack_pos = str; 5554 backtrack_error = inst.error; 5555 backtrack_index = i; 5556 } 5557 5558 if (i > 0 && (i > 1 || inst.operands[0].present)) 5559 po_char_or_fail (','); 5560 5561 switch (upat[i]) 5562 { 5563 /* Registers */ 5564 case OP_oRRnpc: 5565 case OP_RRnpc: 5566 case OP_oRR: 5567 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; 5568 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break; 5569 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break; 5570 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break; 5571 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break; 5572 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break; 5573 case OP_oRND: 5574 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break; 5575 case OP_RVC: 5576 po_reg_or_goto (REG_TYPE_VFC, coproc_reg); 5577 break; 5578 /* Also accept generic coprocessor regs for unknown registers. */ 5579 coproc_reg: 5580 po_reg_or_fail (REG_TYPE_CN); 5581 break; 5582 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break; 5583 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break; 5584 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break; 5585 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break; 5586 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break; 5587 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break; 5588 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break; 5589 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break; 5590 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break; 5591 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break; 5592 case OP_oRNQ: 5593 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break; 5594 case OP_oRNDQ: 5595 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break; 5596 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break; 5597 case OP_oRNSDQ: 5598 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break; 5599 5600 /* Neon scalar. Using an element size of 8 means that some invalid 5601 scalars are accepted here, so deal with those in later code. */ 5602 case OP_RNSC: po_scalar_or_goto (8, failure); break; 5603 5604 /* WARNING: We can expand to two operands here. This has the potential 5605 to totally confuse the backtracking mechanism! It will be OK at 5606 least as long as we don't try to use optional args as well, 5607 though. */ 5608 case OP_NILO: 5609 { 5610 po_reg_or_goto (REG_TYPE_NDQ, try_imm); 5611 inst.operands[i].present = 1; 5612 i++; 5613 skip_past_comma (&str); 5614 po_reg_or_goto (REG_TYPE_NDQ, one_reg_only); 5615 break; 5616 one_reg_only: 5617 /* Optional register operand was omitted. Unfortunately, it's in 5618 operands[i-1] and we need it to be in inst.operands[i]. Fix that 5619 here (this is a bit grotty). */ 5620 inst.operands[i] = inst.operands[i-1]; 5621 inst.operands[i-1].present = 0; 5622 break; 5623 try_imm: 5624 /* There's a possibility of getting a 64-bit immediate here, so 5625 we need special handling. */ 5626 if (parse_big_immediate (&str, i) == FAIL) 5627 { 5628 inst.error = _("immediate value is out of range"); 5629 goto failure; 5630 } 5631 } 5632 break; 5633 5634 case OP_RNDQ_I0: 5635 { 5636 po_reg_or_goto (REG_TYPE_NDQ, try_imm0); 5637 break; 5638 try_imm0: 5639 po_imm_or_fail (0, 0, TRUE); 5640 } 5641 break; 5642 5643 case OP_RVSD_I0: 5644 po_reg_or_goto (REG_TYPE_VFSD, try_imm0); 5645 break; 5646 5647 case OP_RR_RNSC: 5648 { 5649 po_scalar_or_goto (8, try_rr); 5650 break; 5651 try_rr: 5652 po_reg_or_fail (REG_TYPE_RN); 5653 } 5654 break; 5655 5656 case OP_RNSDQ_RNSC: 5657 { 5658 po_scalar_or_goto (8, try_nsdq); 5659 break; 5660 try_nsdq: 5661 po_reg_or_fail (REG_TYPE_NSDQ); 5662 } 5663 break; 5664 5665 case OP_RNDQ_RNSC: 5666 { 5667 po_scalar_or_goto (8, try_ndq); 5668 break; 5669 try_ndq: 5670 po_reg_or_fail (REG_TYPE_NDQ); 5671 } 5672 break; 5673 5674 case OP_RND_RNSC: 5675 { 5676 po_scalar_or_goto (8, try_vfd); 5677 break; 5678 try_vfd: 5679 po_reg_or_fail (REG_TYPE_VFD); 5680 } 5681 break; 5682 5683 case OP_VMOV: 5684 /* WARNING: parse_neon_mov can move the operand counter, i. If we're 5685 not careful then bad things might happen. */ 5686 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL); 5687 break; 5688 5689 case OP_RNDQ_IMVNb: 5690 { 5691 po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm); 5692 break; 5693 try_mvnimm: 5694 /* There's a possibility of getting a 64-bit immediate here, so 5695 we need special handling. */ 5696 if (parse_big_immediate (&str, i) == FAIL) 5697 { 5698 inst.error = _("immediate value is out of range"); 5699 goto failure; 5700 } 5701 } 5702 break; 5703 5704 case OP_RNDQ_I63b: 5705 { 5706 po_reg_or_goto (REG_TYPE_NDQ, try_shimm); 5707 break; 5708 try_shimm: 5709 po_imm_or_fail (0, 63, TRUE); 5710 } 5711 break; 5712 5713 case OP_RRnpcb: 5714 po_char_or_fail ('['); 5715 po_reg_or_fail (REG_TYPE_RN); 5716 po_char_or_fail (']'); 5717 break; 5718 5719 case OP_RRw: 5720 case OP_oRRw: 5721 po_reg_or_fail (REG_TYPE_RN); 5722 if (skip_past_char (&str, '!') == SUCCESS) 5723 inst.operands[i].writeback = 1; 5724 break; 5725 5726 /* Immediates */ 5727 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break; 5728 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break; 5729 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break; 5730 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break; 5731 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break; 5732 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break; 5733 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break; 5734 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break; 5735 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break; 5736 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break; 5737 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break; 5738 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break; 5739 5740 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break; 5741 case OP_oI7b: 5742 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break; 5743 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break; 5744 case OP_oI31b: 5745 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break; 5746 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break; 5747 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break; 5748 5749 /* Immediate variants */ 5750 case OP_oI255c: 5751 po_char_or_fail ('{'); 5752 po_imm_or_fail (0, 255, TRUE); 5753 po_char_or_fail ('}'); 5754 break; 5755 5756 case OP_I31w: 5757 /* The expression parser chokes on a trailing !, so we have 5758 to find it first and zap it. */ 5759 { 5760 char *s = str; 5761 while (*s && *s != ',') 5762 s++; 5763 if (s[-1] == '!') 5764 { 5765 s[-1] = '\0'; 5766 inst.operands[i].writeback = 1; 5767 } 5768 po_imm_or_fail (0, 31, TRUE); 5769 if (str == s - 1) 5770 str = s; 5771 } 5772 break; 5773 5774 /* Expressions */ 5775 case OP_EXPi: EXPi: 5776 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5777 GE_OPT_PREFIX)); 5778 break; 5779 5780 case OP_EXP: 5781 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5782 GE_NO_PREFIX)); 5783 break; 5784 5785 case OP_EXPr: EXPr: 5786 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str, 5787 GE_NO_PREFIX)); 5788 if (inst.reloc.exp.X_op == O_symbol) 5789 { 5790 val = parse_reloc (&str); 5791 if (val == -1) 5792 { 5793 inst.error = _("unrecognized relocation suffix"); 5794 goto failure; 5795 } 5796 else if (val != BFD_RELOC_UNUSED) 5797 { 5798 inst.operands[i].imm = val; 5799 inst.operands[i].hasreloc = 1; 5800 } 5801 } 5802 break; 5803 5804 /* Operand for MOVW or MOVT. */ 5805 case OP_HALF: 5806 po_misc_or_fail (parse_half (&str)); 5807 break; 5808 5809 /* Register or expression */ 5810 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break; 5811 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break; 5812 5813 /* Register or immediate */ 5814 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break; 5815 I0: po_imm_or_fail (0, 0, FALSE); break; 5816 5817 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break; 5818 IF: 5819 if (!is_immediate_prefix (*str)) 5820 goto bad_args; 5821 str++; 5822 val = parse_fpa_immediate (&str); 5823 if (val == FAIL) 5824 goto failure; 5825 /* FPA immediates are encoded as registers 8-15. 5826 parse_fpa_immediate has already applied the offset. */ 5827 inst.operands[i].reg = val; 5828 inst.operands[i].isreg = 1; 5829 break; 5830 5831 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break; 5832 I32z: po_imm_or_fail (0, 32, FALSE); break; 5833 5834 /* Two kinds of register */ 5835 case OP_RIWR_RIWC: 5836 { 5837 struct reg_entry *rege = arm_reg_parse_multi (&str); 5838 if (!rege 5839 || (rege->type != REG_TYPE_MMXWR 5840 && rege->type != REG_TYPE_MMXWC 5841 && rege->type != REG_TYPE_MMXWCG)) 5842 { 5843 inst.error = _("iWMMXt data or control register expected"); 5844 goto failure; 5845 } 5846 inst.operands[i].reg = rege->number; 5847 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR); 5848 } 5849 break; 5850 5851 case OP_RIWC_RIWG: 5852 { 5853 struct reg_entry *rege = arm_reg_parse_multi (&str); 5854 if (!rege 5855 || (rege->type != REG_TYPE_MMXWC 5856 && rege->type != REG_TYPE_MMXWCG)) 5857 { 5858 inst.error = _("iWMMXt control register expected"); 5859 goto failure; 5860 } 5861 inst.operands[i].reg = rege->number; 5862 inst.operands[i].isreg = 1; 5863 } 5864 break; 5865 5866 /* Misc */ 5867 case OP_CPSF: val = parse_cps_flags (&str); break; 5868 case OP_ENDI: val = parse_endian_specifier (&str); break; 5869 case OP_oROR: val = parse_ror (&str); break; 5870 case OP_PSR: val = parse_psr (&str); break; 5871 case OP_COND: val = parse_cond (&str); break; 5872 case OP_oBARRIER:val = parse_barrier (&str); break; 5873 5874 case OP_RVC_PSR: 5875 po_reg_or_goto (REG_TYPE_VFC, try_psr); 5876 inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */ 5877 break; 5878 try_psr: 5879 val = parse_psr (&str); 5880 break; 5881 5882 case OP_APSR_RR: 5883 po_reg_or_goto (REG_TYPE_RN, try_apsr); 5884 break; 5885 try_apsr: 5886 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS 5887 instruction). */ 5888 if (strncasecmp (str, "APSR_", 5) == 0) 5889 { 5890 unsigned found = 0; 5891 str += 5; 5892 while (found < 15) 5893 switch (*str++) 5894 { 5895 case 'c': found = (found & 1) ? 16 : found | 1; break; 5896 case 'n': found = (found & 2) ? 16 : found | 2; break; 5897 case 'z': found = (found & 4) ? 16 : found | 4; break; 5898 case 'v': found = (found & 8) ? 16 : found | 8; break; 5899 default: found = 16; 5900 } 5901 if (found != 15) 5902 goto failure; 5903 inst.operands[i].isvec = 1; 5904 } 5905 else 5906 goto failure; 5907 break; 5908 5909 case OP_TB: 5910 po_misc_or_fail (parse_tb (&str)); 5911 break; 5912 5913 /* Register lists */ 5914 case OP_REGLST: 5915 val = parse_reg_list (&str); 5916 if (*str == '^') 5917 { 5918 inst.operands[1].writeback = 1; 5919 str++; 5920 } 5921 break; 5922 5923 case OP_VRSLST: 5924 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S); 5925 break; 5926 5927 case OP_VRDLST: 5928 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D); 5929 break; 5930 5931 case OP_VRSDLST: 5932 /* Allow Q registers too. */ 5933 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5934 REGLIST_NEON_D); 5935 if (val == FAIL) 5936 { 5937 inst.error = NULL; 5938 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5939 REGLIST_VFP_S); 5940 inst.operands[i].issingle = 1; 5941 } 5942 break; 5943 5944 case OP_NRDLST: 5945 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 5946 REGLIST_NEON_D); 5947 break; 5948 5949 case OP_NSTRLST: 5950 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg, 5951 &inst.operands[i].vectype); 5952 break; 5953 5954 /* Addressing modes */ 5955 case OP_ADDR: 5956 po_misc_or_fail (parse_address (&str, i)); 5957 break; 5958 5959 case OP_ADDRGLDR: 5960 po_misc_or_fail_no_backtrack ( 5961 parse_address_group_reloc (&str, i, GROUP_LDR)); 5962 break; 5963 5964 case OP_ADDRGLDRS: 5965 po_misc_or_fail_no_backtrack ( 5966 parse_address_group_reloc (&str, i, GROUP_LDRS)); 5967 break; 5968 5969 case OP_ADDRGLDC: 5970 po_misc_or_fail_no_backtrack ( 5971 parse_address_group_reloc (&str, i, GROUP_LDC)); 5972 break; 5973 5974 case OP_SH: 5975 po_misc_or_fail (parse_shifter_operand (&str, i)); 5976 break; 5977 5978 case OP_SHG: 5979 po_misc_or_fail_no_backtrack ( 5980 parse_shifter_operand_group_reloc (&str, i)); 5981 break; 5982 5983 case OP_oSHll: 5984 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE)); 5985 break; 5986 5987 case OP_oSHar: 5988 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE)); 5989 break; 5990 5991 case OP_oSHllar: 5992 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE)); 5993 break; 5994 5995 default: 5996 as_fatal ("unhandled operand code %d", upat[i]); 5997 } 5998 5999 /* Various value-based sanity checks and shared operations. We 6000 do not signal immediate failures for the register constraints; 6001 this allows a syntax error to take precedence. */ 6002 switch (upat[i]) 6003 { 6004 case OP_oRRnpc: 6005 case OP_RRnpc: 6006 case OP_RRnpcb: 6007 case OP_RRw: 6008 case OP_oRRw: 6009 case OP_RRnpc_I0: 6010 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC) 6011 inst.error = BAD_PC; 6012 break; 6013 6014 case OP_CPSF: 6015 case OP_ENDI: 6016 case OP_oROR: 6017 case OP_PSR: 6018 case OP_RVC_PSR: 6019 case OP_COND: 6020 case OP_oBARRIER: 6021 case OP_REGLST: 6022 case OP_VRSLST: 6023 case OP_VRDLST: 6024 case OP_VRSDLST: 6025 case OP_NRDLST: 6026 case OP_NSTRLST: 6027 if (val == FAIL) 6028 goto failure; 6029 inst.operands[i].imm = val; 6030 break; 6031 6032 default: 6033 break; 6034 } 6035 6036 /* If we get here, this operand was successfully parsed. */ 6037 inst.operands[i].present = 1; 6038 continue; 6039 6040 bad_args: 6041 inst.error = BAD_ARGS; 6042 6043 failure: 6044 if (!backtrack_pos) 6045 { 6046 /* The parse routine should already have set inst.error, but set a 6047 defaut here just in case. */ 6048 if (!inst.error) 6049 inst.error = _("syntax error"); 6050 return FAIL; 6051 } 6052 6053 /* Do not backtrack over a trailing optional argument that 6054 absorbed some text. We will only fail again, with the 6055 'garbage following instruction' error message, which is 6056 probably less helpful than the current one. */ 6057 if (backtrack_index == i && backtrack_pos != str 6058 && upat[i+1] == OP_stop) 6059 { 6060 if (!inst.error) 6061 inst.error = _("syntax error"); 6062 return FAIL; 6063 } 6064 6065 /* Try again, skipping the optional argument at backtrack_pos. */ 6066 str = backtrack_pos; 6067 inst.error = backtrack_error; 6068 inst.operands[backtrack_index].present = 0; 6069 i = backtrack_index; 6070 backtrack_pos = 0; 6071 } 6072 6073 /* Check that we have parsed all the arguments. */ 6074 if (*str != '\0' && !inst.error) 6075 inst.error = _("garbage following instruction"); 6076 6077 return inst.error ? FAIL : SUCCESS; 6078} 6079 6080#undef po_char_or_fail 6081#undef po_reg_or_fail 6082#undef po_reg_or_goto 6083#undef po_imm_or_fail 6084#undef po_scalar_or_fail 6085 6086/* Shorthand macro for instruction encoding functions issuing errors. */ 6087#define constraint(expr, err) do { \ 6088 if (expr) \ 6089 { \ 6090 inst.error = err; \ 6091 return; \ 6092 } \ 6093} while (0) 6094 6095/* Functions for operand encoding. ARM, then Thumb. */ 6096 6097#define rotate_left(v, n) (v << (n % 32) | v >> ((32 - n) % 32)) 6098 6099/* If VAL can be encoded in the immediate field of an ARM instruction, 6100 return the encoded form. Otherwise, return FAIL. */ 6101 6102static unsigned int 6103encode_arm_immediate (unsigned int val) 6104{ 6105 unsigned int a, i; 6106 6107 for (i = 0; i < 32; i += 2) 6108 if ((a = rotate_left (val, i)) <= 0xff) 6109 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */ 6110 6111 return FAIL; 6112} 6113 6114/* If VAL can be encoded in the immediate field of a Thumb32 instruction, 6115 return the encoded form. Otherwise, return FAIL. */ 6116static unsigned int 6117encode_thumb32_immediate (unsigned int val) 6118{ 6119 unsigned int a, i; 6120 6121 if (val <= 0xff) 6122 return val; 6123 6124 for (i = 1; i <= 24; i++) 6125 { 6126 a = val >> i; 6127 if ((val & ~(0xff << i)) == 0) 6128 return ((val >> i) & 0x7f) | ((32 - i) << 7); 6129 } 6130 6131 a = val & 0xff; 6132 if (val == ((a << 16) | a)) 6133 return 0x100 | a; 6134 if (val == ((a << 24) | (a << 16) | (a << 8) | a)) 6135 return 0x300 | a; 6136 6137 a = val & 0xff00; 6138 if (val == ((a << 16) | a)) 6139 return 0x200 | (a >> 8); 6140 6141 return FAIL; 6142} 6143/* Encode a VFP SP or DP register number into inst.instruction. */ 6144 6145static void 6146encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos) 6147{ 6148 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm) 6149 && reg > 15) 6150 { 6151 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3)) 6152 { 6153 if (thumb_mode) 6154 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 6155 fpu_vfp_ext_v3); 6156 else 6157 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 6158 fpu_vfp_ext_v3); 6159 } 6160 else 6161 { 6162 first_error (_("D register out of range for selected VFP version")); 6163 return; 6164 } 6165 } 6166 6167 switch (pos) 6168 { 6169 case VFP_REG_Sd: 6170 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); 6171 break; 6172 6173 case VFP_REG_Sn: 6174 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); 6175 break; 6176 6177 case VFP_REG_Sm: 6178 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); 6179 break; 6180 6181 case VFP_REG_Dd: 6182 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); 6183 break; 6184 6185 case VFP_REG_Dn: 6186 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); 6187 break; 6188 6189 case VFP_REG_Dm: 6190 inst.instruction |= (reg & 15) | ((reg >> 4) << 5); 6191 break; 6192 6193 default: 6194 abort (); 6195 } 6196} 6197 6198/* Encode a <shift> in an ARM-format instruction. The immediate, 6199 if any, is handled by md_apply_fix. */ 6200static void 6201encode_arm_shift (int i) 6202{ 6203 if (inst.operands[i].shift_kind == SHIFT_RRX) 6204 inst.instruction |= SHIFT_ROR << 5; 6205 else 6206 { 6207 inst.instruction |= inst.operands[i].shift_kind << 5; 6208 if (inst.operands[i].immisreg) 6209 { 6210 inst.instruction |= SHIFT_BY_REG; 6211 inst.instruction |= inst.operands[i].imm << 8; 6212 } 6213 else 6214 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6215 } 6216} 6217 6218static void 6219encode_arm_shifter_operand (int i) 6220{ 6221 if (inst.operands[i].isreg) 6222 { 6223 inst.instruction |= inst.operands[i].reg; 6224 encode_arm_shift (i); 6225 } 6226 else 6227 inst.instruction |= INST_IMMEDIATE; 6228} 6229 6230/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */ 6231static void 6232encode_arm_addr_mode_common (int i, bfd_boolean is_t) 6233{ 6234 assert (inst.operands[i].isreg); 6235 inst.instruction |= inst.operands[i].reg << 16; 6236 6237 if (inst.operands[i].preind) 6238 { 6239 if (is_t) 6240 { 6241 inst.error = _("instruction does not accept preindexed addressing"); 6242 return; 6243 } 6244 inst.instruction |= PRE_INDEX; 6245 if (inst.operands[i].writeback) 6246 inst.instruction |= WRITE_BACK; 6247 6248 } 6249 else if (inst.operands[i].postind) 6250 { 6251 assert (inst.operands[i].writeback); 6252 if (is_t) 6253 inst.instruction |= WRITE_BACK; 6254 } 6255 else /* unindexed - only for coprocessor */ 6256 { 6257 inst.error = _("instruction does not accept unindexed addressing"); 6258 return; 6259 } 6260 6261 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX)) 6262 && (((inst.instruction & 0x000f0000) >> 16) 6263 == ((inst.instruction & 0x0000f000) >> 12))) 6264 as_warn ((inst.instruction & LOAD_BIT) 6265 ? _("destination register same as write-back base") 6266 : _("source register same as write-back base")); 6267} 6268 6269/* inst.operands[i] was set up by parse_address. Encode it into an 6270 ARM-format mode 2 load or store instruction. If is_t is true, 6271 reject forms that cannot be used with a T instruction (i.e. not 6272 post-indexed). */ 6273static void 6274encode_arm_addr_mode_2 (int i, bfd_boolean is_t) 6275{ 6276 encode_arm_addr_mode_common (i, is_t); 6277 6278 if (inst.operands[i].immisreg) 6279 { 6280 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */ 6281 inst.instruction |= inst.operands[i].imm; 6282 if (!inst.operands[i].negative) 6283 inst.instruction |= INDEX_UP; 6284 if (inst.operands[i].shifted) 6285 { 6286 if (inst.operands[i].shift_kind == SHIFT_RRX) 6287 inst.instruction |= SHIFT_ROR << 5; 6288 else 6289 { 6290 inst.instruction |= inst.operands[i].shift_kind << 5; 6291 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 6292 } 6293 } 6294 } 6295 else /* immediate offset in inst.reloc */ 6296 { 6297 if (inst.reloc.type == BFD_RELOC_UNUSED) 6298 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; 6299 } 6300} 6301 6302/* inst.operands[i] was set up by parse_address. Encode it into an 6303 ARM-format mode 3 load or store instruction. Reject forms that 6304 cannot be used with such instructions. If is_t is true, reject 6305 forms that cannot be used with a T instruction (i.e. not 6306 post-indexed). */ 6307static void 6308encode_arm_addr_mode_3 (int i, bfd_boolean is_t) 6309{ 6310 if (inst.operands[i].immisreg && inst.operands[i].shifted) 6311 { 6312 inst.error = _("instruction does not accept scaled register index"); 6313 return; 6314 } 6315 6316 encode_arm_addr_mode_common (i, is_t); 6317 6318 if (inst.operands[i].immisreg) 6319 { 6320 inst.instruction |= inst.operands[i].imm; 6321 if (!inst.operands[i].negative) 6322 inst.instruction |= INDEX_UP; 6323 } 6324 else /* immediate offset in inst.reloc */ 6325 { 6326 inst.instruction |= HWOFFSET_IMM; 6327 if (inst.reloc.type == BFD_RELOC_UNUSED) 6328 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; 6329 } 6330} 6331 6332/* inst.operands[i] was set up by parse_address. Encode it into an 6333 ARM-format instruction. Reject all forms which cannot be encoded 6334 into a coprocessor load/store instruction. If wb_ok is false, 6335 reject use of writeback; if unind_ok is false, reject use of 6336 unindexed addressing. If reloc_override is not 0, use it instead 6337 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one 6338 (in which case it is preserved). */ 6339 6340static int 6341encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override) 6342{ 6343 inst.instruction |= inst.operands[i].reg << 16; 6344 6345 assert (!(inst.operands[i].preind && inst.operands[i].postind)); 6346 6347 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */ 6348 { 6349 assert (!inst.operands[i].writeback); 6350 if (!unind_ok) 6351 { 6352 inst.error = _("instruction does not support unindexed addressing"); 6353 return FAIL; 6354 } 6355 inst.instruction |= inst.operands[i].imm; 6356 inst.instruction |= INDEX_UP; 6357 return SUCCESS; 6358 } 6359 6360 if (inst.operands[i].preind) 6361 inst.instruction |= PRE_INDEX; 6362 6363 if (inst.operands[i].writeback) 6364 { 6365 if (inst.operands[i].reg == REG_PC) 6366 { 6367 inst.error = _("pc may not be used with write-back"); 6368 return FAIL; 6369 } 6370 if (!wb_ok) 6371 { 6372 inst.error = _("instruction does not support writeback"); 6373 return FAIL; 6374 } 6375 inst.instruction |= WRITE_BACK; 6376 } 6377 6378 if (reloc_override) 6379 inst.reloc.type = reloc_override; 6380 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC 6381 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2) 6382 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0) 6383 { 6384 if (thumb_mode) 6385 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM; 6386 else 6387 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; 6388 } 6389 6390 return SUCCESS; 6391} 6392 6393/* inst.reloc.exp describes an "=expr" load pseudo-operation. 6394 Determine whether it can be performed with a move instruction; if 6395 it can, convert inst.instruction to that move instruction and 6396 return 1; if it can't, convert inst.instruction to a literal-pool 6397 load and return 0. If this is not a valid thing to do in the 6398 current context, set inst.error and return 1. 6399 6400 inst.operands[i] describes the destination register. */ 6401 6402static int 6403move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3) 6404{ 6405 unsigned long tbit; 6406 6407 if (thumb_p) 6408 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT; 6409 else 6410 tbit = LOAD_BIT; 6411 6412 if ((inst.instruction & tbit) == 0) 6413 { 6414 inst.error = _("invalid pseudo operation"); 6415 return 1; 6416 } 6417 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol) 6418 { 6419 inst.error = _("constant expression expected"); 6420 return 1; 6421 } 6422 if (inst.reloc.exp.X_op == O_constant) 6423 { 6424 if (thumb_p) 6425 { 6426 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0) 6427 { 6428 /* This can be done with a mov(1) instruction. */ 6429 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8); 6430 inst.instruction |= inst.reloc.exp.X_add_number; 6431 return 1; 6432 } 6433 } 6434 else 6435 { 6436 int value = encode_arm_immediate (inst.reloc.exp.X_add_number); 6437 if (value != FAIL) 6438 { 6439 /* This can be done with a mov instruction. */ 6440 inst.instruction &= LITERAL_MASK; 6441 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT); 6442 inst.instruction |= value & 0xfff; 6443 return 1; 6444 } 6445 6446 value = encode_arm_immediate (~inst.reloc.exp.X_add_number); 6447 if (value != FAIL) 6448 { 6449 /* This can be done with a mvn instruction. */ 6450 inst.instruction &= LITERAL_MASK; 6451 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT); 6452 inst.instruction |= value & 0xfff; 6453 return 1; 6454 } 6455 } 6456 } 6457 6458 if (add_to_lit_pool () == FAIL) 6459 { 6460 inst.error = _("literal pool insertion failed"); 6461 return 1; 6462 } 6463 inst.operands[1].reg = REG_PC; 6464 inst.operands[1].isreg = 1; 6465 inst.operands[1].preind = 1; 6466 inst.reloc.pc_rel = 1; 6467 inst.reloc.type = (thumb_p 6468 ? BFD_RELOC_ARM_THUMB_OFFSET 6469 : (mode_3 6470 ? BFD_RELOC_ARM_HWLITERAL 6471 : BFD_RELOC_ARM_LITERAL)); 6472 return 0; 6473} 6474 6475/* Functions for instruction encoding, sorted by subarchitecture. 6476 First some generics; their names are taken from the conventional 6477 bit positions for register arguments in ARM format instructions. */ 6478 6479static void 6480do_noargs (void) 6481{ 6482} 6483 6484static void 6485do_rd (void) 6486{ 6487 inst.instruction |= inst.operands[0].reg << 12; 6488} 6489 6490static void 6491do_rd_rm (void) 6492{ 6493 inst.instruction |= inst.operands[0].reg << 12; 6494 inst.instruction |= inst.operands[1].reg; 6495} 6496 6497static void 6498do_rd_rn (void) 6499{ 6500 inst.instruction |= inst.operands[0].reg << 12; 6501 inst.instruction |= inst.operands[1].reg << 16; 6502} 6503 6504static void 6505do_rn_rd (void) 6506{ 6507 inst.instruction |= inst.operands[0].reg << 16; 6508 inst.instruction |= inst.operands[1].reg << 12; 6509} 6510 6511static void 6512do_rd_rm_rn (void) 6513{ 6514 unsigned Rn = inst.operands[2].reg; 6515 /* Enforce restrictions on SWP instruction. */ 6516 if ((inst.instruction & 0x0fbfffff) == 0x01000090) 6517 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, 6518 _("Rn must not overlap other operands")); 6519 inst.instruction |= inst.operands[0].reg << 12; 6520 inst.instruction |= inst.operands[1].reg; 6521 inst.instruction |= Rn << 16; 6522} 6523 6524static void 6525do_rd_rn_rm (void) 6526{ 6527 inst.instruction |= inst.operands[0].reg << 12; 6528 inst.instruction |= inst.operands[1].reg << 16; 6529 inst.instruction |= inst.operands[2].reg; 6530} 6531 6532static void 6533do_rm_rd_rn (void) 6534{ 6535 inst.instruction |= inst.operands[0].reg; 6536 inst.instruction |= inst.operands[1].reg << 12; 6537 inst.instruction |= inst.operands[2].reg << 16; 6538} 6539 6540static void 6541do_imm0 (void) 6542{ 6543 inst.instruction |= inst.operands[0].imm; 6544} 6545 6546static void 6547do_rd_cpaddr (void) 6548{ 6549 inst.instruction |= inst.operands[0].reg << 12; 6550 encode_arm_cp_address (1, TRUE, TRUE, 0); 6551} 6552 6553/* ARM instructions, in alphabetical order by function name (except 6554 that wrapper functions appear immediately after the function they 6555 wrap). */ 6556 6557/* This is a pseudo-op of the form "adr rd, label" to be converted 6558 into a relative address of the form "add rd, pc, #label-.-8". */ 6559 6560static void 6561do_adr (void) 6562{ 6563 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6564 6565 /* Frag hacking will turn this into a sub instruction if the offset turns 6566 out to be negative. */ 6567 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 6568 inst.reloc.pc_rel = 1; 6569 inst.reloc.exp.X_add_number -= 8; 6570} 6571 6572/* This is a pseudo-op of the form "adrl rd, label" to be converted 6573 into a relative address of the form: 6574 add rd, pc, #low(label-.-8)" 6575 add rd, rd, #high(label-.-8)" */ 6576 6577static void 6578do_adrl (void) 6579{ 6580 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */ 6581 6582 /* Frag hacking will turn this into a sub instruction if the offset turns 6583 out to be negative. */ 6584 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; 6585 inst.reloc.pc_rel = 1; 6586 inst.size = INSN_SIZE * 2; 6587 inst.reloc.exp.X_add_number -= 8; 6588} 6589 6590static void 6591do_arit (void) 6592{ 6593 if (!inst.operands[1].present) 6594 inst.operands[1].reg = inst.operands[0].reg; 6595 inst.instruction |= inst.operands[0].reg << 12; 6596 inst.instruction |= inst.operands[1].reg << 16; 6597 encode_arm_shifter_operand (2); 6598} 6599 6600static void 6601do_barrier (void) 6602{ 6603 if (inst.operands[0].present) 6604 { 6605 constraint ((inst.instruction & 0xf0) != 0x40 6606 && inst.operands[0].imm != 0xf, 6607 "bad barrier type"); 6608 inst.instruction |= inst.operands[0].imm; 6609 } 6610 else 6611 inst.instruction |= 0xf; 6612} 6613 6614static void 6615do_bfc (void) 6616{ 6617 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 6618 constraint (msb > 32, _("bit-field extends past end of register")); 6619 /* The instruction encoding stores the LSB and MSB, 6620 not the LSB and width. */ 6621 inst.instruction |= inst.operands[0].reg << 12; 6622 inst.instruction |= inst.operands[1].imm << 7; 6623 inst.instruction |= (msb - 1) << 16; 6624} 6625 6626static void 6627do_bfi (void) 6628{ 6629 unsigned int msb; 6630 6631 /* #0 in second position is alternative syntax for bfc, which is 6632 the same instruction but with REG_PC in the Rm field. */ 6633 if (!inst.operands[1].isreg) 6634 inst.operands[1].reg = REG_PC; 6635 6636 msb = inst.operands[2].imm + inst.operands[3].imm; 6637 constraint (msb > 32, _("bit-field extends past end of register")); 6638 /* The instruction encoding stores the LSB and MSB, 6639 not the LSB and width. */ 6640 inst.instruction |= inst.operands[0].reg << 12; 6641 inst.instruction |= inst.operands[1].reg; 6642 inst.instruction |= inst.operands[2].imm << 7; 6643 inst.instruction |= (msb - 1) << 16; 6644} 6645 6646static void 6647do_bfx (void) 6648{ 6649 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 6650 _("bit-field extends past end of register")); 6651 inst.instruction |= inst.operands[0].reg << 12; 6652 inst.instruction |= inst.operands[1].reg; 6653 inst.instruction |= inst.operands[2].imm << 7; 6654 inst.instruction |= (inst.operands[3].imm - 1) << 16; 6655} 6656 6657/* ARM V5 breakpoint instruction (argument parse) 6658 BKPT <16 bit unsigned immediate> 6659 Instruction is not conditional. 6660 The bit pattern given in insns[] has the COND_ALWAYS condition, 6661 and it is an error if the caller tried to override that. */ 6662 6663static void 6664do_bkpt (void) 6665{ 6666 /* Top 12 of 16 bits to bits 19:8. */ 6667 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4; 6668 6669 /* Bottom 4 of 16 bits to bits 3:0. */ 6670 inst.instruction |= inst.operands[0].imm & 0xf; 6671} 6672 6673static void 6674encode_branch (int default_reloc) 6675{ 6676 if (inst.operands[0].hasreloc) 6677 { 6678 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, 6679 _("the only suffix valid here is '(plt)'")); 6680 inst.reloc.type = BFD_RELOC_ARM_PLT32; 6681 } 6682 else 6683 { 6684 inst.reloc.type = default_reloc; 6685 } 6686 inst.reloc.pc_rel = 1; 6687} 6688 6689static void 6690do_branch (void) 6691{ 6692#ifdef OBJ_ELF 6693 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6694 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6695 else 6696#endif 6697 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6698} 6699 6700static void 6701do_bl (void) 6702{ 6703#ifdef OBJ_ELF 6704 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6705 { 6706 if (inst.cond == COND_ALWAYS) 6707 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6708 else 6709 encode_branch (BFD_RELOC_ARM_PCREL_JUMP); 6710 } 6711 else 6712#endif 6713 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH); 6714} 6715 6716/* ARM V5 branch-link-exchange instruction (argument parse) 6717 BLX <target_addr> ie BLX(1) 6718 BLX{<condition>} <Rm> ie BLX(2) 6719 Unfortunately, there are two different opcodes for this mnemonic. 6720 So, the insns[].value is not used, and the code here zaps values 6721 into inst.instruction. 6722 Also, the <target_addr> can be 25 bits, hence has its own reloc. */ 6723 6724static void 6725do_blx (void) 6726{ 6727 if (inst.operands[0].isreg) 6728 { 6729 /* Arg is a register; the opcode provided by insns[] is correct. 6730 It is not illegal to do "blx pc", just useless. */ 6731 if (inst.operands[0].reg == REG_PC) 6732 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful")); 6733 6734 inst.instruction |= inst.operands[0].reg; 6735 } 6736 else 6737 { 6738 /* Arg is an address; this instruction cannot be executed 6739 conditionally, and the opcode must be adjusted. */ 6740 constraint (inst.cond != COND_ALWAYS, BAD_COND); 6741 inst.instruction = 0xfa000000; 6742#ifdef OBJ_ELF 6743 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 6744 encode_branch (BFD_RELOC_ARM_PCREL_CALL); 6745 else 6746#endif 6747 encode_branch (BFD_RELOC_ARM_PCREL_BLX); 6748 } 6749} 6750 6751static void 6752do_bx (void) 6753{ 6754 if (inst.operands[0].reg == REG_PC) 6755 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful")); 6756 6757 inst.instruction |= inst.operands[0].reg; 6758} 6759 6760 6761/* ARM v5TEJ. Jump to Jazelle code. */ 6762 6763static void 6764do_bxj (void) 6765{ 6766 if (inst.operands[0].reg == REG_PC) 6767 as_tsktsk (_("use of r15 in bxj is not really useful")); 6768 6769 inst.instruction |= inst.operands[0].reg; 6770} 6771 6772/* Co-processor data operation: 6773 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} 6774 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */ 6775static void 6776do_cdp (void) 6777{ 6778 inst.instruction |= inst.operands[0].reg << 8; 6779 inst.instruction |= inst.operands[1].imm << 20; 6780 inst.instruction |= inst.operands[2].reg << 12; 6781 inst.instruction |= inst.operands[3].reg << 16; 6782 inst.instruction |= inst.operands[4].reg; 6783 inst.instruction |= inst.operands[5].imm << 5; 6784} 6785 6786static void 6787do_cmp (void) 6788{ 6789 inst.instruction |= inst.operands[0].reg << 16; 6790 encode_arm_shifter_operand (1); 6791} 6792 6793/* Transfer between coprocessor and ARM registers. 6794 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>} 6795 MRC2 6796 MCR{cond} 6797 MCR2 6798 6799 No special properties. */ 6800 6801static void 6802do_co_reg (void) 6803{ 6804 inst.instruction |= inst.operands[0].reg << 8; 6805 inst.instruction |= inst.operands[1].imm << 21; 6806 /* If this is a vector we are using the APSR_nzcv syntax, encode as r15 */ 6807 if (inst.operands[2].isvec != 0) 6808 inst.instruction |= 15 << 12; 6809 else 6810 inst.instruction |= inst.operands[2].reg << 12; 6811 inst.instruction |= inst.operands[3].reg << 16; 6812 inst.instruction |= inst.operands[4].reg; 6813 inst.instruction |= inst.operands[5].imm << 5; 6814} 6815 6816/* Transfer between coprocessor register and pair of ARM registers. 6817 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>. 6818 MCRR2 6819 MRRC{cond} 6820 MRRC2 6821 6822 Two XScale instructions are special cases of these: 6823 6824 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0 6825 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0 6826 6827 Result unpredicatable if Rd or Rn is R15. */ 6828 6829static void 6830do_co_reg2c (void) 6831{ 6832 inst.instruction |= inst.operands[0].reg << 8; 6833 inst.instruction |= inst.operands[1].imm << 4; 6834 inst.instruction |= inst.operands[2].reg << 12; 6835 inst.instruction |= inst.operands[3].reg << 16; 6836 inst.instruction |= inst.operands[4].reg; 6837} 6838 6839static void 6840do_cpsi (void) 6841{ 6842 inst.instruction |= inst.operands[0].imm << 6; 6843 if (inst.operands[1].present) 6844 { 6845 inst.instruction |= CPSI_MMOD; 6846 inst.instruction |= inst.operands[1].imm; 6847 } 6848} 6849 6850static void 6851do_dbg (void) 6852{ 6853 inst.instruction |= inst.operands[0].imm; 6854} 6855 6856static void 6857do_it (void) 6858{ 6859 /* There is no IT instruction in ARM mode. We 6860 process it but do not generate code for it. */ 6861 inst.size = 0; 6862} 6863 6864static void 6865do_ldmstm (void) 6866{ 6867 int base_reg = inst.operands[0].reg; 6868 int range = inst.operands[1].imm; 6869 6870 inst.instruction |= base_reg << 16; 6871 inst.instruction |= range; 6872 6873 if (inst.operands[1].writeback) 6874 inst.instruction |= LDM_TYPE_2_OR_3; 6875 6876 if (inst.operands[0].writeback) 6877 { 6878 inst.instruction |= WRITE_BACK; 6879 /* Check for unpredictable uses of writeback. */ 6880 if (inst.instruction & LOAD_BIT) 6881 { 6882 /* Not allowed in LDM type 2. */ 6883 if ((inst.instruction & LDM_TYPE_2_OR_3) 6884 && ((range & (1 << REG_PC)) == 0)) 6885 as_warn (_("writeback of base register is UNPREDICTABLE")); 6886 /* Only allowed if base reg not in list for other types. */ 6887 else if (range & (1 << base_reg)) 6888 as_warn (_("writeback of base register when in register list is UNPREDICTABLE")); 6889 } 6890 else /* STM. */ 6891 { 6892 /* Not allowed for type 2. */ 6893 if (inst.instruction & LDM_TYPE_2_OR_3) 6894 as_warn (_("writeback of base register is UNPREDICTABLE")); 6895 /* Only allowed if base reg not in list, or first in list. */ 6896 else if ((range & (1 << base_reg)) 6897 && (range & ((1 << base_reg) - 1))) 6898 as_warn (_("if writeback register is in list, it must be the lowest reg in the list")); 6899 } 6900 } 6901} 6902 6903/* ARMv5TE load-consecutive (argument parse) 6904 Mode is like LDRH. 6905 6906 LDRccD R, mode 6907 STRccD R, mode. */ 6908 6909static void 6910do_ldrd (void) 6911{ 6912 constraint (inst.operands[0].reg % 2 != 0, 6913 _("first destination register must be even")); 6914 constraint (inst.operands[1].present 6915 && inst.operands[1].reg != inst.operands[0].reg + 1, 6916 _("can only load two consecutive registers")); 6917 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6918 constraint (!inst.operands[2].isreg, _("'[' expected")); 6919 6920 if (!inst.operands[1].present) 6921 inst.operands[1].reg = inst.operands[0].reg + 1; 6922 6923 if (inst.instruction & LOAD_BIT) 6924 { 6925 /* encode_arm_addr_mode_3 will diagnose overlap between the base 6926 register and the first register written; we have to diagnose 6927 overlap between the base and the second register written here. */ 6928 6929 if (inst.operands[2].reg == inst.operands[1].reg 6930 && (inst.operands[2].writeback || inst.operands[2].postind)) 6931 as_warn (_("base register written back, and overlaps " 6932 "second destination register")); 6933 6934 /* For an index-register load, the index register must not overlap the 6935 destination (even if not write-back). */ 6936 else if (inst.operands[2].immisreg 6937 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg 6938 || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) 6939 as_warn (_("index register overlaps destination register")); 6940 } 6941 6942 inst.instruction |= inst.operands[0].reg << 12; 6943 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE); 6944} 6945 6946static void 6947do_ldrex (void) 6948{ 6949 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 6950 || inst.operands[1].postind || inst.operands[1].writeback 6951 || inst.operands[1].immisreg || inst.operands[1].shifted 6952 || inst.operands[1].negative 6953 /* This can arise if the programmer has written 6954 strex rN, rM, foo 6955 or if they have mistakenly used a register name as the last 6956 operand, eg: 6957 strex rN, rM, rX 6958 It is very difficult to distinguish between these two cases 6959 because "rX" might actually be a label. ie the register 6960 name has been occluded by a symbol of the same name. So we 6961 just generate a general 'bad addressing mode' type error 6962 message and leave it up to the programmer to discover the 6963 true cause and fix their mistake. */ 6964 || (inst.operands[1].reg == REG_PC), 6965 BAD_ADDR_MODE); 6966 6967 constraint (inst.reloc.exp.X_op != O_constant 6968 || inst.reloc.exp.X_add_number != 0, 6969 _("offset must be zero in ARM encoding")); 6970 6971 inst.instruction |= inst.operands[0].reg << 12; 6972 inst.instruction |= inst.operands[1].reg << 16; 6973 inst.reloc.type = BFD_RELOC_UNUSED; 6974} 6975 6976static void 6977do_ldrexd (void) 6978{ 6979 constraint (inst.operands[0].reg % 2 != 0, 6980 _("even register required")); 6981 constraint (inst.operands[1].present 6982 && inst.operands[1].reg != inst.operands[0].reg + 1, 6983 _("can only load two consecutive registers")); 6984 /* If op 1 were present and equal to PC, this function wouldn't 6985 have been called in the first place. */ 6986 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here")); 6987 6988 inst.instruction |= inst.operands[0].reg << 12; 6989 inst.instruction |= inst.operands[2].reg << 16; 6990} 6991 6992static void 6993do_ldst (void) 6994{ 6995 inst.instruction |= inst.operands[0].reg << 12; 6996 if (!inst.operands[1].isreg) 6997 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE)) 6998 return; 6999 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE); 7000} 7001 7002static void 7003do_ldstt (void) 7004{ 7005 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 7006 reject [Rn,...]. */ 7007 if (inst.operands[1].preind) 7008 { 7009 constraint (inst.reloc.exp.X_op != O_constant || 7010 inst.reloc.exp.X_add_number != 0, 7011 _("this instruction requires a post-indexed address")); 7012 7013 inst.operands[1].preind = 0; 7014 inst.operands[1].postind = 1; 7015 inst.operands[1].writeback = 1; 7016 } 7017 inst.instruction |= inst.operands[0].reg << 12; 7018 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE); 7019} 7020 7021/* Halfword and signed-byte load/store operations. */ 7022 7023static void 7024do_ldstv4 (void) 7025{ 7026 inst.instruction |= inst.operands[0].reg << 12; 7027 if (!inst.operands[1].isreg) 7028 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE)) 7029 return; 7030 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE); 7031} 7032 7033static void 7034do_ldsttv4 (void) 7035{ 7036 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and 7037 reject [Rn,...]. */ 7038 if (inst.operands[1].preind) 7039 { 7040 constraint (inst.reloc.exp.X_op != O_constant || 7041 inst.reloc.exp.X_add_number != 0, 7042 _("this instruction requires a post-indexed address")); 7043 7044 inst.operands[1].preind = 0; 7045 inst.operands[1].postind = 1; 7046 inst.operands[1].writeback = 1; 7047 } 7048 inst.instruction |= inst.operands[0].reg << 12; 7049 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE); 7050} 7051 7052/* Co-processor register load/store. 7053 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */ 7054static void 7055do_lstc (void) 7056{ 7057 inst.instruction |= inst.operands[0].reg << 8; 7058 inst.instruction |= inst.operands[1].reg << 12; 7059 encode_arm_cp_address (2, TRUE, TRUE, 0); 7060} 7061 7062static void 7063do_mlas (void) 7064{ 7065 /* This restriction does not apply to mls (nor to mla in v6 or later). */ 7066 if (inst.operands[0].reg == inst.operands[1].reg 7067 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6) 7068 && !(inst.instruction & 0x00400000)) 7069 as_tsktsk (_("Rd and Rm should be different in mla")); 7070 7071 inst.instruction |= inst.operands[0].reg << 16; 7072 inst.instruction |= inst.operands[1].reg; 7073 inst.instruction |= inst.operands[2].reg << 8; 7074 inst.instruction |= inst.operands[3].reg << 12; 7075} 7076 7077static void 7078do_mov (void) 7079{ 7080 inst.instruction |= inst.operands[0].reg << 12; 7081 encode_arm_shifter_operand (1); 7082} 7083 7084/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */ 7085static void 7086do_mov16 (void) 7087{ 7088 bfd_vma imm; 7089 bfd_boolean top; 7090 7091 top = (inst.instruction & 0x00400000) != 0; 7092 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW, 7093 _(":lower16: not allowed this instruction")); 7094 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT, 7095 _(":upper16: not allowed instruction")); 7096 inst.instruction |= inst.operands[0].reg << 12; 7097 if (inst.reloc.type == BFD_RELOC_UNUSED) 7098 { 7099 imm = inst.reloc.exp.X_add_number; 7100 /* The value is in two pieces: 0:11, 16:19. */ 7101 inst.instruction |= (imm & 0x00000fff); 7102 inst.instruction |= (imm & 0x0000f000) << 4; 7103 } 7104} 7105 7106static void do_vfp_nsyn_opcode (const char *); 7107 7108static int 7109do_vfp_nsyn_mrs (void) 7110{ 7111 if (inst.operands[0].isvec) 7112 { 7113 if (inst.operands[1].reg != 1) 7114 first_error (_("operand 1 must be FPSCR")); 7115 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 7116 memset (&inst.operands[1], '\0', sizeof (inst.operands[1])); 7117 do_vfp_nsyn_opcode ("fmstat"); 7118 } 7119 else if (inst.operands[1].isvec) 7120 do_vfp_nsyn_opcode ("fmrx"); 7121 else 7122 return FAIL; 7123 7124 return SUCCESS; 7125} 7126 7127static int 7128do_vfp_nsyn_msr (void) 7129{ 7130 if (inst.operands[0].isvec) 7131 do_vfp_nsyn_opcode ("fmxr"); 7132 else 7133 return FAIL; 7134 7135 return SUCCESS; 7136} 7137 7138static void 7139do_vfp_vmrs (void) 7140{ 7141 int rt; 7142 7143 /* The destination register can be r0-r14 or APSR_nzcv */ 7144 if (inst.operands[0].reg > 14) 7145 { 7146 inst.error = BAD_PC; 7147 return; 7148 } 7149 7150 /* If the destination is r13 and not in ARM mode then unprefictable */ 7151 if (thumb_mode && inst.operands[0].reg == REG_SP) 7152 { 7153 inst.error = BAD_SP; 7154 return; 7155 } 7156 7157 /* If the destination is APSR_nzcv */ 7158 if (inst.operands[0].isvec && inst.operands[1].reg != 1) 7159 { 7160 inst.error = BAD_VMRS; 7161 return; 7162 } 7163 7164 if (inst.operands[0].isvec) 7165 rt = 15; 7166 else 7167 rt = inst.operands[0].reg; 7168 7169 /* Or in the registers to use */ 7170 inst.instruction |= rt << 12; 7171 inst.instruction |= inst.operands[1].reg << 16; 7172} 7173 7174static void 7175do_vfp_vmsr (void) 7176{ 7177 /* The destination register can be r0-r14 or APSR_nzcv */ 7178 if (inst.operands[1].reg > 14) 7179 { 7180 inst.error = BAD_PC; 7181 return; 7182 } 7183 7184 /* If the destination is r13 and not in ARM mode then unprefictable */ 7185 if (thumb_mode && inst.operands[0].reg == REG_SP) 7186 { 7187 inst.error = BAD_SP; 7188 return; 7189 } 7190 7191 /* Or in the registers to use */ 7192 inst.instruction |= inst.operands[1].reg << 12; 7193 inst.instruction |= inst.operands[0].reg << 16; 7194} 7195 7196static void 7197do_mrs (void) 7198{ 7199 if (do_vfp_nsyn_mrs () == SUCCESS) 7200 return; 7201 7202 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 7203 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f)) 7204 != (PSR_c|PSR_f), 7205 _("'CPSR' or 'SPSR' expected")); 7206 inst.instruction |= inst.operands[0].reg << 12; 7207 inst.instruction |= (inst.operands[1].imm & SPSR_BIT); 7208} 7209 7210/* Two possible forms: 7211 "{C|S}PSR_<field>, Rm", 7212 "{C|S}PSR_f, #expression". */ 7213 7214static void 7215do_msr (void) 7216{ 7217 if (do_vfp_nsyn_msr () == SUCCESS) 7218 return; 7219 7220 inst.instruction |= inst.operands[0].imm; 7221 if (inst.operands[1].isreg) 7222 inst.instruction |= inst.operands[1].reg; 7223 else 7224 { 7225 inst.instruction |= INST_IMMEDIATE; 7226 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; 7227 inst.reloc.pc_rel = 0; 7228 } 7229} 7230 7231static void 7232do_mul (void) 7233{ 7234 if (!inst.operands[2].present) 7235 inst.operands[2].reg = inst.operands[0].reg; 7236 inst.instruction |= inst.operands[0].reg << 16; 7237 inst.instruction |= inst.operands[1].reg; 7238 inst.instruction |= inst.operands[2].reg << 8; 7239 7240 if (inst.operands[0].reg == inst.operands[1].reg 7241 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)) 7242 as_tsktsk (_("Rd and Rm should be different in mul")); 7243} 7244 7245/* Long Multiply Parser 7246 UMULL RdLo, RdHi, Rm, Rs 7247 SMULL RdLo, RdHi, Rm, Rs 7248 UMLAL RdLo, RdHi, Rm, Rs 7249 SMLAL RdLo, RdHi, Rm, Rs. */ 7250 7251static void 7252do_mull (void) 7253{ 7254 inst.instruction |= inst.operands[0].reg << 12; 7255 inst.instruction |= inst.operands[1].reg << 16; 7256 inst.instruction |= inst.operands[2].reg; 7257 inst.instruction |= inst.operands[3].reg << 8; 7258 7259 /* rdhi, rdlo and rm must all be different prior to ARMv6. */ 7260 if (inst.operands[0].reg == inst.operands[1].reg 7261 || ((inst.operands[0].reg == inst.operands[2].reg 7262 || inst.operands[1].reg == inst.operands[2].reg) 7263 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))) 7264 as_tsktsk (_("rdhi, rdlo and rm must all be different")); 7265} 7266 7267static void 7268do_nop (void) 7269{ 7270 if (inst.operands[0].present) 7271 { 7272 /* Architectural NOP hints are CPSR sets with no bits selected. */ 7273 inst.instruction &= 0xf0000000; 7274 inst.instruction |= 0x0320f000 + inst.operands[0].imm; 7275 } 7276} 7277 7278/* ARM V6 Pack Halfword Bottom Top instruction (argument parse). 7279 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} 7280 Condition defaults to COND_ALWAYS. 7281 Error if Rd, Rn or Rm are R15. */ 7282 7283static void 7284do_pkhbt (void) 7285{ 7286 inst.instruction |= inst.operands[0].reg << 12; 7287 inst.instruction |= inst.operands[1].reg << 16; 7288 inst.instruction |= inst.operands[2].reg; 7289 if (inst.operands[3].present) 7290 encode_arm_shift (3); 7291} 7292 7293/* ARM V6 PKHTB (Argument Parse). */ 7294 7295static void 7296do_pkhtb (void) 7297{ 7298 if (!inst.operands[3].present) 7299 { 7300 /* If the shift specifier is omitted, turn the instruction 7301 into pkhbt rd, rm, rn. */ 7302 inst.instruction &= 0xfff00010; 7303 inst.instruction |= inst.operands[0].reg << 12; 7304 inst.instruction |= inst.operands[1].reg; 7305 inst.instruction |= inst.operands[2].reg << 16; 7306 } 7307 else 7308 { 7309 inst.instruction |= inst.operands[0].reg << 12; 7310 inst.instruction |= inst.operands[1].reg << 16; 7311 inst.instruction |= inst.operands[2].reg; 7312 encode_arm_shift (3); 7313 } 7314} 7315 7316/* ARMv5TE: Preload-Cache 7317 7318 PLD <addr_mode> 7319 7320 Syntactically, like LDR with B=1, W=0, L=1. */ 7321 7322static void 7323do_pld (void) 7324{ 7325 constraint (!inst.operands[0].isreg, 7326 _("'[' expected after PLD mnemonic")); 7327 constraint (inst.operands[0].postind, 7328 _("post-indexed expression used in preload instruction")); 7329 constraint (inst.operands[0].writeback, 7330 _("writeback used in preload instruction")); 7331 constraint (!inst.operands[0].preind, 7332 _("unindexed addressing used in preload instruction")); 7333 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7334} 7335 7336/* ARMv7: PLI <addr_mode> */ 7337static void 7338do_pli (void) 7339{ 7340 constraint (!inst.operands[0].isreg, 7341 _("'[' expected after PLI mnemonic")); 7342 constraint (inst.operands[0].postind, 7343 _("post-indexed expression used in preload instruction")); 7344 constraint (inst.operands[0].writeback, 7345 _("writeback used in preload instruction")); 7346 constraint (!inst.operands[0].preind, 7347 _("unindexed addressing used in preload instruction")); 7348 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE); 7349 inst.instruction &= ~PRE_INDEX; 7350} 7351 7352static void 7353do_push_pop (void) 7354{ 7355 inst.operands[1] = inst.operands[0]; 7356 memset (&inst.operands[0], 0, sizeof inst.operands[0]); 7357 inst.operands[0].isreg = 1; 7358 inst.operands[0].writeback = 1; 7359 inst.operands[0].reg = REG_SP; 7360 do_ldmstm (); 7361} 7362 7363/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the 7364 word at the specified address and the following word 7365 respectively. 7366 Unconditionally executed. 7367 Error if Rn is R15. */ 7368 7369static void 7370do_rfe (void) 7371{ 7372 inst.instruction |= inst.operands[0].reg << 16; 7373 if (inst.operands[0].writeback) 7374 inst.instruction |= WRITE_BACK; 7375} 7376 7377/* ARM V6 ssat (argument parse). */ 7378 7379static void 7380do_ssat (void) 7381{ 7382 inst.instruction |= inst.operands[0].reg << 12; 7383 inst.instruction |= (inst.operands[1].imm - 1) << 16; 7384 inst.instruction |= inst.operands[2].reg; 7385 7386 if (inst.operands[3].present) 7387 encode_arm_shift (3); 7388} 7389 7390/* ARM V6 usat (argument parse). */ 7391 7392static void 7393do_usat (void) 7394{ 7395 inst.instruction |= inst.operands[0].reg << 12; 7396 inst.instruction |= inst.operands[1].imm << 16; 7397 inst.instruction |= inst.operands[2].reg; 7398 7399 if (inst.operands[3].present) 7400 encode_arm_shift (3); 7401} 7402 7403/* ARM V6 ssat16 (argument parse). */ 7404 7405static void 7406do_ssat16 (void) 7407{ 7408 inst.instruction |= inst.operands[0].reg << 12; 7409 inst.instruction |= ((inst.operands[1].imm - 1) << 16); 7410 inst.instruction |= inst.operands[2].reg; 7411} 7412 7413static void 7414do_usat16 (void) 7415{ 7416 inst.instruction |= inst.operands[0].reg << 12; 7417 inst.instruction |= inst.operands[1].imm << 16; 7418 inst.instruction |= inst.operands[2].reg; 7419} 7420 7421/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while 7422 preserving the other bits. 7423 7424 setend <endian_specifier>, where <endian_specifier> is either 7425 BE or LE. */ 7426 7427static void 7428do_setend (void) 7429{ 7430 if (inst.operands[0].imm) 7431 inst.instruction |= 0x200; 7432} 7433 7434static void 7435do_shift (void) 7436{ 7437 unsigned int Rm = (inst.operands[1].present 7438 ? inst.operands[1].reg 7439 : inst.operands[0].reg); 7440 7441 inst.instruction |= inst.operands[0].reg << 12; 7442 inst.instruction |= Rm; 7443 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */ 7444 { 7445 inst.instruction |= inst.operands[2].reg << 8; 7446 inst.instruction |= SHIFT_BY_REG; 7447 } 7448 else 7449 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM; 7450} 7451 7452static void 7453do_smc (void) 7454{ 7455 inst.reloc.type = BFD_RELOC_ARM_SMC; 7456 inst.reloc.pc_rel = 0; 7457} 7458 7459static void 7460do_swi (void) 7461{ 7462 inst.reloc.type = BFD_RELOC_ARM_SWI; 7463 inst.reloc.pc_rel = 0; 7464} 7465 7466/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse) 7467 SMLAxy{cond} Rd,Rm,Rs,Rn 7468 SMLAWy{cond} Rd,Rm,Rs,Rn 7469 Error if any register is R15. */ 7470 7471static void 7472do_smla (void) 7473{ 7474 inst.instruction |= inst.operands[0].reg << 16; 7475 inst.instruction |= inst.operands[1].reg; 7476 inst.instruction |= inst.operands[2].reg << 8; 7477 inst.instruction |= inst.operands[3].reg << 12; 7478} 7479 7480/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse) 7481 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs 7482 Error if any register is R15. 7483 Warning if Rdlo == Rdhi. */ 7484 7485static void 7486do_smlal (void) 7487{ 7488 inst.instruction |= inst.operands[0].reg << 12; 7489 inst.instruction |= inst.operands[1].reg << 16; 7490 inst.instruction |= inst.operands[2].reg; 7491 inst.instruction |= inst.operands[3].reg << 8; 7492 7493 if (inst.operands[0].reg == inst.operands[1].reg) 7494 as_tsktsk (_("rdhi and rdlo must be different")); 7495} 7496 7497/* ARM V5E (El Segundo) signed-multiply (argument parse) 7498 SMULxy{cond} Rd,Rm,Rs 7499 Error if any register is R15. */ 7500 7501static void 7502do_smul (void) 7503{ 7504 inst.instruction |= inst.operands[0].reg << 16; 7505 inst.instruction |= inst.operands[1].reg; 7506 inst.instruction |= inst.operands[2].reg << 8; 7507} 7508 7509/* ARM V6 srs (argument parse). The variable fields in the encoding are 7510 the same for both ARM and Thumb-2. */ 7511 7512static void 7513do_srs (void) 7514{ 7515 int reg; 7516 7517 if (inst.operands[0].present) 7518 { 7519 reg = inst.operands[0].reg; 7520 constraint (reg != 13, _("SRS base register must be r13")); 7521 } 7522 else 7523 reg = 13; 7524 7525 inst.instruction |= reg << 16; 7526 inst.instruction |= inst.operands[1].imm; 7527 if (inst.operands[0].writeback || inst.operands[1].writeback) 7528 inst.instruction |= WRITE_BACK; 7529} 7530 7531/* ARM V6 strex (argument parse). */ 7532 7533static void 7534do_strex (void) 7535{ 7536 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 7537 || inst.operands[2].postind || inst.operands[2].writeback 7538 || inst.operands[2].immisreg || inst.operands[2].shifted 7539 || inst.operands[2].negative 7540 /* See comment in do_ldrex(). */ 7541 || (inst.operands[2].reg == REG_PC), 7542 BAD_ADDR_MODE); 7543 7544 constraint (inst.operands[0].reg == inst.operands[1].reg 7545 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); 7546 7547 constraint (inst.reloc.exp.X_op != O_constant 7548 || inst.reloc.exp.X_add_number != 0, 7549 _("offset must be zero in ARM encoding")); 7550 7551 inst.instruction |= inst.operands[0].reg << 12; 7552 inst.instruction |= inst.operands[1].reg; 7553 inst.instruction |= inst.operands[2].reg << 16; 7554 inst.reloc.type = BFD_RELOC_UNUSED; 7555} 7556 7557static void 7558do_strexd (void) 7559{ 7560 constraint (inst.operands[1].reg % 2 != 0, 7561 _("even register required")); 7562 constraint (inst.operands[2].present 7563 && inst.operands[2].reg != inst.operands[1].reg + 1, 7564 _("can only store two consecutive registers")); 7565 /* If op 2 were present and equal to PC, this function wouldn't 7566 have been called in the first place. */ 7567 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here")); 7568 7569 constraint (inst.operands[0].reg == inst.operands[1].reg 7570 || inst.operands[0].reg == inst.operands[1].reg + 1 7571 || inst.operands[0].reg == inst.operands[3].reg, 7572 BAD_OVERLAP); 7573 7574 inst.instruction |= inst.operands[0].reg << 12; 7575 inst.instruction |= inst.operands[1].reg; 7576 inst.instruction |= inst.operands[3].reg << 16; 7577} 7578 7579/* ARM V6 SXTAH extracts a 16-bit value from a register, sign 7580 extends it to 32-bits, and adds the result to a value in another 7581 register. You can specify a rotation by 0, 8, 16, or 24 bits 7582 before extracting the 16-bit value. 7583 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>} 7584 Condition defaults to COND_ALWAYS. 7585 Error if any register uses R15. */ 7586 7587static void 7588do_sxtah (void) 7589{ 7590 inst.instruction |= inst.operands[0].reg << 12; 7591 inst.instruction |= inst.operands[1].reg << 16; 7592 inst.instruction |= inst.operands[2].reg; 7593 inst.instruction |= inst.operands[3].imm << 10; 7594} 7595 7596/* ARM V6 SXTH. 7597 7598 SXTH {<cond>} <Rd>, <Rm>{, <rotation>} 7599 Condition defaults to COND_ALWAYS. 7600 Error if any register uses R15. */ 7601 7602static void 7603do_sxth (void) 7604{ 7605 inst.instruction |= inst.operands[0].reg << 12; 7606 inst.instruction |= inst.operands[1].reg; 7607 inst.instruction |= inst.operands[2].imm << 10; 7608} 7609 7610/* VFP instructions. In a logical order: SP variant first, monad 7611 before dyad, arithmetic then move then load/store. */ 7612 7613static void 7614do_vfp_sp_monadic (void) 7615{ 7616 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7617 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7618} 7619 7620static void 7621do_vfp_sp_dyadic (void) 7622{ 7623 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7624 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7625 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7626} 7627 7628static void 7629do_vfp_sp_compare_z (void) 7630{ 7631 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7632} 7633 7634static void 7635do_vfp_dp_sp_cvt (void) 7636{ 7637 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7638 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); 7639} 7640 7641static void 7642do_vfp_sp_dp_cvt (void) 7643{ 7644 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7645 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7646} 7647 7648static void 7649do_vfp_reg_from_sp (void) 7650{ 7651 inst.instruction |= inst.operands[0].reg << 12; 7652 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn); 7653} 7654 7655static void 7656do_vfp_reg2_from_sp2 (void) 7657{ 7658 constraint (inst.operands[2].imm != 2, 7659 _("only two consecutive VFP SP registers allowed here")); 7660 inst.instruction |= inst.operands[0].reg << 12; 7661 inst.instruction |= inst.operands[1].reg << 16; 7662 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm); 7663} 7664 7665static void 7666do_vfp_sp_from_reg (void) 7667{ 7668 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn); 7669 inst.instruction |= inst.operands[1].reg << 12; 7670} 7671 7672static void 7673do_vfp_sp2_from_reg2 (void) 7674{ 7675 constraint (inst.operands[0].imm != 2, 7676 _("only two consecutive VFP SP registers allowed here")); 7677 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm); 7678 inst.instruction |= inst.operands[1].reg << 12; 7679 inst.instruction |= inst.operands[2].reg << 16; 7680} 7681 7682static void 7683do_vfp_sp_ldst (void) 7684{ 7685 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7686 encode_arm_cp_address (1, FALSE, TRUE, 0); 7687} 7688 7689static void 7690do_vfp_dp_ldst (void) 7691{ 7692 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7693 encode_arm_cp_address (1, FALSE, TRUE, 0); 7694} 7695 7696 7697static void 7698vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type) 7699{ 7700 if (inst.operands[0].writeback) 7701 inst.instruction |= WRITE_BACK; 7702 else 7703 constraint (ldstm_type != VFP_LDSTMIA, 7704 _("this addressing mode requires base-register writeback")); 7705 inst.instruction |= inst.operands[0].reg << 16; 7706 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd); 7707 inst.instruction |= inst.operands[1].imm; 7708} 7709 7710static void 7711vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type) 7712{ 7713 int count; 7714 7715 if (inst.operands[0].writeback) 7716 inst.instruction |= WRITE_BACK; 7717 else 7718 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX, 7719 _("this addressing mode requires base-register writeback")); 7720 7721 inst.instruction |= inst.operands[0].reg << 16; 7722 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7723 7724 count = inst.operands[1].imm << 1; 7725 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX) 7726 count += 1; 7727 7728 inst.instruction |= count; 7729} 7730 7731static void 7732do_vfp_sp_ldstmia (void) 7733{ 7734 vfp_sp_ldstm (VFP_LDSTMIA); 7735} 7736 7737static void 7738do_vfp_sp_ldstmdb (void) 7739{ 7740 vfp_sp_ldstm (VFP_LDSTMDB); 7741} 7742 7743static void 7744do_vfp_dp_ldstmia (void) 7745{ 7746 vfp_dp_ldstm (VFP_LDSTMIA); 7747} 7748 7749static void 7750do_vfp_dp_ldstmdb (void) 7751{ 7752 vfp_dp_ldstm (VFP_LDSTMDB); 7753} 7754 7755static void 7756do_vfp_xp_ldstmia (void) 7757{ 7758 vfp_dp_ldstm (VFP_LDSTMIAX); 7759} 7760 7761static void 7762do_vfp_xp_ldstmdb (void) 7763{ 7764 vfp_dp_ldstm (VFP_LDSTMDBX); 7765} 7766 7767static void 7768do_vfp_dp_rd_rm (void) 7769{ 7770 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7771 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm); 7772} 7773 7774static void 7775do_vfp_dp_rn_rd (void) 7776{ 7777 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn); 7778 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7779} 7780 7781static void 7782do_vfp_dp_rd_rn (void) 7783{ 7784 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7785 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7786} 7787 7788static void 7789do_vfp_dp_rd_rn_rm (void) 7790{ 7791 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7792 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn); 7793 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm); 7794} 7795 7796static void 7797do_vfp_dp_rd (void) 7798{ 7799 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7800} 7801 7802static void 7803do_vfp_dp_rm_rd_rn (void) 7804{ 7805 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm); 7806 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd); 7807 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn); 7808} 7809 7810/* VFPv3 instructions. */ 7811static void 7812do_vfp_sp_const (void) 7813{ 7814 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7815 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7816 inst.instruction |= (inst.operands[1].imm & 0x0f); 7817} 7818 7819static void 7820do_vfp_dp_const (void) 7821{ 7822 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7823 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12; 7824 inst.instruction |= (inst.operands[1].imm & 0x0f); 7825} 7826 7827static void 7828vfp_conv (int srcsize) 7829{ 7830 unsigned immbits = srcsize - inst.operands[1].imm; 7831 inst.instruction |= (immbits & 1) << 5; 7832 inst.instruction |= (immbits >> 1); 7833} 7834 7835static void 7836do_vfp_sp_conv_16 (void) 7837{ 7838 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7839 vfp_conv (16); 7840} 7841 7842static void 7843do_vfp_dp_conv_16 (void) 7844{ 7845 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7846 vfp_conv (16); 7847} 7848 7849static void 7850do_vfp_sp_conv_32 (void) 7851{ 7852 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); 7853 vfp_conv (32); 7854} 7855 7856static void 7857do_vfp_dp_conv_32 (void) 7858{ 7859 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd); 7860 vfp_conv (32); 7861} 7862 7863 7864/* FPA instructions. Also in a logical order. */ 7865 7866static void 7867do_fpa_cmp (void) 7868{ 7869 inst.instruction |= inst.operands[0].reg << 16; 7870 inst.instruction |= inst.operands[1].reg; 7871} 7872 7873static void 7874do_fpa_ldmstm (void) 7875{ 7876 inst.instruction |= inst.operands[0].reg << 12; 7877 switch (inst.operands[1].imm) 7878 { 7879 case 1: inst.instruction |= CP_T_X; break; 7880 case 2: inst.instruction |= CP_T_Y; break; 7881 case 3: inst.instruction |= CP_T_Y | CP_T_X; break; 7882 case 4: break; 7883 default: abort (); 7884 } 7885 7886 if (inst.instruction & (PRE_INDEX | INDEX_UP)) 7887 { 7888 /* The instruction specified "ea" or "fd", so we can only accept 7889 [Rn]{!}. The instruction does not really support stacking or 7890 unstacking, so we have to emulate these by setting appropriate 7891 bits and offsets. */ 7892 constraint (inst.reloc.exp.X_op != O_constant 7893 || inst.reloc.exp.X_add_number != 0, 7894 _("this instruction does not support indexing")); 7895 7896 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback) 7897 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm; 7898 7899 if (!(inst.instruction & INDEX_UP)) 7900 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number; 7901 7902 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback) 7903 { 7904 inst.operands[2].preind = 0; 7905 inst.operands[2].postind = 1; 7906 } 7907 } 7908 7909 encode_arm_cp_address (2, TRUE, TRUE, 0); 7910} 7911 7912 7913/* iWMMXt instructions: strictly in alphabetical order. */ 7914 7915static void 7916do_iwmmxt_tandorc (void) 7917{ 7918 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here")); 7919} 7920 7921static void 7922do_iwmmxt_textrc (void) 7923{ 7924 inst.instruction |= inst.operands[0].reg << 12; 7925 inst.instruction |= inst.operands[1].imm; 7926} 7927 7928static void 7929do_iwmmxt_textrm (void) 7930{ 7931 inst.instruction |= inst.operands[0].reg << 12; 7932 inst.instruction |= inst.operands[1].reg << 16; 7933 inst.instruction |= inst.operands[2].imm; 7934} 7935 7936static void 7937do_iwmmxt_tinsr (void) 7938{ 7939 inst.instruction |= inst.operands[0].reg << 16; 7940 inst.instruction |= inst.operands[1].reg << 12; 7941 inst.instruction |= inst.operands[2].imm; 7942} 7943 7944static void 7945do_iwmmxt_tmia (void) 7946{ 7947 inst.instruction |= inst.operands[0].reg << 5; 7948 inst.instruction |= inst.operands[1].reg; 7949 inst.instruction |= inst.operands[2].reg << 12; 7950} 7951 7952static void 7953do_iwmmxt_waligni (void) 7954{ 7955 inst.instruction |= inst.operands[0].reg << 12; 7956 inst.instruction |= inst.operands[1].reg << 16; 7957 inst.instruction |= inst.operands[2].reg; 7958 inst.instruction |= inst.operands[3].imm << 20; 7959} 7960 7961static void 7962do_iwmmxt_wmerge (void) 7963{ 7964 inst.instruction |= inst.operands[0].reg << 12; 7965 inst.instruction |= inst.operands[1].reg << 16; 7966 inst.instruction |= inst.operands[2].reg; 7967 inst.instruction |= inst.operands[3].imm << 21; 7968} 7969 7970static void 7971do_iwmmxt_wmov (void) 7972{ 7973 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */ 7974 inst.instruction |= inst.operands[0].reg << 12; 7975 inst.instruction |= inst.operands[1].reg << 16; 7976 inst.instruction |= inst.operands[1].reg; 7977} 7978 7979static void 7980do_iwmmxt_wldstbh (void) 7981{ 7982 int reloc; 7983 inst.instruction |= inst.operands[0].reg << 12; 7984 if (thumb_mode) 7985 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2; 7986 else 7987 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2; 7988 encode_arm_cp_address (1, TRUE, FALSE, reloc); 7989} 7990 7991static void 7992do_iwmmxt_wldstw (void) 7993{ 7994 /* RIWR_RIWC clears .isreg for a control register. */ 7995 if (!inst.operands[0].isreg) 7996 { 7997 constraint (inst.cond != COND_ALWAYS, BAD_COND); 7998 inst.instruction |= 0xf0000000; 7999 } 8000 8001 inst.instruction |= inst.operands[0].reg << 12; 8002 encode_arm_cp_address (1, TRUE, TRUE, 0); 8003} 8004 8005static void 8006do_iwmmxt_wldstd (void) 8007{ 8008 inst.instruction |= inst.operands[0].reg << 12; 8009 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2) 8010 && inst.operands[1].immisreg) 8011 { 8012 inst.instruction &= ~0x1a000ff; 8013 inst.instruction |= (0xf << 28); 8014 if (inst.operands[1].preind) 8015 inst.instruction |= PRE_INDEX; 8016 if (!inst.operands[1].negative) 8017 inst.instruction |= INDEX_UP; 8018 if (inst.operands[1].writeback) 8019 inst.instruction |= WRITE_BACK; 8020 inst.instruction |= inst.operands[1].reg << 16; 8021 inst.instruction |= inst.reloc.exp.X_add_number << 4; 8022 inst.instruction |= inst.operands[1].imm; 8023 } 8024 else 8025 encode_arm_cp_address (1, TRUE, FALSE, 0); 8026} 8027 8028static void 8029do_iwmmxt_wshufh (void) 8030{ 8031 inst.instruction |= inst.operands[0].reg << 12; 8032 inst.instruction |= inst.operands[1].reg << 16; 8033 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16); 8034 inst.instruction |= (inst.operands[2].imm & 0x0f); 8035} 8036 8037static void 8038do_iwmmxt_wzero (void) 8039{ 8040 /* WZERO reg is an alias for WANDN reg, reg, reg. */ 8041 inst.instruction |= inst.operands[0].reg; 8042 inst.instruction |= inst.operands[0].reg << 12; 8043 inst.instruction |= inst.operands[0].reg << 16; 8044} 8045 8046static void 8047do_iwmmxt_wrwrwr_or_imm5 (void) 8048{ 8049 if (inst.operands[2].isreg) 8050 do_rd_rn_rm (); 8051 else { 8052 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2), 8053 _("immediate operand requires iWMMXt2")); 8054 do_rd_rn (); 8055 if (inst.operands[2].imm == 0) 8056 { 8057 switch ((inst.instruction >> 20) & 0xf) 8058 { 8059 case 4: 8060 case 5: 8061 case 6: 8062 case 7: 8063 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */ 8064 inst.operands[2].imm = 16; 8065 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20); 8066 break; 8067 case 8: 8068 case 9: 8069 case 10: 8070 case 11: 8071 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */ 8072 inst.operands[2].imm = 32; 8073 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20); 8074 break; 8075 case 12: 8076 case 13: 8077 case 14: 8078 case 15: 8079 { 8080 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */ 8081 unsigned long wrn; 8082 wrn = (inst.instruction >> 16) & 0xf; 8083 inst.instruction &= 0xff0fff0f; 8084 inst.instruction |= wrn; 8085 /* Bail out here; the instruction is now assembled. */ 8086 return; 8087 } 8088 } 8089 } 8090 /* Map 32 -> 0, etc. */ 8091 inst.operands[2].imm &= 0x1f; 8092 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf); 8093 } 8094} 8095 8096/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register 8097 operations first, then control, shift, and load/store. */ 8098 8099/* Insns like "foo X,Y,Z". */ 8100 8101static void 8102do_mav_triple (void) 8103{ 8104 inst.instruction |= inst.operands[0].reg << 16; 8105 inst.instruction |= inst.operands[1].reg; 8106 inst.instruction |= inst.operands[2].reg << 12; 8107} 8108 8109/* Insns like "foo W,X,Y,Z". 8110 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */ 8111 8112static void 8113do_mav_quad (void) 8114{ 8115 inst.instruction |= inst.operands[0].reg << 5; 8116 inst.instruction |= inst.operands[1].reg << 12; 8117 inst.instruction |= inst.operands[2].reg << 16; 8118 inst.instruction |= inst.operands[3].reg; 8119} 8120 8121/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */ 8122static void 8123do_mav_dspsc (void) 8124{ 8125 inst.instruction |= inst.operands[1].reg << 12; 8126} 8127 8128/* Maverick shift immediate instructions. 8129 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0]. 8130 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */ 8131 8132static void 8133do_mav_shift (void) 8134{ 8135 int imm = inst.operands[2].imm; 8136 8137 inst.instruction |= inst.operands[0].reg << 12; 8138 inst.instruction |= inst.operands[1].reg << 16; 8139 8140 /* Bits 0-3 of the insn should have bits 0-3 of the immediate. 8141 Bits 5-7 of the insn should have bits 4-6 of the immediate. 8142 Bit 4 should be 0. */ 8143 imm = (imm & 0xf) | ((imm & 0x70) << 1); 8144 8145 inst.instruction |= imm; 8146} 8147 8148/* XScale instructions. Also sorted arithmetic before move. */ 8149 8150/* Xscale multiply-accumulate (argument parse) 8151 MIAcc acc0,Rm,Rs 8152 MIAPHcc acc0,Rm,Rs 8153 MIAxycc acc0,Rm,Rs. */ 8154 8155static void 8156do_xsc_mia (void) 8157{ 8158 inst.instruction |= inst.operands[1].reg; 8159 inst.instruction |= inst.operands[2].reg << 12; 8160} 8161 8162/* Xscale move-accumulator-register (argument parse) 8163 8164 MARcc acc0,RdLo,RdHi. */ 8165 8166static void 8167do_xsc_mar (void) 8168{ 8169 inst.instruction |= inst.operands[1].reg << 12; 8170 inst.instruction |= inst.operands[2].reg << 16; 8171} 8172 8173/* Xscale move-register-accumulator (argument parse) 8174 8175 MRAcc RdLo,RdHi,acc0. */ 8176 8177static void 8178do_xsc_mra (void) 8179{ 8180 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP); 8181 inst.instruction |= inst.operands[0].reg << 12; 8182 inst.instruction |= inst.operands[1].reg << 16; 8183} 8184 8185/* Encoding functions relevant only to Thumb. */ 8186 8187/* inst.operands[i] is a shifted-register operand; encode 8188 it into inst.instruction in the format used by Thumb32. */ 8189 8190static void 8191encode_thumb32_shifted_operand (int i) 8192{ 8193 unsigned int value = inst.reloc.exp.X_add_number; 8194 unsigned int shift = inst.operands[i].shift_kind; 8195 8196 constraint (inst.operands[i].immisreg, 8197 _("shift by register not allowed in thumb mode")); 8198 inst.instruction |= inst.operands[i].reg; 8199 if (shift == SHIFT_RRX) 8200 inst.instruction |= SHIFT_ROR << 4; 8201 else 8202 { 8203 constraint (inst.reloc.exp.X_op != O_constant, 8204 _("expression too complex")); 8205 8206 constraint (value > 32 8207 || (value == 32 && (shift == SHIFT_LSL 8208 || shift == SHIFT_ROR)), 8209 _("shift expression is too large")); 8210 8211 if (value == 0) 8212 shift = SHIFT_LSL; 8213 else if (value == 32) 8214 value = 0; 8215 8216 inst.instruction |= shift << 4; 8217 inst.instruction |= (value & 0x1c) << 10; 8218 inst.instruction |= (value & 0x03) << 6; 8219 } 8220} 8221 8222 8223/* inst.operands[i] was set up by parse_address. Encode it into a 8224 Thumb32 format load or store instruction. Reject forms that cannot 8225 be used with such instructions. If is_t is true, reject forms that 8226 cannot be used with a T instruction; if is_d is true, reject forms 8227 that cannot be used with a D instruction. */ 8228 8229static void 8230encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) 8231{ 8232 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC); 8233 8234 constraint (!inst.operands[i].isreg, 8235 _("Instruction does not support =N addresses")); 8236 8237 inst.instruction |= inst.operands[i].reg << 16; 8238 if (inst.operands[i].immisreg) 8239 { 8240 constraint (is_pc, _("cannot use register index with PC-relative addressing")); 8241 constraint (is_t || is_d, _("cannot use register index with this instruction")); 8242 constraint (inst.operands[i].negative, 8243 _("Thumb does not support negative register indexing")); 8244 constraint (inst.operands[i].postind, 8245 _("Thumb does not support register post-indexing")); 8246 constraint (inst.operands[i].writeback, 8247 _("Thumb does not support register indexing with writeback")); 8248 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL, 8249 _("Thumb supports only LSL in shifted register indexing")); 8250 8251 inst.instruction |= inst.operands[i].imm; 8252 if (inst.operands[i].shifted) 8253 { 8254 constraint (inst.reloc.exp.X_op != O_constant, 8255 _("expression too complex")); 8256 constraint (inst.reloc.exp.X_add_number < 0 8257 || inst.reloc.exp.X_add_number > 3, 8258 _("shift out of range")); 8259 inst.instruction |= inst.reloc.exp.X_add_number << 4; 8260 } 8261 inst.reloc.type = BFD_RELOC_UNUSED; 8262 } 8263 else if (inst.operands[i].preind) 8264 { 8265 constraint (is_pc && inst.operands[i].writeback, 8266 _("cannot use writeback with PC-relative addressing")); 8267 constraint (is_t && inst.operands[i].writeback, 8268 _("cannot use writeback with this instruction")); 8269 8270 if (is_d) 8271 { 8272 inst.instruction |= 0x01000000; 8273 if (inst.operands[i].writeback) 8274 inst.instruction |= 0x00200000; 8275 } 8276 else 8277 { 8278 inst.instruction |= 0x00000c00; 8279 if (inst.operands[i].writeback) 8280 inst.instruction |= 0x00000100; 8281 } 8282 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8283 } 8284 else if (inst.operands[i].postind) 8285 { 8286 assert (inst.operands[i].writeback); 8287 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing")); 8288 constraint (is_t, _("cannot use post-indexing with this instruction")); 8289 8290 if (is_d) 8291 inst.instruction |= 0x00200000; 8292 else 8293 inst.instruction |= 0x00000900; 8294 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM; 8295 } 8296 else /* unindexed - only for coprocessor */ 8297 inst.error = _("instruction does not accept unindexed addressing"); 8298} 8299 8300/* Table of Thumb instructions which exist in both 16- and 32-bit 8301 encodings (the latter only in post-V6T2 cores). The index is the 8302 value used in the insns table below. When there is more than one 8303 possible 16-bit encoding for the instruction, this table always 8304 holds variant (1). 8305 Also contains several pseudo-instructions used during relaxation. */ 8306#define T16_32_TAB \ 8307 X(adc, 4140, eb400000), \ 8308 X(adcs, 4140, eb500000), \ 8309 X(add, 1c00, eb000000), \ 8310 X(adds, 1c00, eb100000), \ 8311 X(addi, 0000, f1000000), \ 8312 X(addis, 0000, f1100000), \ 8313 X(add_pc,000f, f20f0000), \ 8314 X(add_sp,000d, f10d0000), \ 8315 X(adr, 000f, f20f0000), \ 8316 X(and, 4000, ea000000), \ 8317 X(ands, 4000, ea100000), \ 8318 X(asr, 1000, fa40f000), \ 8319 X(asrs, 1000, fa50f000), \ 8320 X(b, e000, f000b000), \ 8321 X(bcond, d000, f0008000), \ 8322 X(bic, 4380, ea200000), \ 8323 X(bics, 4380, ea300000), \ 8324 X(cmn, 42c0, eb100f00), \ 8325 X(cmp, 2800, ebb00f00), \ 8326 X(cpsie, b660, f3af8400), \ 8327 X(cpsid, b670, f3af8600), \ 8328 X(cpy, 4600, ea4f0000), \ 8329 X(dec_sp,80dd, f1ad0d00), \ 8330 X(eor, 4040, ea800000), \ 8331 X(eors, 4040, ea900000), \ 8332 X(inc_sp,00dd, f10d0d00), \ 8333 X(ldmia, c800, e8900000), \ 8334 X(ldr, 6800, f8500000), \ 8335 X(ldrb, 7800, f8100000), \ 8336 X(ldrh, 8800, f8300000), \ 8337 X(ldrsb, 5600, f9100000), \ 8338 X(ldrsh, 5e00, f9300000), \ 8339 X(ldr_pc,4800, f85f0000), \ 8340 X(ldr_pc2,4800, f85f0000), \ 8341 X(ldr_sp,9800, f85d0000), \ 8342 X(lsl, 0000, fa00f000), \ 8343 X(lsls, 0000, fa10f000), \ 8344 X(lsr, 0800, fa20f000), \ 8345 X(lsrs, 0800, fa30f000), \ 8346 X(mov, 2000, ea4f0000), \ 8347 X(movs, 2000, ea5f0000), \ 8348 X(mul, 4340, fb00f000), \ 8349 X(muls, 4340, ffffffff), /* no 32b muls */ \ 8350 X(mvn, 43c0, ea6f0000), \ 8351 X(mvns, 43c0, ea7f0000), \ 8352 X(neg, 4240, f1c00000), /* rsb #0 */ \ 8353 X(negs, 4240, f1d00000), /* rsbs #0 */ \ 8354 X(orr, 4300, ea400000), \ 8355 X(orrs, 4300, ea500000), \ 8356 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \ 8357 X(push, b400, e92d0000), /* stmdb sp!,... */ \ 8358 X(rev, ba00, fa90f080), \ 8359 X(rev16, ba40, fa90f090), \ 8360 X(revsh, bac0, fa90f0b0), \ 8361 X(ror, 41c0, fa60f000), \ 8362 X(rors, 41c0, fa70f000), \ 8363 X(sbc, 4180, eb600000), \ 8364 X(sbcs, 4180, eb700000), \ 8365 X(stmia, c000, e8800000), \ 8366 X(str, 6000, f8400000), \ 8367 X(strb, 7000, f8000000), \ 8368 X(strh, 8000, f8200000), \ 8369 X(str_sp,9000, f84d0000), \ 8370 X(sub, 1e00, eba00000), \ 8371 X(subs, 1e00, ebb00000), \ 8372 X(subi, 8000, f1a00000), \ 8373 X(subis, 8000, f1b00000), \ 8374 X(sxtb, b240, fa4ff080), \ 8375 X(sxth, b200, fa0ff080), \ 8376 X(tst, 4200, ea100f00), \ 8377 X(uxtb, b2c0, fa5ff080), \ 8378 X(uxth, b280, fa1ff080), \ 8379 X(nop, bf00, f3af8000), \ 8380 X(yield, bf10, f3af8001), \ 8381 X(wfe, bf20, f3af8002), \ 8382 X(wfi, bf30, f3af8003), \ 8383 X(sev, bf40, f3af9004), /* typo, 8004? */ 8384 8385/* To catch errors in encoding functions, the codes are all offset by 8386 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined 8387 as 16-bit instructions. */ 8388#define X(a,b,c) T_MNEM_##a 8389enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }; 8390#undef X 8391 8392#define X(a,b,c) 0x##b 8393static const unsigned short thumb_op16[] = { T16_32_TAB }; 8394#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)]) 8395#undef X 8396 8397#define X(a,b,c) 0x##c 8398static const unsigned int thumb_op32[] = { T16_32_TAB }; 8399#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)]) 8400#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000) 8401#undef X 8402#undef T16_32_TAB 8403 8404/* Thumb instruction encoders, in alphabetical order. */ 8405 8406/* ADDW or SUBW. */ 8407static void 8408do_t_add_sub_w (void) 8409{ 8410 int Rd, Rn; 8411 8412 Rd = inst.operands[0].reg; 8413 Rn = inst.operands[1].reg; 8414 8415 constraint (Rd == 15, _("PC not allowed as destination")); 8416 inst.instruction |= (Rn << 16) | (Rd << 8); 8417 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8418} 8419 8420/* Parse an add or subtract instruction. We get here with inst.instruction 8421 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ 8422 8423static void 8424do_t_add_sub (void) 8425{ 8426 int Rd, Rs, Rn; 8427 8428 Rd = inst.operands[0].reg; 8429 Rs = (inst.operands[1].present 8430 ? inst.operands[1].reg /* Rd, Rs, foo */ 8431 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8432 8433 if (unified_syntax) 8434 { 8435 bfd_boolean flags; 8436 bfd_boolean narrow; 8437 int opcode; 8438 8439 flags = (inst.instruction == T_MNEM_adds 8440 || inst.instruction == T_MNEM_subs); 8441 if (flags) 8442 narrow = (current_it_mask == 0); 8443 else 8444 narrow = (current_it_mask != 0); 8445 if (!inst.operands[2].isreg) 8446 { 8447 int add; 8448 8449 add = (inst.instruction == T_MNEM_add 8450 || inst.instruction == T_MNEM_adds); 8451 opcode = 0; 8452 if (inst.size_req != 4) 8453 { 8454 /* Attempt to use a narrow opcode, with relaxation if 8455 appropriate. */ 8456 if (Rd == REG_SP && Rs == REG_SP && !flags) 8457 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp; 8458 else if (Rd <= 7 && Rs == REG_SP && add && !flags) 8459 opcode = T_MNEM_add_sp; 8460 else if (Rd <= 7 && Rs == REG_PC && add && !flags) 8461 opcode = T_MNEM_add_pc; 8462 else if (Rd <= 7 && Rs <= 7 && narrow) 8463 { 8464 if (flags) 8465 opcode = add ? T_MNEM_addis : T_MNEM_subis; 8466 else 8467 opcode = add ? T_MNEM_addi : T_MNEM_subi; 8468 } 8469 if (opcode) 8470 { 8471 inst.instruction = THUMB_OP16(opcode); 8472 inst.instruction |= (Rd << 4) | Rs; 8473 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8474 if (inst.size_req != 2) 8475 inst.relax = opcode; 8476 } 8477 else 8478 constraint (inst.size_req == 2, BAD_HIREG); 8479 } 8480 if (inst.size_req == 4 8481 || (inst.size_req != 2 && !opcode)) 8482 { 8483 if (Rd == REG_PC) 8484 { 8485 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs, 8486 _("only SUBS PC, LR, #const allowed")); 8487 constraint (inst.reloc.exp.X_op != O_constant, 8488 _("expression too complex")); 8489 constraint (inst.reloc.exp.X_add_number < 0 8490 || inst.reloc.exp.X_add_number > 0xff, 8491 _("immediate value out of range")); 8492 inst.instruction = T2_SUBS_PC_LR 8493 | inst.reloc.exp.X_add_number; 8494 inst.reloc.type = BFD_RELOC_UNUSED; 8495 return; 8496 } 8497 else if (Rs == REG_PC) 8498 { 8499 /* Always use addw/subw. */ 8500 inst.instruction = add ? 0xf20f0000 : 0xf2af0000; 8501 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; 8502 } 8503 else 8504 { 8505 inst.instruction = THUMB_OP32 (inst.instruction); 8506 inst.instruction = (inst.instruction & 0xe1ffffff) 8507 | 0x10000000; 8508 if (flags) 8509 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8510 else 8511 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM; 8512 } 8513 inst.instruction |= Rd << 8; 8514 inst.instruction |= Rs << 16; 8515 } 8516 } 8517 else 8518 { 8519 Rn = inst.operands[2].reg; 8520 /* See if we can do this with a 16-bit instruction. */ 8521 if (!inst.operands[2].shifted && inst.size_req != 4) 8522 { 8523 if (Rd > 7 || Rs > 7 || Rn > 7) 8524 narrow = FALSE; 8525 8526 if (narrow) 8527 { 8528 inst.instruction = ((inst.instruction == T_MNEM_adds 8529 || inst.instruction == T_MNEM_add) 8530 ? T_OPCODE_ADD_R3 8531 : T_OPCODE_SUB_R3); 8532 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8533 return; 8534 } 8535 8536 if (inst.instruction == T_MNEM_add) 8537 { 8538 if (Rd == Rs) 8539 { 8540 inst.instruction = T_OPCODE_ADD_HI; 8541 inst.instruction |= (Rd & 8) << 4; 8542 inst.instruction |= (Rd & 7); 8543 inst.instruction |= Rn << 3; 8544 return; 8545 } 8546 /* ... because addition is commutative! */ 8547 else if (Rd == Rn) 8548 { 8549 inst.instruction = T_OPCODE_ADD_HI; 8550 inst.instruction |= (Rd & 8) << 4; 8551 inst.instruction |= (Rd & 7); 8552 inst.instruction |= Rs << 3; 8553 return; 8554 } 8555 } 8556 } 8557 /* If we get here, it can't be done in 16 bits. */ 8558 constraint (inst.operands[2].shifted && inst.operands[2].immisreg, 8559 _("shift must be constant")); 8560 inst.instruction = THUMB_OP32 (inst.instruction); 8561 inst.instruction |= Rd << 8; 8562 inst.instruction |= Rs << 16; 8563 encode_thumb32_shifted_operand (2); 8564 } 8565 } 8566 else 8567 { 8568 constraint (inst.instruction == T_MNEM_adds 8569 || inst.instruction == T_MNEM_subs, 8570 BAD_THUMB32); 8571 8572 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */ 8573 { 8574 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP)) 8575 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC), 8576 BAD_HIREG); 8577 8578 inst.instruction = (inst.instruction == T_MNEM_add 8579 ? 0x0000 : 0x8000); 8580 inst.instruction |= (Rd << 4) | Rs; 8581 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8582 return; 8583 } 8584 8585 Rn = inst.operands[2].reg; 8586 constraint (inst.operands[2].shifted, _("unshifted register required")); 8587 8588 /* We now have Rd, Rs, and Rn set to registers. */ 8589 if (Rd > 7 || Rs > 7 || Rn > 7) 8590 { 8591 /* Can't do this for SUB. */ 8592 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG); 8593 inst.instruction = T_OPCODE_ADD_HI; 8594 inst.instruction |= (Rd & 8) << 4; 8595 inst.instruction |= (Rd & 7); 8596 if (Rs == Rd) 8597 inst.instruction |= Rn << 3; 8598 else if (Rn == Rd) 8599 inst.instruction |= Rs << 3; 8600 else 8601 constraint (1, _("dest must overlap one source register")); 8602 } 8603 else 8604 { 8605 inst.instruction = (inst.instruction == T_MNEM_add 8606 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3); 8607 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); 8608 } 8609 } 8610} 8611 8612static void 8613do_t_adr (void) 8614{ 8615 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7) 8616 { 8617 /* Defer to section relaxation. */ 8618 inst.relax = inst.instruction; 8619 inst.instruction = THUMB_OP16 (inst.instruction); 8620 inst.instruction |= inst.operands[0].reg << 4; 8621 } 8622 else if (unified_syntax && inst.size_req != 2) 8623 { 8624 /* Generate a 32-bit opcode. */ 8625 inst.instruction = THUMB_OP32 (inst.instruction); 8626 inst.instruction |= inst.operands[0].reg << 8; 8627 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12; 8628 inst.reloc.pc_rel = 1; 8629 } 8630 else 8631 { 8632 /* Generate a 16-bit opcode. */ 8633 inst.instruction = THUMB_OP16 (inst.instruction); 8634 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD; 8635 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */ 8636 inst.reloc.pc_rel = 1; 8637 8638 inst.instruction |= inst.operands[0].reg << 4; 8639 } 8640} 8641 8642/* Arithmetic instructions for which there is just one 16-bit 8643 instruction encoding, and it allows only two low registers. 8644 For maximal compatibility with ARM syntax, we allow three register 8645 operands even when Thumb-32 instructions are not available, as long 8646 as the first two are identical. For instance, both "sbc r0,r1" and 8647 "sbc r0,r0,r1" are allowed. */ 8648static void 8649do_t_arit3 (void) 8650{ 8651 int Rd, Rs, Rn; 8652 8653 Rd = inst.operands[0].reg; 8654 Rs = (inst.operands[1].present 8655 ? inst.operands[1].reg /* Rd, Rs, foo */ 8656 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8657 Rn = inst.operands[2].reg; 8658 8659 if (unified_syntax) 8660 { 8661 if (!inst.operands[2].isreg) 8662 { 8663 /* For an immediate, we always generate a 32-bit opcode; 8664 section relaxation will shrink it later if possible. */ 8665 inst.instruction = THUMB_OP32 (inst.instruction); 8666 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8667 inst.instruction |= Rd << 8; 8668 inst.instruction |= Rs << 16; 8669 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8670 } 8671 else 8672 { 8673 bfd_boolean narrow; 8674 8675 /* See if we can do this with a 16-bit instruction. */ 8676 if (THUMB_SETS_FLAGS (inst.instruction)) 8677 narrow = current_it_mask == 0; 8678 else 8679 narrow = current_it_mask != 0; 8680 8681 if (Rd > 7 || Rn > 7 || Rs > 7) 8682 narrow = FALSE; 8683 if (inst.operands[2].shifted) 8684 narrow = FALSE; 8685 if (inst.size_req == 4) 8686 narrow = FALSE; 8687 8688 if (narrow 8689 && Rd == Rs) 8690 { 8691 inst.instruction = THUMB_OP16 (inst.instruction); 8692 inst.instruction |= Rd; 8693 inst.instruction |= Rn << 3; 8694 return; 8695 } 8696 8697 /* If we get here, it can't be done in 16 bits. */ 8698 constraint (inst.operands[2].shifted 8699 && inst.operands[2].immisreg, 8700 _("shift must be constant")); 8701 inst.instruction = THUMB_OP32 (inst.instruction); 8702 inst.instruction |= Rd << 8; 8703 inst.instruction |= Rs << 16; 8704 encode_thumb32_shifted_operand (2); 8705 } 8706 } 8707 else 8708 { 8709 /* On its face this is a lie - the instruction does set the 8710 flags. However, the only supported mnemonic in this mode 8711 says it doesn't. */ 8712 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8713 8714 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8715 _("unshifted register required")); 8716 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8717 constraint (Rd != Rs, 8718 _("dest and source1 must be the same register")); 8719 8720 inst.instruction = THUMB_OP16 (inst.instruction); 8721 inst.instruction |= Rd; 8722 inst.instruction |= Rn << 3; 8723 } 8724} 8725 8726/* Similarly, but for instructions where the arithmetic operation is 8727 commutative, so we can allow either of them to be different from 8728 the destination operand in a 16-bit instruction. For instance, all 8729 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are 8730 accepted. */ 8731static void 8732do_t_arit3c (void) 8733{ 8734 int Rd, Rs, Rn; 8735 8736 Rd = inst.operands[0].reg; 8737 Rs = (inst.operands[1].present 8738 ? inst.operands[1].reg /* Rd, Rs, foo */ 8739 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 8740 Rn = inst.operands[2].reg; 8741 8742 if (unified_syntax) 8743 { 8744 if (!inst.operands[2].isreg) 8745 { 8746 /* For an immediate, we always generate a 32-bit opcode; 8747 section relaxation will shrink it later if possible. */ 8748 inst.instruction = THUMB_OP32 (inst.instruction); 8749 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 8750 inst.instruction |= Rd << 8; 8751 inst.instruction |= Rs << 16; 8752 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 8753 } 8754 else 8755 { 8756 bfd_boolean narrow; 8757 8758 /* See if we can do this with a 16-bit instruction. */ 8759 if (THUMB_SETS_FLAGS (inst.instruction)) 8760 narrow = current_it_mask == 0; 8761 else 8762 narrow = current_it_mask != 0; 8763 8764 if (Rd > 7 || Rn > 7 || Rs > 7) 8765 narrow = FALSE; 8766 if (inst.operands[2].shifted) 8767 narrow = FALSE; 8768 if (inst.size_req == 4) 8769 narrow = FALSE; 8770 8771 if (narrow) 8772 { 8773 if (Rd == Rs) 8774 { 8775 inst.instruction = THUMB_OP16 (inst.instruction); 8776 inst.instruction |= Rd; 8777 inst.instruction |= Rn << 3; 8778 return; 8779 } 8780 if (Rd == Rn) 8781 { 8782 inst.instruction = THUMB_OP16 (inst.instruction); 8783 inst.instruction |= Rd; 8784 inst.instruction |= Rs << 3; 8785 return; 8786 } 8787 } 8788 8789 /* If we get here, it can't be done in 16 bits. */ 8790 constraint (inst.operands[2].shifted 8791 && inst.operands[2].immisreg, 8792 _("shift must be constant")); 8793 inst.instruction = THUMB_OP32 (inst.instruction); 8794 inst.instruction |= Rd << 8; 8795 inst.instruction |= Rs << 16; 8796 encode_thumb32_shifted_operand (2); 8797 } 8798 } 8799 else 8800 { 8801 /* On its face this is a lie - the instruction does set the 8802 flags. However, the only supported mnemonic in this mode 8803 says it doesn't. */ 8804 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 8805 8806 constraint (!inst.operands[2].isreg || inst.operands[2].shifted, 8807 _("unshifted register required")); 8808 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); 8809 8810 inst.instruction = THUMB_OP16 (inst.instruction); 8811 inst.instruction |= Rd; 8812 8813 if (Rd == Rs) 8814 inst.instruction |= Rn << 3; 8815 else if (Rd == Rn) 8816 inst.instruction |= Rs << 3; 8817 else 8818 constraint (1, _("dest must overlap one source register")); 8819 } 8820} 8821 8822static void 8823do_t_barrier (void) 8824{ 8825 if (inst.operands[0].present) 8826 { 8827 constraint ((inst.instruction & 0xf0) != 0x40 8828 && inst.operands[0].imm != 0xf, 8829 "bad barrier type"); 8830 inst.instruction |= inst.operands[0].imm; 8831 } 8832 else 8833 inst.instruction |= 0xf; 8834} 8835 8836static void 8837do_t_bfc (void) 8838{ 8839 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm; 8840 constraint (msb > 32, _("bit-field extends past end of register")); 8841 /* The instruction encoding stores the LSB and MSB, 8842 not the LSB and width. */ 8843 inst.instruction |= inst.operands[0].reg << 8; 8844 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10; 8845 inst.instruction |= (inst.operands[1].imm & 0x03) << 6; 8846 inst.instruction |= msb - 1; 8847} 8848 8849static void 8850do_t_bfi (void) 8851{ 8852 unsigned int msb; 8853 8854 /* #0 in second position is alternative syntax for bfc, which is 8855 the same instruction but with REG_PC in the Rm field. */ 8856 if (!inst.operands[1].isreg) 8857 inst.operands[1].reg = REG_PC; 8858 8859 msb = inst.operands[2].imm + inst.operands[3].imm; 8860 constraint (msb > 32, _("bit-field extends past end of register")); 8861 /* The instruction encoding stores the LSB and MSB, 8862 not the LSB and width. */ 8863 inst.instruction |= inst.operands[0].reg << 8; 8864 inst.instruction |= inst.operands[1].reg << 16; 8865 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8866 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8867 inst.instruction |= msb - 1; 8868} 8869 8870static void 8871do_t_bfx (void) 8872{ 8873 constraint (inst.operands[2].imm + inst.operands[3].imm > 32, 8874 _("bit-field extends past end of register")); 8875 inst.instruction |= inst.operands[0].reg << 8; 8876 inst.instruction |= inst.operands[1].reg << 16; 8877 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10; 8878 inst.instruction |= (inst.operands[2].imm & 0x03) << 6; 8879 inst.instruction |= inst.operands[3].imm - 1; 8880} 8881 8882/* ARM V5 Thumb BLX (argument parse) 8883 BLX <target_addr> which is BLX(1) 8884 BLX <Rm> which is BLX(2) 8885 Unfortunately, there are two different opcodes for this mnemonic. 8886 So, the insns[].value is not used, and the code here zaps values 8887 into inst.instruction. 8888 8889 ??? How to take advantage of the additional two bits of displacement 8890 available in Thumb32 mode? Need new relocation? */ 8891 8892static void 8893do_t_blx (void) 8894{ 8895 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8896 if (inst.operands[0].isreg) 8897 /* We have a register, so this is BLX(2). */ 8898 inst.instruction |= inst.operands[0].reg << 3; 8899 else 8900 { 8901 /* No register. This must be BLX(1). */ 8902 inst.instruction = 0xf000e800; 8903#ifdef OBJ_ELF 8904 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4) 8905 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8906 else 8907#endif 8908 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; 8909 inst.reloc.pc_rel = 1; 8910 } 8911} 8912 8913static void 8914do_t_branch (void) 8915{ 8916 int opcode; 8917 int cond; 8918 8919 if (current_it_mask) 8920 { 8921 /* Conditional branches inside IT blocks are encoded as unconditional 8922 branches. */ 8923 cond = COND_ALWAYS; 8924 /* A branch must be the last instruction in an IT block. */ 8925 constraint (current_it_mask != 0x10, BAD_BRANCH); 8926 } 8927 else 8928 cond = inst.cond; 8929 8930 if (cond != COND_ALWAYS) 8931 opcode = T_MNEM_bcond; 8932 else 8933 opcode = inst.instruction; 8934 8935 if (unified_syntax && inst.size_req == 4) 8936 { 8937 inst.instruction = THUMB_OP32(opcode); 8938 if (cond == COND_ALWAYS) 8939 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; 8940 else 8941 { 8942 assert (cond != 0xF); 8943 inst.instruction |= cond << 22; 8944 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; 8945 } 8946 } 8947 else 8948 { 8949 inst.instruction = THUMB_OP16(opcode); 8950 if (cond == COND_ALWAYS) 8951 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; 8952 else 8953 { 8954 inst.instruction |= cond << 8; 8955 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; 8956 } 8957 /* Allow section relaxation. */ 8958 if (unified_syntax && inst.size_req != 2) 8959 inst.relax = opcode; 8960 } 8961 8962 inst.reloc.pc_rel = 1; 8963} 8964 8965static void 8966do_t_bkpt (void) 8967{ 8968 constraint (inst.cond != COND_ALWAYS, 8969 _("instruction is always unconditional")); 8970 if (inst.operands[0].present) 8971 { 8972 constraint (inst.operands[0].imm > 255, 8973 _("immediate value out of range")); 8974 inst.instruction |= inst.operands[0].imm; 8975 } 8976} 8977 8978static void 8979do_t_branch23 (void) 8980{ 8981 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 8982 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23; 8983 inst.reloc.pc_rel = 1; 8984 8985 /* If the destination of the branch is a defined symbol which does not have 8986 the THUMB_FUNC attribute, then we must be calling a function which has 8987 the (interfacearm) attribute. We look for the Thumb entry point to that 8988 function and change the branch to refer to that function instead. */ 8989 if ( inst.reloc.exp.X_op == O_symbol 8990 && inst.reloc.exp.X_add_symbol != NULL 8991 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol) 8992 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol)) 8993 inst.reloc.exp.X_add_symbol = 8994 find_real_start (inst.reloc.exp.X_add_symbol); 8995} 8996 8997static void 8998do_t_bx (void) 8999{ 9000 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 9001 inst.instruction |= inst.operands[0].reg << 3; 9002 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc 9003 should cause the alignment to be checked once it is known. This is 9004 because BX PC only works if the instruction is word aligned. */ 9005} 9006 9007static void 9008do_t_bxj (void) 9009{ 9010 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 9011 if (inst.operands[0].reg == REG_PC) 9012 as_tsktsk (_("use of r15 in bxj is not really useful")); 9013 9014 inst.instruction |= inst.operands[0].reg << 16; 9015} 9016 9017static void 9018do_t_clz (void) 9019{ 9020 inst.instruction |= inst.operands[0].reg << 8; 9021 inst.instruction |= inst.operands[1].reg << 16; 9022 inst.instruction |= inst.operands[1].reg; 9023} 9024 9025static void 9026do_t_cps (void) 9027{ 9028 constraint (current_it_mask, BAD_NOT_IT); 9029 inst.instruction |= inst.operands[0].imm; 9030} 9031 9032static void 9033do_t_cpsi (void) 9034{ 9035 constraint (current_it_mask, BAD_NOT_IT); 9036 if (unified_syntax 9037 && (inst.operands[1].present || inst.size_req == 4) 9038 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm)) 9039 { 9040 unsigned int imod = (inst.instruction & 0x0030) >> 4; 9041 inst.instruction = 0xf3af8000; 9042 inst.instruction |= imod << 9; 9043 inst.instruction |= inst.operands[0].imm << 5; 9044 if (inst.operands[1].present) 9045 inst.instruction |= 0x100 | inst.operands[1].imm; 9046 } 9047 else 9048 { 9049 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1) 9050 && (inst.operands[0].imm & 4), 9051 _("selected processor does not support 'A' form " 9052 "of this instruction")); 9053 constraint (inst.operands[1].present || inst.size_req == 4, 9054 _("Thumb does not support the 2-argument " 9055 "form of this instruction")); 9056 inst.instruction |= inst.operands[0].imm; 9057 } 9058} 9059 9060/* THUMB CPY instruction (argument parse). */ 9061 9062static void 9063do_t_cpy (void) 9064{ 9065 if (inst.size_req == 4) 9066 { 9067 inst.instruction = THUMB_OP32 (T_MNEM_mov); 9068 inst.instruction |= inst.operands[0].reg << 8; 9069 inst.instruction |= inst.operands[1].reg; 9070 } 9071 else 9072 { 9073 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9074 inst.instruction |= (inst.operands[0].reg & 0x7); 9075 inst.instruction |= inst.operands[1].reg << 3; 9076 } 9077} 9078 9079static void 9080do_t_cbz (void) 9081{ 9082 constraint (current_it_mask, BAD_NOT_IT); 9083 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9084 inst.instruction |= inst.operands[0].reg; 9085 inst.reloc.pc_rel = 1; 9086 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7; 9087} 9088 9089static void 9090do_t_dbg (void) 9091{ 9092 inst.instruction |= inst.operands[0].imm; 9093} 9094 9095static void 9096do_t_div (void) 9097{ 9098 if (!inst.operands[1].present) 9099 inst.operands[1].reg = inst.operands[0].reg; 9100 inst.instruction |= inst.operands[0].reg << 8; 9101 inst.instruction |= inst.operands[1].reg << 16; 9102 inst.instruction |= inst.operands[2].reg; 9103} 9104 9105static void 9106do_t_hint (void) 9107{ 9108 if (unified_syntax && inst.size_req == 4) 9109 inst.instruction = THUMB_OP32 (inst.instruction); 9110 else 9111 inst.instruction = THUMB_OP16 (inst.instruction); 9112} 9113 9114static void 9115do_t_it (void) 9116{ 9117 unsigned int cond = inst.operands[0].imm; 9118 9119 constraint (current_it_mask, BAD_NOT_IT); 9120 current_it_mask = (inst.instruction & 0xf) | 0x10; 9121 current_cc = cond; 9122 9123 /* If the condition is a negative condition, invert the mask. */ 9124 if ((cond & 0x1) == 0x0) 9125 { 9126 unsigned int mask = inst.instruction & 0x000f; 9127 9128 if ((mask & 0x7) == 0) 9129 /* no conversion needed */; 9130 else if ((mask & 0x3) == 0) 9131 mask ^= 0x8; 9132 else if ((mask & 0x1) == 0) 9133 mask ^= 0xC; 9134 else 9135 mask ^= 0xE; 9136 9137 inst.instruction &= 0xfff0; 9138 inst.instruction |= mask; 9139 } 9140 9141 inst.instruction |= cond << 4; 9142} 9143 9144/* Helper function used for both push/pop and ldm/stm. */ 9145static void 9146encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback) 9147{ 9148 bfd_boolean load; 9149 9150 load = (inst.instruction & (1 << 20)) != 0; 9151 9152 if (mask & (1 << 13)) 9153 inst.error = _("SP not allowed in register list"); 9154 if (load) 9155 { 9156 if (mask & (1 << 14) 9157 && mask & (1 << 15)) 9158 inst.error = _("LR and PC should not both be in register list"); 9159 9160 if ((mask & (1 << base)) != 0 9161 && writeback) 9162 as_warn (_("base register should not be in register list " 9163 "when written back")); 9164 } 9165 else 9166 { 9167 if (mask & (1 << 15)) 9168 inst.error = _("PC not allowed in register list"); 9169 9170 if (mask & (1 << base)) 9171 as_warn (_("value stored for r%d is UNPREDICTABLE"), base); 9172 } 9173 9174 if ((mask & (mask - 1)) == 0) 9175 { 9176 /* Single register transfers implemented as str/ldr. */ 9177 if (writeback) 9178 { 9179 if (inst.instruction & (1 << 23)) 9180 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */ 9181 else 9182 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */ 9183 } 9184 else 9185 { 9186 if (inst.instruction & (1 << 23)) 9187 inst.instruction = 0x00800000; /* ia -> [base] */ 9188 else 9189 inst.instruction = 0x00000c04; /* db -> [base, #-4] */ 9190 } 9191 9192 inst.instruction |= 0xf8400000; 9193 if (load) 9194 inst.instruction |= 0x00100000; 9195 9196 mask = ffs(mask) - 1; 9197 mask <<= 12; 9198 } 9199 else if (writeback) 9200 inst.instruction |= WRITE_BACK; 9201 9202 inst.instruction |= mask; 9203 inst.instruction |= base << 16; 9204} 9205 9206static void 9207do_t_ldmstm (void) 9208{ 9209 /* This really doesn't seem worth it. */ 9210 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 9211 _("expression too complex")); 9212 constraint (inst.operands[1].writeback, 9213 _("Thumb load/store multiple does not support {reglist}^")); 9214 9215 if (unified_syntax) 9216 { 9217 bfd_boolean narrow; 9218 unsigned mask; 9219 9220 narrow = FALSE; 9221 /* See if we can use a 16-bit instruction. */ 9222 if (inst.instruction < 0xffff /* not ldmdb/stmdb */ 9223 && inst.size_req != 4 9224 && !(inst.operands[1].imm & ~0xff)) 9225 { 9226 mask = 1 << inst.operands[0].reg; 9227 9228 if (inst.operands[0].reg <= 7 9229 && (inst.instruction == T_MNEM_stmia 9230 ? inst.operands[0].writeback 9231 : (inst.operands[0].writeback 9232 == !(inst.operands[1].imm & mask)))) 9233 { 9234 if (inst.instruction == T_MNEM_stmia 9235 && (inst.operands[1].imm & mask) 9236 && (inst.operands[1].imm & (mask - 1))) 9237 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9238 inst.operands[0].reg); 9239 9240 inst.instruction = THUMB_OP16 (inst.instruction); 9241 inst.instruction |= inst.operands[0].reg << 8; 9242 inst.instruction |= inst.operands[1].imm; 9243 narrow = TRUE; 9244 } 9245 else if (inst.operands[0] .reg == REG_SP 9246 && inst.operands[0].writeback) 9247 { 9248 inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia 9249 ? T_MNEM_push : T_MNEM_pop); 9250 inst.instruction |= inst.operands[1].imm; 9251 narrow = TRUE; 9252 } 9253 } 9254 9255 if (!narrow) 9256 { 9257 if (inst.instruction < 0xffff) 9258 inst.instruction = THUMB_OP32 (inst.instruction); 9259 9260 encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm, 9261 inst.operands[0].writeback); 9262 } 9263 } 9264 else 9265 { 9266 constraint (inst.operands[0].reg > 7 9267 || (inst.operands[1].imm & ~0xff), BAD_HIREG); 9268 constraint (inst.instruction != T_MNEM_ldmia 9269 && inst.instruction != T_MNEM_stmia, 9270 _("Thumb-2 instruction only valid in unified syntax")); 9271 if (inst.instruction == T_MNEM_stmia) 9272 { 9273 if (!inst.operands[0].writeback) 9274 as_warn (_("this instruction will write back the base register")); 9275 if ((inst.operands[1].imm & (1 << inst.operands[0].reg)) 9276 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1))) 9277 as_warn (_("value stored for r%d is UNPREDICTABLE"), 9278 inst.operands[0].reg); 9279 } 9280 else 9281 { 9282 if (!inst.operands[0].writeback 9283 && !(inst.operands[1].imm & (1 << inst.operands[0].reg))) 9284 as_warn (_("this instruction will write back the base register")); 9285 else if (inst.operands[0].writeback 9286 && (inst.operands[1].imm & (1 << inst.operands[0].reg))) 9287 as_warn (_("this instruction will not write back the base register")); 9288 } 9289 9290 inst.instruction = THUMB_OP16 (inst.instruction); 9291 inst.instruction |= inst.operands[0].reg << 8; 9292 inst.instruction |= inst.operands[1].imm; 9293 } 9294} 9295 9296static void 9297do_t_ldrex (void) 9298{ 9299 constraint (!inst.operands[1].isreg || !inst.operands[1].preind 9300 || inst.operands[1].postind || inst.operands[1].writeback 9301 || inst.operands[1].immisreg || inst.operands[1].shifted 9302 || inst.operands[1].negative, 9303 BAD_ADDR_MODE); 9304 9305 inst.instruction |= inst.operands[0].reg << 12; 9306 inst.instruction |= inst.operands[1].reg << 16; 9307 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 9308} 9309 9310static void 9311do_t_ldrexd (void) 9312{ 9313 if (!inst.operands[1].present) 9314 { 9315 constraint (inst.operands[0].reg == REG_LR, 9316 _("r14 not allowed as first register " 9317 "when second register is omitted")); 9318 inst.operands[1].reg = inst.operands[0].reg + 1; 9319 } 9320 constraint (inst.operands[0].reg == inst.operands[1].reg, 9321 BAD_OVERLAP); 9322 9323 inst.instruction |= inst.operands[0].reg << 12; 9324 inst.instruction |= inst.operands[1].reg << 8; 9325 inst.instruction |= inst.operands[2].reg << 16; 9326} 9327 9328static void 9329do_t_ldst (void) 9330{ 9331 unsigned long opcode; 9332 int Rn; 9333 9334 opcode = inst.instruction; 9335 if (unified_syntax) 9336 { 9337 if (!inst.operands[1].isreg) 9338 { 9339 if (opcode <= 0xffff) 9340 inst.instruction = THUMB_OP32 (opcode); 9341 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9342 return; 9343 } 9344 if (inst.operands[1].isreg 9345 && !inst.operands[1].writeback 9346 && !inst.operands[1].shifted && !inst.operands[1].postind 9347 && !inst.operands[1].negative && inst.operands[0].reg <= 7 9348 && opcode <= 0xffff 9349 && inst.size_req != 4) 9350 { 9351 /* Insn may have a 16-bit form. */ 9352 Rn = inst.operands[1].reg; 9353 if (inst.operands[1].immisreg) 9354 { 9355 inst.instruction = THUMB_OP16 (opcode); 9356 /* [Rn, Ri] */ 9357 if (Rn <= 7 && inst.operands[1].imm <= 7) 9358 goto op16; 9359 } 9360 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh 9361 && opcode != T_MNEM_ldrsb) 9362 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) 9363 || (Rn == REG_SP && opcode == T_MNEM_str)) 9364 { 9365 /* [Rn, #const] */ 9366 if (Rn > 7) 9367 { 9368 if (Rn == REG_PC) 9369 { 9370 if (inst.reloc.pc_rel) 9371 opcode = T_MNEM_ldr_pc2; 9372 else 9373 opcode = T_MNEM_ldr_pc; 9374 } 9375 else 9376 { 9377 if (opcode == T_MNEM_ldr) 9378 opcode = T_MNEM_ldr_sp; 9379 else 9380 opcode = T_MNEM_str_sp; 9381 } 9382 inst.instruction = inst.operands[0].reg << 8; 9383 } 9384 else 9385 { 9386 inst.instruction = inst.operands[0].reg; 9387 inst.instruction |= inst.operands[1].reg << 3; 9388 } 9389 inst.instruction |= THUMB_OP16 (opcode); 9390 if (inst.size_req == 2) 9391 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9392 else 9393 inst.relax = opcode; 9394 return; 9395 } 9396 } 9397 /* Definitely a 32-bit variant. */ 9398 inst.instruction = THUMB_OP32 (opcode); 9399 inst.instruction |= inst.operands[0].reg << 12; 9400 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE); 9401 return; 9402 } 9403 9404 constraint (inst.operands[0].reg > 7, BAD_HIREG); 9405 9406 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb) 9407 { 9408 /* Only [Rn,Rm] is acceptable. */ 9409 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG); 9410 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg 9411 || inst.operands[1].postind || inst.operands[1].shifted 9412 || inst.operands[1].negative, 9413 _("Thumb does not support this addressing mode")); 9414 inst.instruction = THUMB_OP16 (inst.instruction); 9415 goto op16; 9416 } 9417 9418 inst.instruction = THUMB_OP16 (inst.instruction); 9419 if (!inst.operands[1].isreg) 9420 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE)) 9421 return; 9422 9423 constraint (!inst.operands[1].preind 9424 || inst.operands[1].shifted 9425 || inst.operands[1].writeback, 9426 _("Thumb does not support this addressing mode")); 9427 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP) 9428 { 9429 constraint (inst.instruction & 0x0600, 9430 _("byte or halfword not valid for base register")); 9431 constraint (inst.operands[1].reg == REG_PC 9432 && !(inst.instruction & THUMB_LOAD_BIT), 9433 _("r15 based store not allowed")); 9434 constraint (inst.operands[1].immisreg, 9435 _("invalid base register for register offset")); 9436 9437 if (inst.operands[1].reg == REG_PC) 9438 inst.instruction = T_OPCODE_LDR_PC; 9439 else if (inst.instruction & THUMB_LOAD_BIT) 9440 inst.instruction = T_OPCODE_LDR_SP; 9441 else 9442 inst.instruction = T_OPCODE_STR_SP; 9443 9444 inst.instruction |= inst.operands[0].reg << 8; 9445 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9446 return; 9447 } 9448 9449 constraint (inst.operands[1].reg > 7, BAD_HIREG); 9450 if (!inst.operands[1].immisreg) 9451 { 9452 /* Immediate offset. */ 9453 inst.instruction |= inst.operands[0].reg; 9454 inst.instruction |= inst.operands[1].reg << 3; 9455 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET; 9456 return; 9457 } 9458 9459 /* Register offset. */ 9460 constraint (inst.operands[1].imm > 7, BAD_HIREG); 9461 constraint (inst.operands[1].negative, 9462 _("Thumb does not support this addressing mode")); 9463 9464 op16: 9465 switch (inst.instruction) 9466 { 9467 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break; 9468 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break; 9469 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break; 9470 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break; 9471 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break; 9472 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break; 9473 case 0x5600 /* ldrsb */: 9474 case 0x5e00 /* ldrsh */: break; 9475 default: abort (); 9476 } 9477 9478 inst.instruction |= inst.operands[0].reg; 9479 inst.instruction |= inst.operands[1].reg << 3; 9480 inst.instruction |= inst.operands[1].imm << 6; 9481} 9482 9483static void 9484do_t_ldstd (void) 9485{ 9486 if (!inst.operands[1].present) 9487 { 9488 inst.operands[1].reg = inst.operands[0].reg + 1; 9489 constraint (inst.operands[0].reg == REG_LR, 9490 _("r14 not allowed here")); 9491 } 9492 inst.instruction |= inst.operands[0].reg << 12; 9493 inst.instruction |= inst.operands[1].reg << 8; 9494 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE); 9495 9496} 9497 9498static void 9499do_t_ldstt (void) 9500{ 9501 inst.instruction |= inst.operands[0].reg << 12; 9502 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE); 9503} 9504 9505static void 9506do_t_mla (void) 9507{ 9508 inst.instruction |= inst.operands[0].reg << 8; 9509 inst.instruction |= inst.operands[1].reg << 16; 9510 inst.instruction |= inst.operands[2].reg; 9511 inst.instruction |= inst.operands[3].reg << 12; 9512} 9513 9514static void 9515do_t_mlal (void) 9516{ 9517 inst.instruction |= inst.operands[0].reg << 12; 9518 inst.instruction |= inst.operands[1].reg << 8; 9519 inst.instruction |= inst.operands[2].reg << 16; 9520 inst.instruction |= inst.operands[3].reg; 9521} 9522 9523static void 9524do_t_mov_cmp (void) 9525{ 9526 if (unified_syntax) 9527 { 9528 int r0off = (inst.instruction == T_MNEM_mov 9529 || inst.instruction == T_MNEM_movs) ? 8 : 16; 9530 unsigned long opcode; 9531 bfd_boolean narrow; 9532 bfd_boolean low_regs; 9533 9534 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7); 9535 opcode = inst.instruction; 9536 if (current_it_mask) 9537 narrow = opcode != T_MNEM_movs; 9538 else 9539 narrow = opcode != T_MNEM_movs || low_regs; 9540 if (inst.size_req == 4 9541 || inst.operands[1].shifted) 9542 narrow = FALSE; 9543 9544 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */ 9545 if (opcode == T_MNEM_movs && inst.operands[1].isreg 9546 && !inst.operands[1].shifted 9547 && inst.operands[0].reg == REG_PC 9548 && inst.operands[1].reg == REG_LR) 9549 { 9550 inst.instruction = T2_SUBS_PC_LR; 9551 return; 9552 } 9553 9554 if (!inst.operands[1].isreg) 9555 { 9556 /* Immediate operand. */ 9557 if (current_it_mask == 0 && opcode == T_MNEM_mov) 9558 narrow = 0; 9559 if (low_regs && narrow) 9560 { 9561 inst.instruction = THUMB_OP16 (opcode); 9562 inst.instruction |= inst.operands[0].reg << 8; 9563 if (inst.size_req == 2) 9564 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9565 else 9566 inst.relax = opcode; 9567 } 9568 else 9569 { 9570 inst.instruction = THUMB_OP32 (inst.instruction); 9571 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9572 inst.instruction |= inst.operands[0].reg << r0off; 9573 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9574 } 9575 } 9576 else if (inst.operands[1].shifted && inst.operands[1].immisreg 9577 && (inst.instruction == T_MNEM_mov 9578 || inst.instruction == T_MNEM_movs)) 9579 { 9580 /* Register shifts are encoded as separate shift instructions. */ 9581 bfd_boolean flags = (inst.instruction == T_MNEM_movs); 9582 9583 if (current_it_mask) 9584 narrow = !flags; 9585 else 9586 narrow = flags; 9587 9588 if (inst.size_req == 4) 9589 narrow = FALSE; 9590 9591 if (!low_regs || inst.operands[1].imm > 7) 9592 narrow = FALSE; 9593 9594 if (inst.operands[0].reg != inst.operands[1].reg) 9595 narrow = FALSE; 9596 9597 switch (inst.operands[1].shift_kind) 9598 { 9599 case SHIFT_LSL: 9600 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl); 9601 break; 9602 case SHIFT_ASR: 9603 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr); 9604 break; 9605 case SHIFT_LSR: 9606 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr); 9607 break; 9608 case SHIFT_ROR: 9609 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror); 9610 break; 9611 default: 9612 abort(); 9613 } 9614 9615 inst.instruction = opcode; 9616 if (narrow) 9617 { 9618 inst.instruction |= inst.operands[0].reg; 9619 inst.instruction |= inst.operands[1].imm << 3; 9620 } 9621 else 9622 { 9623 if (flags) 9624 inst.instruction |= CONDS_BIT; 9625 9626 inst.instruction |= inst.operands[0].reg << 8; 9627 inst.instruction |= inst.operands[1].reg << 16; 9628 inst.instruction |= inst.operands[1].imm; 9629 } 9630 } 9631 else if (!narrow) 9632 { 9633 /* Some mov with immediate shift have narrow variants. 9634 Register shifts are handled above. */ 9635 if (low_regs && inst.operands[1].shifted 9636 && (inst.instruction == T_MNEM_mov 9637 || inst.instruction == T_MNEM_movs)) 9638 { 9639 if (current_it_mask) 9640 narrow = (inst.instruction == T_MNEM_mov); 9641 else 9642 narrow = (inst.instruction == T_MNEM_movs); 9643 } 9644 9645 if (narrow) 9646 { 9647 switch (inst.operands[1].shift_kind) 9648 { 9649 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 9650 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 9651 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 9652 default: narrow = FALSE; break; 9653 } 9654 } 9655 9656 if (narrow) 9657 { 9658 inst.instruction |= inst.operands[0].reg; 9659 inst.instruction |= inst.operands[1].reg << 3; 9660 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 9661 } 9662 else 9663 { 9664 inst.instruction = THUMB_OP32 (inst.instruction); 9665 inst.instruction |= inst.operands[0].reg << r0off; 9666 encode_thumb32_shifted_operand (1); 9667 } 9668 } 9669 else 9670 switch (inst.instruction) 9671 { 9672 case T_MNEM_mov: 9673 inst.instruction = T_OPCODE_MOV_HR; 9674 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9675 inst.instruction |= (inst.operands[0].reg & 0x7); 9676 inst.instruction |= inst.operands[1].reg << 3; 9677 break; 9678 9679 case T_MNEM_movs: 9680 /* We know we have low registers at this point. 9681 Generate ADD Rd, Rs, #0. */ 9682 inst.instruction = T_OPCODE_ADD_I3; 9683 inst.instruction |= inst.operands[0].reg; 9684 inst.instruction |= inst.operands[1].reg << 3; 9685 break; 9686 9687 case T_MNEM_cmp: 9688 if (low_regs) 9689 { 9690 inst.instruction = T_OPCODE_CMP_LR; 9691 inst.instruction |= inst.operands[0].reg; 9692 inst.instruction |= inst.operands[1].reg << 3; 9693 } 9694 else 9695 { 9696 inst.instruction = T_OPCODE_CMP_HR; 9697 inst.instruction |= (inst.operands[0].reg & 0x8) << 4; 9698 inst.instruction |= (inst.operands[0].reg & 0x7); 9699 inst.instruction |= inst.operands[1].reg << 3; 9700 } 9701 break; 9702 } 9703 return; 9704 } 9705 9706 inst.instruction = THUMB_OP16 (inst.instruction); 9707 if (inst.operands[1].isreg) 9708 { 9709 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8) 9710 { 9711 /* A move of two lowregs is encoded as ADD Rd, Rs, #0 9712 since a MOV instruction produces unpredictable results. */ 9713 if (inst.instruction == T_OPCODE_MOV_I8) 9714 inst.instruction = T_OPCODE_ADD_I3; 9715 else 9716 inst.instruction = T_OPCODE_CMP_LR; 9717 9718 inst.instruction |= inst.operands[0].reg; 9719 inst.instruction |= inst.operands[1].reg << 3; 9720 } 9721 else 9722 { 9723 if (inst.instruction == T_OPCODE_MOV_I8) 9724 inst.instruction = T_OPCODE_MOV_HR; 9725 else 9726 inst.instruction = T_OPCODE_CMP_HR; 9727 do_t_cpy (); 9728 } 9729 } 9730 else 9731 { 9732 constraint (inst.operands[0].reg > 7, 9733 _("only lo regs allowed with immediate")); 9734 inst.instruction |= inst.operands[0].reg << 8; 9735 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM; 9736 } 9737} 9738 9739static void 9740do_t_mov16 (void) 9741{ 9742 bfd_vma imm; 9743 bfd_boolean top; 9744 9745 top = (inst.instruction & 0x00800000) != 0; 9746 if (inst.reloc.type == BFD_RELOC_ARM_MOVW) 9747 { 9748 constraint (top, _(":lower16: not allowed this instruction")); 9749 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW; 9750 } 9751 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT) 9752 { 9753 constraint (!top, _(":upper16: not allowed this instruction")); 9754 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT; 9755 } 9756 9757 inst.instruction |= inst.operands[0].reg << 8; 9758 if (inst.reloc.type == BFD_RELOC_UNUSED) 9759 { 9760 imm = inst.reloc.exp.X_add_number; 9761 inst.instruction |= (imm & 0xf000) << 4; 9762 inst.instruction |= (imm & 0x0800) << 15; 9763 inst.instruction |= (imm & 0x0700) << 4; 9764 inst.instruction |= (imm & 0x00ff); 9765 } 9766} 9767 9768static void 9769do_t_mvn_tst (void) 9770{ 9771 if (unified_syntax) 9772 { 9773 int r0off = (inst.instruction == T_MNEM_mvn 9774 || inst.instruction == T_MNEM_mvns) ? 8 : 16; 9775 bfd_boolean narrow; 9776 9777 if (inst.size_req == 4 9778 || inst.instruction > 0xffff 9779 || inst.operands[1].shifted 9780 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9781 narrow = FALSE; 9782 else if (inst.instruction == T_MNEM_cmn) 9783 narrow = TRUE; 9784 else if (THUMB_SETS_FLAGS (inst.instruction)) 9785 narrow = (current_it_mask == 0); 9786 else 9787 narrow = (current_it_mask != 0); 9788 9789 if (!inst.operands[1].isreg) 9790 { 9791 /* For an immediate, we always generate a 32-bit opcode; 9792 section relaxation will shrink it later if possible. */ 9793 if (inst.instruction < 0xffff) 9794 inst.instruction = THUMB_OP32 (inst.instruction); 9795 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 9796 inst.instruction |= inst.operands[0].reg << r0off; 9797 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 9798 } 9799 else 9800 { 9801 /* See if we can do this with a 16-bit instruction. */ 9802 if (narrow) 9803 { 9804 inst.instruction = THUMB_OP16 (inst.instruction); 9805 inst.instruction |= inst.operands[0].reg; 9806 inst.instruction |= inst.operands[1].reg << 3; 9807 } 9808 else 9809 { 9810 constraint (inst.operands[1].shifted 9811 && inst.operands[1].immisreg, 9812 _("shift must be constant")); 9813 if (inst.instruction < 0xffff) 9814 inst.instruction = THUMB_OP32 (inst.instruction); 9815 inst.instruction |= inst.operands[0].reg << r0off; 9816 encode_thumb32_shifted_operand (1); 9817 } 9818 } 9819 } 9820 else 9821 { 9822 constraint (inst.instruction > 0xffff 9823 || inst.instruction == T_MNEM_mvns, BAD_THUMB32); 9824 constraint (!inst.operands[1].isreg || inst.operands[1].shifted, 9825 _("unshifted register required")); 9826 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9827 BAD_HIREG); 9828 9829 inst.instruction = THUMB_OP16 (inst.instruction); 9830 inst.instruction |= inst.operands[0].reg; 9831 inst.instruction |= inst.operands[1].reg << 3; 9832 } 9833} 9834 9835static void 9836do_t_mrs (void) 9837{ 9838 int flags; 9839 9840 if (do_vfp_nsyn_mrs () == SUCCESS) 9841 return; 9842 9843 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT); 9844 if (flags == 0) 9845 { 9846 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9847 _("selected processor does not support " 9848 "requested special purpose register")); 9849 } 9850 else 9851 { 9852 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9853 _("selected processor does not support " 9854 "requested special purpose register %x")); 9855 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */ 9856 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f), 9857 _("'CPSR' or 'SPSR' expected")); 9858 } 9859 9860 inst.instruction |= inst.operands[0].reg << 8; 9861 inst.instruction |= (flags & SPSR_BIT) >> 2; 9862 inst.instruction |= inst.operands[1].imm & 0xff; 9863} 9864 9865static void 9866do_t_msr (void) 9867{ 9868 int flags; 9869 9870 if (do_vfp_nsyn_msr () == SUCCESS) 9871 return; 9872 9873 constraint (!inst.operands[1].isreg, 9874 _("Thumb encoding does not support an immediate here")); 9875 flags = inst.operands[0].imm; 9876 if (flags & ~0xff) 9877 { 9878 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1), 9879 _("selected processor does not support " 9880 "requested special purpose register")); 9881 } 9882 else 9883 { 9884 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m), 9885 _("selected processor does not support " 9886 "requested special purpose register")); 9887 flags |= PSR_f; 9888 } 9889 inst.instruction |= (flags & SPSR_BIT) >> 2; 9890 inst.instruction |= (flags & ~SPSR_BIT) >> 8; 9891 inst.instruction |= (flags & 0xff); 9892 inst.instruction |= inst.operands[1].reg << 16; 9893} 9894 9895static void 9896do_t_mul (void) 9897{ 9898 if (!inst.operands[2].present) 9899 inst.operands[2].reg = inst.operands[0].reg; 9900 9901 /* There is no 32-bit MULS and no 16-bit MUL. */ 9902 if (unified_syntax && inst.instruction == T_MNEM_mul) 9903 { 9904 inst.instruction = THUMB_OP32 (inst.instruction); 9905 inst.instruction |= inst.operands[0].reg << 8; 9906 inst.instruction |= inst.operands[1].reg << 16; 9907 inst.instruction |= inst.operands[2].reg << 0; 9908 } 9909 else 9910 { 9911 constraint (!unified_syntax 9912 && inst.instruction == T_MNEM_muls, BAD_THUMB32); 9913 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9914 BAD_HIREG); 9915 9916 inst.instruction = THUMB_OP16 (inst.instruction); 9917 inst.instruction |= inst.operands[0].reg; 9918 9919 if (inst.operands[0].reg == inst.operands[1].reg) 9920 inst.instruction |= inst.operands[2].reg << 3; 9921 else if (inst.operands[0].reg == inst.operands[2].reg) 9922 inst.instruction |= inst.operands[1].reg << 3; 9923 else 9924 constraint (1, _("dest must overlap one source register")); 9925 } 9926} 9927 9928static void 9929do_t_mull (void) 9930{ 9931 inst.instruction |= inst.operands[0].reg << 12; 9932 inst.instruction |= inst.operands[1].reg << 8; 9933 inst.instruction |= inst.operands[2].reg << 16; 9934 inst.instruction |= inst.operands[3].reg; 9935 9936 if (inst.operands[0].reg == inst.operands[1].reg) 9937 as_tsktsk (_("rdhi and rdlo must be different")); 9938} 9939 9940static void 9941do_t_nop (void) 9942{ 9943 if (unified_syntax) 9944 { 9945 if (inst.size_req == 4 || inst.operands[0].imm > 15) 9946 { 9947 inst.instruction = THUMB_OP32 (inst.instruction); 9948 inst.instruction |= inst.operands[0].imm; 9949 } 9950 else 9951 { 9952 inst.instruction = THUMB_OP16 (inst.instruction); 9953 inst.instruction |= inst.operands[0].imm << 4; 9954 } 9955 } 9956 else 9957 { 9958 constraint (inst.operands[0].present, 9959 _("Thumb does not support NOP with hints")); 9960 inst.instruction = 0x46c0; 9961 } 9962} 9963 9964static void 9965do_t_neg (void) 9966{ 9967 if (unified_syntax) 9968 { 9969 bfd_boolean narrow; 9970 9971 if (THUMB_SETS_FLAGS (inst.instruction)) 9972 narrow = (current_it_mask == 0); 9973 else 9974 narrow = (current_it_mask != 0); 9975 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 9976 narrow = FALSE; 9977 if (inst.size_req == 4) 9978 narrow = FALSE; 9979 9980 if (!narrow) 9981 { 9982 inst.instruction = THUMB_OP32 (inst.instruction); 9983 inst.instruction |= inst.operands[0].reg << 8; 9984 inst.instruction |= inst.operands[1].reg << 16; 9985 } 9986 else 9987 { 9988 inst.instruction = THUMB_OP16 (inst.instruction); 9989 inst.instruction |= inst.operands[0].reg; 9990 inst.instruction |= inst.operands[1].reg << 3; 9991 } 9992 } 9993 else 9994 { 9995 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7, 9996 BAD_HIREG); 9997 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 9998 9999 inst.instruction = THUMB_OP16 (inst.instruction); 10000 inst.instruction |= inst.operands[0].reg; 10001 inst.instruction |= inst.operands[1].reg << 3; 10002 } 10003} 10004 10005static void 10006do_t_pkhbt (void) 10007{ 10008 inst.instruction |= inst.operands[0].reg << 8; 10009 inst.instruction |= inst.operands[1].reg << 16; 10010 inst.instruction |= inst.operands[2].reg; 10011 if (inst.operands[3].present) 10012 { 10013 unsigned int val = inst.reloc.exp.X_add_number; 10014 constraint (inst.reloc.exp.X_op != O_constant, 10015 _("expression too complex")); 10016 inst.instruction |= (val & 0x1c) << 10; 10017 inst.instruction |= (val & 0x03) << 6; 10018 } 10019} 10020 10021static void 10022do_t_pkhtb (void) 10023{ 10024 if (!inst.operands[3].present) 10025 inst.instruction &= ~0x00000020; 10026 do_t_pkhbt (); 10027} 10028 10029static void 10030do_t_pld (void) 10031{ 10032 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE); 10033} 10034 10035static void 10036do_t_push_pop (void) 10037{ 10038 unsigned mask; 10039 10040 constraint (inst.operands[0].writeback, 10041 _("push/pop do not support {reglist}^")); 10042 constraint (inst.reloc.type != BFD_RELOC_UNUSED, 10043 _("expression too complex")); 10044 10045 mask = inst.operands[0].imm; 10046 if ((mask & ~0xff) == 0) 10047 inst.instruction = THUMB_OP16 (inst.instruction) | mask; 10048 else if ((inst.instruction == T_MNEM_push 10049 && (mask & ~0xff) == 1 << REG_LR) 10050 || (inst.instruction == T_MNEM_pop 10051 && (mask & ~0xff) == 1 << REG_PC)) 10052 { 10053 inst.instruction = THUMB_OP16 (inst.instruction); 10054 inst.instruction |= THUMB_PP_PC_LR; 10055 inst.instruction |= mask & 0xff; 10056 } 10057 else if (unified_syntax) 10058 { 10059 inst.instruction = THUMB_OP32 (inst.instruction); 10060 encode_thumb2_ldmstm(13, mask, TRUE); 10061 } 10062 else 10063 { 10064 inst.error = _("invalid register list to push/pop instruction"); 10065 return; 10066 } 10067} 10068 10069static void 10070do_t_rbit (void) 10071{ 10072 inst.instruction |= inst.operands[0].reg << 8; 10073 inst.instruction |= inst.operands[1].reg << 16; 10074} 10075 10076static void 10077do_t_rd_rm (void) 10078{ 10079 inst.instruction |= inst.operands[0].reg << 8; 10080 inst.instruction |= inst.operands[1].reg; 10081} 10082 10083static void 10084do_t_rev (void) 10085{ 10086 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10087 && inst.size_req != 4) 10088 { 10089 inst.instruction = THUMB_OP16 (inst.instruction); 10090 inst.instruction |= inst.operands[0].reg; 10091 inst.instruction |= inst.operands[1].reg << 3; 10092 } 10093 else if (unified_syntax) 10094 { 10095 inst.instruction = THUMB_OP32 (inst.instruction); 10096 inst.instruction |= inst.operands[0].reg << 8; 10097 inst.instruction |= inst.operands[1].reg << 16; 10098 inst.instruction |= inst.operands[1].reg; 10099 } 10100 else 10101 inst.error = BAD_HIREG; 10102} 10103 10104static void 10105do_t_rsb (void) 10106{ 10107 int Rd, Rs; 10108 10109 Rd = inst.operands[0].reg; 10110 Rs = (inst.operands[1].present 10111 ? inst.operands[1].reg /* Rd, Rs, foo */ 10112 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */ 10113 10114 inst.instruction |= Rd << 8; 10115 inst.instruction |= Rs << 16; 10116 if (!inst.operands[2].isreg) 10117 { 10118 bfd_boolean narrow; 10119 10120 if ((inst.instruction & 0x00100000) != 0) 10121 narrow = (current_it_mask == 0); 10122 else 10123 narrow = (current_it_mask != 0); 10124 10125 if (Rd > 7 || Rs > 7) 10126 narrow = FALSE; 10127 10128 if (inst.size_req == 4 || !unified_syntax) 10129 narrow = FALSE; 10130 10131 if (inst.reloc.exp.X_op != O_constant 10132 || inst.reloc.exp.X_add_number != 0) 10133 narrow = FALSE; 10134 10135 /* Turn rsb #0 into 16-bit neg. We should probably do this via 10136 relaxation, but it doesn't seem worth the hassle. */ 10137 if (narrow) 10138 { 10139 inst.reloc.type = BFD_RELOC_UNUSED; 10140 inst.instruction = THUMB_OP16 (T_MNEM_negs); 10141 inst.instruction |= Rs << 3; 10142 inst.instruction |= Rd; 10143 } 10144 else 10145 { 10146 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000; 10147 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE; 10148 } 10149 } 10150 else 10151 encode_thumb32_shifted_operand (2); 10152} 10153 10154static void 10155do_t_setend (void) 10156{ 10157 constraint (current_it_mask, BAD_NOT_IT); 10158 if (inst.operands[0].imm) 10159 inst.instruction |= 0x8; 10160} 10161 10162static void 10163do_t_shift (void) 10164{ 10165 if (!inst.operands[1].present) 10166 inst.operands[1].reg = inst.operands[0].reg; 10167 10168 if (unified_syntax) 10169 { 10170 bfd_boolean narrow; 10171 int shift_kind; 10172 10173 switch (inst.instruction) 10174 { 10175 case T_MNEM_asr: 10176 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break; 10177 case T_MNEM_lsl: 10178 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break; 10179 case T_MNEM_lsr: 10180 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break; 10181 case T_MNEM_ror: 10182 case T_MNEM_rors: shift_kind = SHIFT_ROR; break; 10183 default: abort (); 10184 } 10185 10186 if (THUMB_SETS_FLAGS (inst.instruction)) 10187 narrow = (current_it_mask == 0); 10188 else 10189 narrow = (current_it_mask != 0); 10190 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7) 10191 narrow = FALSE; 10192 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR) 10193 narrow = FALSE; 10194 if (inst.operands[2].isreg 10195 && (inst.operands[1].reg != inst.operands[0].reg 10196 || inst.operands[2].reg > 7)) 10197 narrow = FALSE; 10198 if (inst.size_req == 4) 10199 narrow = FALSE; 10200 10201 if (!narrow) 10202 { 10203 if (inst.operands[2].isreg) 10204 { 10205 inst.instruction = THUMB_OP32 (inst.instruction); 10206 inst.instruction |= inst.operands[0].reg << 8; 10207 inst.instruction |= inst.operands[1].reg << 16; 10208 inst.instruction |= inst.operands[2].reg; 10209 } 10210 else 10211 { 10212 inst.operands[1].shifted = 1; 10213 inst.operands[1].shift_kind = shift_kind; 10214 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction) 10215 ? T_MNEM_movs : T_MNEM_mov); 10216 inst.instruction |= inst.operands[0].reg << 8; 10217 encode_thumb32_shifted_operand (1); 10218 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */ 10219 inst.reloc.type = BFD_RELOC_UNUSED; 10220 } 10221 } 10222 else 10223 { 10224 if (inst.operands[2].isreg) 10225 { 10226 switch (shift_kind) 10227 { 10228 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break; 10229 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break; 10230 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break; 10231 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break; 10232 default: abort (); 10233 } 10234 10235 inst.instruction |= inst.operands[0].reg; 10236 inst.instruction |= inst.operands[2].reg << 3; 10237 } 10238 else 10239 { 10240 switch (shift_kind) 10241 { 10242 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break; 10243 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break; 10244 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break; 10245 default: abort (); 10246 } 10247 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10248 inst.instruction |= inst.operands[0].reg; 10249 inst.instruction |= inst.operands[1].reg << 3; 10250 } 10251 } 10252 } 10253 else 10254 { 10255 constraint (inst.operands[0].reg > 7 10256 || inst.operands[1].reg > 7, BAD_HIREG); 10257 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32); 10258 10259 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */ 10260 { 10261 constraint (inst.operands[2].reg > 7, BAD_HIREG); 10262 constraint (inst.operands[0].reg != inst.operands[1].reg, 10263 _("source1 and dest must be same register")); 10264 10265 switch (inst.instruction) 10266 { 10267 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break; 10268 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break; 10269 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break; 10270 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break; 10271 default: abort (); 10272 } 10273 10274 inst.instruction |= inst.operands[0].reg; 10275 inst.instruction |= inst.operands[2].reg << 3; 10276 } 10277 else 10278 { 10279 switch (inst.instruction) 10280 { 10281 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break; 10282 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break; 10283 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break; 10284 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return; 10285 default: abort (); 10286 } 10287 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT; 10288 inst.instruction |= inst.operands[0].reg; 10289 inst.instruction |= inst.operands[1].reg << 3; 10290 } 10291 } 10292} 10293 10294static void 10295do_t_simd (void) 10296{ 10297 inst.instruction |= inst.operands[0].reg << 8; 10298 inst.instruction |= inst.operands[1].reg << 16; 10299 inst.instruction |= inst.operands[2].reg; 10300} 10301 10302static void 10303do_t_smc (void) 10304{ 10305 unsigned int value = inst.reloc.exp.X_add_number; 10306 constraint (inst.reloc.exp.X_op != O_constant, 10307 _("expression too complex")); 10308 inst.reloc.type = BFD_RELOC_UNUSED; 10309 inst.instruction |= (value & 0xf000) >> 12; 10310 inst.instruction |= (value & 0x0ff0); 10311 inst.instruction |= (value & 0x000f) << 16; 10312} 10313 10314static void 10315do_t_ssat (void) 10316{ 10317 inst.instruction |= inst.operands[0].reg << 8; 10318 inst.instruction |= inst.operands[1].imm - 1; 10319 inst.instruction |= inst.operands[2].reg << 16; 10320 10321 if (inst.operands[3].present) 10322 { 10323 constraint (inst.reloc.exp.X_op != O_constant, 10324 _("expression too complex")); 10325 10326 if (inst.reloc.exp.X_add_number != 0) 10327 { 10328 if (inst.operands[3].shift_kind == SHIFT_ASR) 10329 inst.instruction |= 0x00200000; /* sh bit */ 10330 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10331 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10332 } 10333 inst.reloc.type = BFD_RELOC_UNUSED; 10334 } 10335} 10336 10337static void 10338do_t_ssat16 (void) 10339{ 10340 inst.instruction |= inst.operands[0].reg << 8; 10341 inst.instruction |= inst.operands[1].imm - 1; 10342 inst.instruction |= inst.operands[2].reg << 16; 10343} 10344 10345static void 10346do_t_strex (void) 10347{ 10348 constraint (!inst.operands[2].isreg || !inst.operands[2].preind 10349 || inst.operands[2].postind || inst.operands[2].writeback 10350 || inst.operands[2].immisreg || inst.operands[2].shifted 10351 || inst.operands[2].negative, 10352 BAD_ADDR_MODE); 10353 10354 inst.instruction |= inst.operands[0].reg << 8; 10355 inst.instruction |= inst.operands[1].reg << 12; 10356 inst.instruction |= inst.operands[2].reg << 16; 10357 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8; 10358} 10359 10360static void 10361do_t_strexd (void) 10362{ 10363 if (!inst.operands[2].present) 10364 inst.operands[2].reg = inst.operands[1].reg + 1; 10365 10366 constraint (inst.operands[0].reg == inst.operands[1].reg 10367 || inst.operands[0].reg == inst.operands[2].reg 10368 || inst.operands[0].reg == inst.operands[3].reg 10369 || inst.operands[1].reg == inst.operands[2].reg, 10370 BAD_OVERLAP); 10371 10372 inst.instruction |= inst.operands[0].reg; 10373 inst.instruction |= inst.operands[1].reg << 12; 10374 inst.instruction |= inst.operands[2].reg << 8; 10375 inst.instruction |= inst.operands[3].reg << 16; 10376} 10377 10378static void 10379do_t_sxtah (void) 10380{ 10381 inst.instruction |= inst.operands[0].reg << 8; 10382 inst.instruction |= inst.operands[1].reg << 16; 10383 inst.instruction |= inst.operands[2].reg; 10384 inst.instruction |= inst.operands[3].imm << 4; 10385} 10386 10387static void 10388do_t_sxth (void) 10389{ 10390 if (inst.instruction <= 0xffff && inst.size_req != 4 10391 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7 10392 && (!inst.operands[2].present || inst.operands[2].imm == 0)) 10393 { 10394 inst.instruction = THUMB_OP16 (inst.instruction); 10395 inst.instruction |= inst.operands[0].reg; 10396 inst.instruction |= inst.operands[1].reg << 3; 10397 } 10398 else if (unified_syntax) 10399 { 10400 if (inst.instruction <= 0xffff) 10401 inst.instruction = THUMB_OP32 (inst.instruction); 10402 inst.instruction |= inst.operands[0].reg << 8; 10403 inst.instruction |= inst.operands[1].reg; 10404 inst.instruction |= inst.operands[2].imm << 4; 10405 } 10406 else 10407 { 10408 constraint (inst.operands[2].present && inst.operands[2].imm != 0, 10409 _("Thumb encoding does not support rotation")); 10410 constraint (1, BAD_HIREG); 10411 } 10412} 10413 10414static void 10415do_t_swi (void) 10416{ 10417 inst.reloc.type = BFD_RELOC_ARM_SWI; 10418} 10419 10420static void 10421do_t_tb (void) 10422{ 10423 int half; 10424 10425 half = (inst.instruction & 0x10) != 0; 10426 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH); 10427 constraint (inst.operands[0].immisreg, 10428 _("instruction requires register index")); 10429 constraint (inst.operands[0].imm == 15, 10430 _("PC is not a valid index register")); 10431 constraint (!half && inst.operands[0].shifted, 10432 _("instruction does not allow shifted index")); 10433 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; 10434} 10435 10436static void 10437do_t_usat (void) 10438{ 10439 inst.instruction |= inst.operands[0].reg << 8; 10440 inst.instruction |= inst.operands[1].imm; 10441 inst.instruction |= inst.operands[2].reg << 16; 10442 10443 if (inst.operands[3].present) 10444 { 10445 constraint (inst.reloc.exp.X_op != O_constant, 10446 _("expression too complex")); 10447 if (inst.reloc.exp.X_add_number != 0) 10448 { 10449 if (inst.operands[3].shift_kind == SHIFT_ASR) 10450 inst.instruction |= 0x00200000; /* sh bit */ 10451 10452 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10; 10453 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6; 10454 } 10455 inst.reloc.type = BFD_RELOC_UNUSED; 10456 } 10457} 10458 10459static void 10460do_t_usat16 (void) 10461{ 10462 inst.instruction |= inst.operands[0].reg << 8; 10463 inst.instruction |= inst.operands[1].imm; 10464 inst.instruction |= inst.operands[2].reg << 16; 10465} 10466 10467/* Neon instruction encoder helpers. */ 10468 10469/* Encodings for the different types for various Neon opcodes. */ 10470 10471/* An "invalid" code for the following tables. */ 10472#define N_INV -1u 10473 10474struct neon_tab_entry 10475{ 10476 unsigned integer; 10477 unsigned float_or_poly; 10478 unsigned scalar_or_imm; 10479}; 10480 10481/* Map overloaded Neon opcodes to their respective encodings. */ 10482#define NEON_ENC_TAB \ 10483 X(vabd, 0x0000700, 0x1200d00, N_INV), \ 10484 X(vmax, 0x0000600, 0x0000f00, N_INV), \ 10485 X(vmin, 0x0000610, 0x0200f00, N_INV), \ 10486 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \ 10487 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \ 10488 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \ 10489 X(vadd, 0x0000800, 0x0000d00, N_INV), \ 10490 X(vsub, 0x1000800, 0x0200d00, N_INV), \ 10491 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \ 10492 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \ 10493 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \ 10494 /* Register variants of the following two instructions are encoded as 10495 vcge / vcgt with the operands reversed. */ \ 10496 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \ 10497 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \ 10498 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \ 10499 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \ 10500 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \ 10501 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \ 10502 X(vmlal, 0x0800800, N_INV, 0x0800240), \ 10503 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \ 10504 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \ 10505 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \ 10506 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \ 10507 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \ 10508 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \ 10509 X(vshl, 0x0000400, N_INV, 0x0800510), \ 10510 X(vqshl, 0x0000410, N_INV, 0x0800710), \ 10511 X(vand, 0x0000110, N_INV, 0x0800030), \ 10512 X(vbic, 0x0100110, N_INV, 0x0800030), \ 10513 X(veor, 0x1000110, N_INV, N_INV), \ 10514 X(vorn, 0x0300110, N_INV, 0x0800010), \ 10515 X(vorr, 0x0200110, N_INV, 0x0800010), \ 10516 X(vmvn, 0x1b00580, N_INV, 0x0800030), \ 10517 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \ 10518 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \ 10519 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \ 10520 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \ 10521 X(vst1, 0x0000000, 0x0800000, N_INV), \ 10522 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \ 10523 X(vst2, 0x0000100, 0x0800100, N_INV), \ 10524 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \ 10525 X(vst3, 0x0000200, 0x0800200, N_INV), \ 10526 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \ 10527 X(vst4, 0x0000300, 0x0800300, N_INV), \ 10528 X(vmovn, 0x1b20200, N_INV, N_INV), \ 10529 X(vtrn, 0x1b20080, N_INV, N_INV), \ 10530 X(vqmovn, 0x1b20200, N_INV, N_INV), \ 10531 X(vqmovun, 0x1b20240, N_INV, N_INV), \ 10532 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \ 10533 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \ 10534 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \ 10535 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \ 10536 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \ 10537 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \ 10538 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV) 10539 10540enum neon_opc 10541{ 10542#define X(OPC,I,F,S) N_MNEM_##OPC 10543NEON_ENC_TAB 10544#undef X 10545}; 10546 10547static const struct neon_tab_entry neon_enc_tab[] = 10548{ 10549#define X(OPC,I,F,S) { (I), (F), (S) } 10550NEON_ENC_TAB 10551#undef X 10552}; 10553 10554#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10555#define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10556#define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10557#define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10558#define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10559#define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10560#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer) 10561#define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly) 10562#define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm) 10563#define NEON_ENC_SINGLE(X) \ 10564 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000)) 10565#define NEON_ENC_DOUBLE(X) \ 10566 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000)) 10567 10568/* Define shapes for instruction operands. The following mnemonic characters 10569 are used in this table: 10570 10571 F - VFP S<n> register 10572 D - Neon D<n> register 10573 Q - Neon Q<n> register 10574 I - Immediate 10575 S - Scalar 10576 R - ARM register 10577 L - D<n> register list 10578 10579 This table is used to generate various data: 10580 - enumerations of the form NS_DDR to be used as arguments to 10581 neon_select_shape. 10582 - a table classifying shapes into single, double, quad, mixed. 10583 - a table used to drive neon_select_shape. 10584*/ 10585 10586#define NEON_SHAPE_DEF \ 10587 X(3, (D, D, D), DOUBLE), \ 10588 X(3, (Q, Q, Q), QUAD), \ 10589 X(3, (D, D, I), DOUBLE), \ 10590 X(3, (Q, Q, I), QUAD), \ 10591 X(3, (D, D, S), DOUBLE), \ 10592 X(3, (Q, Q, S), QUAD), \ 10593 X(2, (D, D), DOUBLE), \ 10594 X(2, (Q, Q), QUAD), \ 10595 X(2, (D, S), DOUBLE), \ 10596 X(2, (Q, S), QUAD), \ 10597 X(2, (D, R), DOUBLE), \ 10598 X(2, (Q, R), QUAD), \ 10599 X(2, (D, I), DOUBLE), \ 10600 X(2, (Q, I), QUAD), \ 10601 X(3, (D, L, D), DOUBLE), \ 10602 X(2, (D, Q), MIXED), \ 10603 X(2, (Q, D), MIXED), \ 10604 X(3, (D, Q, I), MIXED), \ 10605 X(3, (Q, D, I), MIXED), \ 10606 X(3, (Q, D, D), MIXED), \ 10607 X(3, (D, Q, Q), MIXED), \ 10608 X(3, (Q, Q, D), MIXED), \ 10609 X(3, (Q, D, S), MIXED), \ 10610 X(3, (D, Q, S), MIXED), \ 10611 X(4, (D, D, D, I), DOUBLE), \ 10612 X(4, (Q, Q, Q, I), QUAD), \ 10613 X(2, (F, F), SINGLE), \ 10614 X(3, (F, F, F), SINGLE), \ 10615 X(2, (F, I), SINGLE), \ 10616 X(2, (F, D), MIXED), \ 10617 X(2, (D, F), MIXED), \ 10618 X(3, (F, F, I), MIXED), \ 10619 X(4, (R, R, F, F), SINGLE), \ 10620 X(4, (F, F, R, R), SINGLE), \ 10621 X(3, (D, R, R), DOUBLE), \ 10622 X(3, (R, R, D), DOUBLE), \ 10623 X(2, (S, R), SINGLE), \ 10624 X(2, (R, S), SINGLE), \ 10625 X(2, (F, R), SINGLE), \ 10626 X(2, (R, F), SINGLE) 10627 10628#define S2(A,B) NS_##A##B 10629#define S3(A,B,C) NS_##A##B##C 10630#define S4(A,B,C,D) NS_##A##B##C##D 10631 10632#define X(N, L, C) S##N L 10633 10634enum neon_shape 10635{ 10636 NEON_SHAPE_DEF, 10637 NS_NULL 10638}; 10639 10640#undef X 10641#undef S2 10642#undef S3 10643#undef S4 10644 10645enum neon_shape_class 10646{ 10647 SC_SINGLE, 10648 SC_DOUBLE, 10649 SC_QUAD, 10650 SC_MIXED 10651}; 10652 10653#define X(N, L, C) SC_##C 10654 10655static enum neon_shape_class neon_shape_class[] = 10656{ 10657 NEON_SHAPE_DEF 10658}; 10659 10660#undef X 10661 10662enum neon_shape_el 10663{ 10664 SE_F, 10665 SE_D, 10666 SE_Q, 10667 SE_I, 10668 SE_S, 10669 SE_R, 10670 SE_L 10671}; 10672 10673/* Register widths of above. */ 10674static unsigned neon_shape_el_size[] = 10675{ 10676 32, 10677 64, 10678 128, 10679 0, 10680 32, 10681 32, 10682 0 10683}; 10684 10685struct neon_shape_info 10686{ 10687 unsigned els; 10688 enum neon_shape_el el[NEON_MAX_TYPE_ELS]; 10689}; 10690 10691#define S2(A,B) { SE_##A, SE_##B } 10692#define S3(A,B,C) { SE_##A, SE_##B, SE_##C } 10693#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D } 10694 10695#define X(N, L, C) { N, S##N L } 10696 10697static struct neon_shape_info neon_shape_tab[] = 10698{ 10699 NEON_SHAPE_DEF 10700}; 10701 10702#undef X 10703#undef S2 10704#undef S3 10705#undef S4 10706 10707/* Bit masks used in type checking given instructions. 10708 'N_EQK' means the type must be the same as (or based on in some way) the key 10709 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is 10710 set, various other bits can be set as well in order to modify the meaning of 10711 the type constraint. */ 10712 10713enum neon_type_mask 10714{ 10715 N_S8 = 0x000001, 10716 N_S16 = 0x000002, 10717 N_S32 = 0x000004, 10718 N_S64 = 0x000008, 10719 N_U8 = 0x000010, 10720 N_U16 = 0x000020, 10721 N_U32 = 0x000040, 10722 N_U64 = 0x000080, 10723 N_I8 = 0x000100, 10724 N_I16 = 0x000200, 10725 N_I32 = 0x000400, 10726 N_I64 = 0x000800, 10727 N_8 = 0x001000, 10728 N_16 = 0x002000, 10729 N_32 = 0x004000, 10730 N_64 = 0x008000, 10731 N_P8 = 0x010000, 10732 N_P16 = 0x020000, 10733 N_F32 = 0x040000, 10734 N_F64 = 0x080000, 10735 N_KEY = 0x100000, /* key element (main type specifier). */ 10736 N_EQK = 0x200000, /* given operand has the same type & size as the key. */ 10737 N_VFP = 0x400000, /* VFP mode: operand size must match register width. */ 10738 N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */ 10739 N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */ 10740 N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */ 10741 N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */ 10742 N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */ 10743 N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */ 10744 N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */ 10745 N_UTYP = 0, 10746 N_MAX_NONSPECIAL = N_F64 10747}; 10748 10749#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ) 10750 10751#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64) 10752#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32) 10753#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64) 10754#define N_SUF_32 (N_SU_32 | N_F32) 10755#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64) 10756#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32) 10757 10758/* Pass this as the first type argument to neon_check_type to ignore types 10759 altogether. */ 10760#define N_IGNORE_TYPE (N_KEY | N_EQK) 10761 10762/* Select a "shape" for the current instruction (describing register types or 10763 sizes) from a list of alternatives. Return NS_NULL if the current instruction 10764 doesn't fit. For non-polymorphic shapes, checking is usually done as a 10765 function of operand parsing, so this function doesn't need to be called. 10766 Shapes should be listed in order of decreasing length. */ 10767 10768static enum neon_shape 10769neon_select_shape (enum neon_shape shape, ...) 10770{ 10771 va_list ap; 10772 enum neon_shape first_shape = shape; 10773 10774 /* Fix missing optional operands. FIXME: we don't know at this point how 10775 many arguments we should have, so this makes the assumption that we have 10776 > 1. This is true of all current Neon opcodes, I think, but may not be 10777 true in the future. */ 10778 if (!inst.operands[1].present) 10779 inst.operands[1] = inst.operands[0]; 10780 10781 va_start (ap, shape); 10782 10783 for (; shape != NS_NULL; shape = va_arg (ap, int)) 10784 { 10785 unsigned j; 10786 int matches = 1; 10787 10788 for (j = 0; j < neon_shape_tab[shape].els; j++) 10789 { 10790 if (!inst.operands[j].present) 10791 { 10792 matches = 0; 10793 break; 10794 } 10795 10796 switch (neon_shape_tab[shape].el[j]) 10797 { 10798 case SE_F: 10799 if (!(inst.operands[j].isreg 10800 && inst.operands[j].isvec 10801 && inst.operands[j].issingle 10802 && !inst.operands[j].isquad)) 10803 matches = 0; 10804 break; 10805 10806 case SE_D: 10807 if (!(inst.operands[j].isreg 10808 && inst.operands[j].isvec 10809 && !inst.operands[j].isquad 10810 && !inst.operands[j].issingle)) 10811 matches = 0; 10812 break; 10813 10814 case SE_R: 10815 if (!(inst.operands[j].isreg 10816 && !inst.operands[j].isvec)) 10817 matches = 0; 10818 break; 10819 10820 case SE_Q: 10821 if (!(inst.operands[j].isreg 10822 && inst.operands[j].isvec 10823 && inst.operands[j].isquad 10824 && !inst.operands[j].issingle)) 10825 matches = 0; 10826 break; 10827 10828 case SE_I: 10829 if (!(!inst.operands[j].isreg 10830 && !inst.operands[j].isscalar)) 10831 matches = 0; 10832 break; 10833 10834 case SE_S: 10835 if (!(!inst.operands[j].isreg 10836 && inst.operands[j].isscalar)) 10837 matches = 0; 10838 break; 10839 10840 case SE_L: 10841 break; 10842 } 10843 } 10844 if (matches) 10845 break; 10846 } 10847 10848 va_end (ap); 10849 10850 if (shape == NS_NULL && first_shape != NS_NULL) 10851 first_error (_("invalid instruction shape")); 10852 10853 return shape; 10854} 10855 10856/* True if SHAPE is predominantly a quadword operation (most of the time, this 10857 means the Q bit should be set). */ 10858 10859static int 10860neon_quad (enum neon_shape shape) 10861{ 10862 return neon_shape_class[shape] == SC_QUAD; 10863} 10864 10865static void 10866neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type, 10867 unsigned *g_size) 10868{ 10869 /* Allow modification to be made to types which are constrained to be 10870 based on the key element, based on bits set alongside N_EQK. */ 10871 if ((typebits & N_EQK) != 0) 10872 { 10873 if ((typebits & N_HLF) != 0) 10874 *g_size /= 2; 10875 else if ((typebits & N_DBL) != 0) 10876 *g_size *= 2; 10877 if ((typebits & N_SGN) != 0) 10878 *g_type = NT_signed; 10879 else if ((typebits & N_UNS) != 0) 10880 *g_type = NT_unsigned; 10881 else if ((typebits & N_INT) != 0) 10882 *g_type = NT_integer; 10883 else if ((typebits & N_FLT) != 0) 10884 *g_type = NT_float; 10885 else if ((typebits & N_SIZ) != 0) 10886 *g_type = NT_untyped; 10887 } 10888} 10889 10890/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key" 10891 operand type, i.e. the single type specified in a Neon instruction when it 10892 is the only one given. */ 10893 10894static struct neon_type_el 10895neon_type_promote (struct neon_type_el *key, unsigned thisarg) 10896{ 10897 struct neon_type_el dest = *key; 10898 10899 assert ((thisarg & N_EQK) != 0); 10900 10901 neon_modify_type_size (thisarg, &dest.type, &dest.size); 10902 10903 return dest; 10904} 10905 10906/* Convert Neon type and size into compact bitmask representation. */ 10907 10908static enum neon_type_mask 10909type_chk_of_el_type (enum neon_el_type type, unsigned size) 10910{ 10911 switch (type) 10912 { 10913 case NT_untyped: 10914 switch (size) 10915 { 10916 case 8: return N_8; 10917 case 16: return N_16; 10918 case 32: return N_32; 10919 case 64: return N_64; 10920 default: ; 10921 } 10922 break; 10923 10924 case NT_integer: 10925 switch (size) 10926 { 10927 case 8: return N_I8; 10928 case 16: return N_I16; 10929 case 32: return N_I32; 10930 case 64: return N_I64; 10931 default: ; 10932 } 10933 break; 10934 10935 case NT_float: 10936 switch (size) 10937 { 10938 case 32: return N_F32; 10939 case 64: return N_F64; 10940 default: ; 10941 } 10942 break; 10943 10944 case NT_poly: 10945 switch (size) 10946 { 10947 case 8: return N_P8; 10948 case 16: return N_P16; 10949 default: ; 10950 } 10951 break; 10952 10953 case NT_signed: 10954 switch (size) 10955 { 10956 case 8: return N_S8; 10957 case 16: return N_S16; 10958 case 32: return N_S32; 10959 case 64: return N_S64; 10960 default: ; 10961 } 10962 break; 10963 10964 case NT_unsigned: 10965 switch (size) 10966 { 10967 case 8: return N_U8; 10968 case 16: return N_U16; 10969 case 32: return N_U32; 10970 case 64: return N_U64; 10971 default: ; 10972 } 10973 break; 10974 10975 default: ; 10976 } 10977 10978 return N_UTYP; 10979} 10980 10981/* Convert compact Neon bitmask type representation to a type and size. Only 10982 handles the case where a single bit is set in the mask. */ 10983 10984static int 10985el_type_of_type_chk (enum neon_el_type *type, unsigned *size, 10986 enum neon_type_mask mask) 10987{ 10988 if ((mask & N_EQK) != 0) 10989 return FAIL; 10990 10991 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0) 10992 *size = 8; 10993 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0) 10994 *size = 16; 10995 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0) 10996 *size = 32; 10997 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0) 10998 *size = 64; 10999 else 11000 return FAIL; 11001 11002 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0) 11003 *type = NT_signed; 11004 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0) 11005 *type = NT_unsigned; 11006 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0) 11007 *type = NT_integer; 11008 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0) 11009 *type = NT_untyped; 11010 else if ((mask & (N_P8 | N_P16)) != 0) 11011 *type = NT_poly; 11012 else if ((mask & (N_F32 | N_F64)) != 0) 11013 *type = NT_float; 11014 else 11015 return FAIL; 11016 11017 return SUCCESS; 11018} 11019 11020/* Modify a bitmask of allowed types. This is only needed for type 11021 relaxation. */ 11022 11023static unsigned 11024modify_types_allowed (unsigned allowed, unsigned mods) 11025{ 11026 unsigned size; 11027 enum neon_el_type type; 11028 unsigned destmask; 11029 int i; 11030 11031 destmask = 0; 11032 11033 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1) 11034 { 11035 if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS) 11036 { 11037 neon_modify_type_size (mods, &type, &size); 11038 destmask |= type_chk_of_el_type (type, size); 11039 } 11040 } 11041 11042 return destmask; 11043} 11044 11045/* Check type and return type classification. 11046 The manual states (paraphrase): If one datatype is given, it indicates the 11047 type given in: 11048 - the second operand, if there is one 11049 - the operand, if there is no second operand 11050 - the result, if there are no operands. 11051 This isn't quite good enough though, so we use a concept of a "key" datatype 11052 which is set on a per-instruction basis, which is the one which matters when 11053 only one data type is written. 11054 Note: this function has side-effects (e.g. filling in missing operands). All 11055 Neon instructions should call it before performing bit encoding. */ 11056 11057static struct neon_type_el 11058neon_check_type (unsigned els, enum neon_shape ns, ...) 11059{ 11060 va_list ap; 11061 unsigned i, pass, key_el = 0; 11062 unsigned types[NEON_MAX_TYPE_ELS]; 11063 enum neon_el_type k_type = NT_invtype; 11064 unsigned k_size = -1u; 11065 struct neon_type_el badtype = {NT_invtype, -1}; 11066 unsigned key_allowed = 0; 11067 11068 /* Optional registers in Neon instructions are always (not) in operand 1. 11069 Fill in the missing operand here, if it was omitted. */ 11070 if (els > 1 && !inst.operands[1].present) 11071 inst.operands[1] = inst.operands[0]; 11072 11073 /* Suck up all the varargs. */ 11074 va_start (ap, ns); 11075 for (i = 0; i < els; i++) 11076 { 11077 unsigned thisarg = va_arg (ap, unsigned); 11078 if (thisarg == N_IGNORE_TYPE) 11079 { 11080 va_end (ap); 11081 return badtype; 11082 } 11083 types[i] = thisarg; 11084 if ((thisarg & N_KEY) != 0) 11085 key_el = i; 11086 } 11087 va_end (ap); 11088 11089 if (inst.vectype.elems > 0) 11090 for (i = 0; i < els; i++) 11091 if (inst.operands[i].vectype.type != NT_invtype) 11092 { 11093 first_error (_("types specified in both the mnemonic and operands")); 11094 return badtype; 11095 } 11096 11097 /* Duplicate inst.vectype elements here as necessary. 11098 FIXME: No idea if this is exactly the same as the ARM assembler, 11099 particularly when an insn takes one register and one non-register 11100 operand. */ 11101 if (inst.vectype.elems == 1 && els > 1) 11102 { 11103 unsigned j; 11104 inst.vectype.elems = els; 11105 inst.vectype.el[key_el] = inst.vectype.el[0]; 11106 for (j = 0; j < els; j++) 11107 if (j != key_el) 11108 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11109 types[j]); 11110 } 11111 else if (inst.vectype.elems == 0 && els > 0) 11112 { 11113 unsigned j; 11114 /* No types were given after the mnemonic, so look for types specified 11115 after each operand. We allow some flexibility here; as long as the 11116 "key" operand has a type, we can infer the others. */ 11117 for (j = 0; j < els; j++) 11118 if (inst.operands[j].vectype.type != NT_invtype) 11119 inst.vectype.el[j] = inst.operands[j].vectype; 11120 11121 if (inst.operands[key_el].vectype.type != NT_invtype) 11122 { 11123 for (j = 0; j < els; j++) 11124 if (inst.operands[j].vectype.type == NT_invtype) 11125 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el], 11126 types[j]); 11127 } 11128 else 11129 { 11130 first_error (_("operand types can't be inferred")); 11131 return badtype; 11132 } 11133 } 11134 else if (inst.vectype.elems != els) 11135 { 11136 first_error (_("type specifier has the wrong number of parts")); 11137 return badtype; 11138 } 11139 11140 for (pass = 0; pass < 2; pass++) 11141 { 11142 for (i = 0; i < els; i++) 11143 { 11144 unsigned thisarg = types[i]; 11145 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0) 11146 ? modify_types_allowed (key_allowed, thisarg) : thisarg; 11147 enum neon_el_type g_type = inst.vectype.el[i].type; 11148 unsigned g_size = inst.vectype.el[i].size; 11149 11150 /* Decay more-specific signed & unsigned types to sign-insensitive 11151 integer types if sign-specific variants are unavailable. */ 11152 if ((g_type == NT_signed || g_type == NT_unsigned) 11153 && (types_allowed & N_SU_ALL) == 0) 11154 g_type = NT_integer; 11155 11156 /* If only untyped args are allowed, decay any more specific types to 11157 them. Some instructions only care about signs for some element 11158 sizes, so handle that properly. */ 11159 if ((g_size == 8 && (types_allowed & N_8) != 0) 11160 || (g_size == 16 && (types_allowed & N_16) != 0) 11161 || (g_size == 32 && (types_allowed & N_32) != 0) 11162 || (g_size == 64 && (types_allowed & N_64) != 0)) 11163 g_type = NT_untyped; 11164 11165 if (pass == 0) 11166 { 11167 if ((thisarg & N_KEY) != 0) 11168 { 11169 k_type = g_type; 11170 k_size = g_size; 11171 key_allowed = thisarg & ~N_KEY; 11172 } 11173 } 11174 else 11175 { 11176 if ((thisarg & N_VFP) != 0) 11177 { 11178 enum neon_shape_el regshape = neon_shape_tab[ns].el[i]; 11179 unsigned regwidth = neon_shape_el_size[regshape], match; 11180 11181 /* In VFP mode, operands must match register widths. If we 11182 have a key operand, use its width, else use the width of 11183 the current operand. */ 11184 if (k_size != -1u) 11185 match = k_size; 11186 else 11187 match = g_size; 11188 11189 if (regwidth != match) 11190 { 11191 first_error (_("operand size must match register width")); 11192 return badtype; 11193 } 11194 } 11195 11196 if ((thisarg & N_EQK) == 0) 11197 { 11198 unsigned given_type = type_chk_of_el_type (g_type, g_size); 11199 11200 if ((given_type & types_allowed) == 0) 11201 { 11202 first_error (_("bad type in Neon instruction")); 11203 return badtype; 11204 } 11205 } 11206 else 11207 { 11208 enum neon_el_type mod_k_type = k_type; 11209 unsigned mod_k_size = k_size; 11210 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size); 11211 if (g_type != mod_k_type || g_size != mod_k_size) 11212 { 11213 first_error (_("inconsistent types in Neon instruction")); 11214 return badtype; 11215 } 11216 } 11217 } 11218 } 11219 } 11220 11221 return inst.vectype.el[key_el]; 11222} 11223 11224/* Neon-style VFP instruction forwarding. */ 11225 11226/* Thumb VFP instructions have 0xE in the condition field. */ 11227 11228static void 11229do_vfp_cond_or_thumb (void) 11230{ 11231 if (thumb_mode) 11232 inst.instruction |= 0xe0000000; 11233 else 11234 inst.instruction |= inst.cond << 28; 11235} 11236 11237/* Look up and encode a simple mnemonic, for use as a helper function for the 11238 Neon-style VFP syntax. This avoids duplication of bits of the insns table, 11239 etc. It is assumed that operand parsing has already been done, and that the 11240 operands are in the form expected by the given opcode (this isn't necessarily 11241 the same as the form in which they were parsed, hence some massaging must 11242 take place before this function is called). 11243 Checks current arch version against that in the looked-up opcode. */ 11244 11245static void 11246do_vfp_nsyn_opcode (const char *opname) 11247{ 11248 const struct asm_opcode *opcode; 11249 11250 opcode = hash_find (arm_ops_hsh, opname); 11251 11252 if (!opcode) 11253 abort (); 11254 11255 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, 11256 thumb_mode ? *opcode->tvariant : *opcode->avariant), 11257 _(BAD_FPU)); 11258 11259 if (thumb_mode) 11260 { 11261 inst.instruction = opcode->tvalue; 11262 opcode->tencode (); 11263 } 11264 else 11265 { 11266 inst.instruction = (inst.cond << 28) | opcode->avalue; 11267 opcode->aencode (); 11268 } 11269} 11270 11271static void 11272do_vfp_nsyn_add_sub (enum neon_shape rs) 11273{ 11274 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd; 11275 11276 if (rs == NS_FFF) 11277 { 11278 if (is_add) 11279 do_vfp_nsyn_opcode ("fadds"); 11280 else 11281 do_vfp_nsyn_opcode ("fsubs"); 11282 } 11283 else 11284 { 11285 if (is_add) 11286 do_vfp_nsyn_opcode ("faddd"); 11287 else 11288 do_vfp_nsyn_opcode ("fsubd"); 11289 } 11290} 11291 11292/* Check operand types to see if this is a VFP instruction, and if so call 11293 PFN (). */ 11294 11295static int 11296try_vfp_nsyn (int args, void (*pfn) (enum neon_shape)) 11297{ 11298 enum neon_shape rs; 11299 struct neon_type_el et; 11300 11301 switch (args) 11302 { 11303 case 2: 11304 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11305 et = neon_check_type (2, rs, 11306 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11307 break; 11308 11309 case 3: 11310 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11311 et = neon_check_type (3, rs, 11312 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11313 break; 11314 11315 default: 11316 abort (); 11317 } 11318 11319 if (et.type != NT_invtype) 11320 { 11321 pfn (rs); 11322 return SUCCESS; 11323 } 11324 else 11325 inst.error = NULL; 11326 11327 return FAIL; 11328} 11329 11330static void 11331do_vfp_nsyn_mla_mls (enum neon_shape rs) 11332{ 11333 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla; 11334 11335 if (rs == NS_FFF) 11336 { 11337 if (is_mla) 11338 do_vfp_nsyn_opcode ("fmacs"); 11339 else 11340 do_vfp_nsyn_opcode ("fmscs"); 11341 } 11342 else 11343 { 11344 if (is_mla) 11345 do_vfp_nsyn_opcode ("fmacd"); 11346 else 11347 do_vfp_nsyn_opcode ("fmscd"); 11348 } 11349} 11350 11351static void 11352do_vfp_nsyn_mul (enum neon_shape rs) 11353{ 11354 if (rs == NS_FFF) 11355 do_vfp_nsyn_opcode ("fmuls"); 11356 else 11357 do_vfp_nsyn_opcode ("fmuld"); 11358} 11359 11360static void 11361do_vfp_nsyn_abs_neg (enum neon_shape rs) 11362{ 11363 int is_neg = (inst.instruction & 0x80) != 0; 11364 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY); 11365 11366 if (rs == NS_FF) 11367 { 11368 if (is_neg) 11369 do_vfp_nsyn_opcode ("fnegs"); 11370 else 11371 do_vfp_nsyn_opcode ("fabss"); 11372 } 11373 else 11374 { 11375 if (is_neg) 11376 do_vfp_nsyn_opcode ("fnegd"); 11377 else 11378 do_vfp_nsyn_opcode ("fabsd"); 11379 } 11380} 11381 11382/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision 11383 insns belong to Neon, and are handled elsewhere. */ 11384 11385static void 11386do_vfp_nsyn_ldm_stm (int is_dbmode) 11387{ 11388 int is_ldm = (inst.instruction & (1 << 20)) != 0; 11389 if (is_ldm) 11390 { 11391 if (is_dbmode) 11392 do_vfp_nsyn_opcode ("fldmdbs"); 11393 else 11394 do_vfp_nsyn_opcode ("fldmias"); 11395 } 11396 else 11397 { 11398 if (is_dbmode) 11399 do_vfp_nsyn_opcode ("fstmdbs"); 11400 else 11401 do_vfp_nsyn_opcode ("fstmias"); 11402 } 11403} 11404 11405static void 11406do_vfp_nsyn_sqrt (void) 11407{ 11408 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11409 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11410 11411 if (rs == NS_FF) 11412 do_vfp_nsyn_opcode ("fsqrts"); 11413 else 11414 do_vfp_nsyn_opcode ("fsqrtd"); 11415} 11416 11417static void 11418do_vfp_nsyn_div (void) 11419{ 11420 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11421 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11422 N_F32 | N_F64 | N_KEY | N_VFP); 11423 11424 if (rs == NS_FFF) 11425 do_vfp_nsyn_opcode ("fdivs"); 11426 else 11427 do_vfp_nsyn_opcode ("fdivd"); 11428} 11429 11430static void 11431do_vfp_nsyn_nmul (void) 11432{ 11433 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL); 11434 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP, 11435 N_F32 | N_F64 | N_KEY | N_VFP); 11436 11437 if (rs == NS_FFF) 11438 { 11439 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11440 do_vfp_sp_dyadic (); 11441 } 11442 else 11443 { 11444 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11445 do_vfp_dp_rd_rn_rm (); 11446 } 11447 do_vfp_cond_or_thumb (); 11448} 11449 11450static void 11451do_vfp_nsyn_cmp (void) 11452{ 11453 if (inst.operands[1].isreg) 11454 { 11455 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL); 11456 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP); 11457 11458 if (rs == NS_FF) 11459 { 11460 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11461 do_vfp_sp_monadic (); 11462 } 11463 else 11464 { 11465 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11466 do_vfp_dp_rd_rm (); 11467 } 11468 } 11469 else 11470 { 11471 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL); 11472 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK); 11473 11474 switch (inst.instruction & 0x0fffffff) 11475 { 11476 case N_MNEM_vcmp: 11477 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp; 11478 break; 11479 case N_MNEM_vcmpe: 11480 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe; 11481 break; 11482 default: 11483 abort (); 11484 } 11485 11486 if (rs == NS_FI) 11487 { 11488 inst.instruction = NEON_ENC_SINGLE (inst.instruction); 11489 do_vfp_sp_compare_z (); 11490 } 11491 else 11492 { 11493 inst.instruction = NEON_ENC_DOUBLE (inst.instruction); 11494 do_vfp_dp_rd (); 11495 } 11496 } 11497 do_vfp_cond_or_thumb (); 11498} 11499 11500static void 11501nsyn_insert_sp (void) 11502{ 11503 inst.operands[1] = inst.operands[0]; 11504 memset (&inst.operands[0], '\0', sizeof (inst.operands[0])); 11505 inst.operands[0].reg = 13; 11506 inst.operands[0].isreg = 1; 11507 inst.operands[0].writeback = 1; 11508 inst.operands[0].present = 1; 11509} 11510 11511static void 11512do_vfp_nsyn_push (void) 11513{ 11514 nsyn_insert_sp (); 11515 if (inst.operands[1].issingle) 11516 do_vfp_nsyn_opcode ("fstmdbs"); 11517 else 11518 do_vfp_nsyn_opcode ("fstmdbd"); 11519} 11520 11521static void 11522do_vfp_nsyn_pop (void) 11523{ 11524 nsyn_insert_sp (); 11525 if (inst.operands[1].issingle) 11526 do_vfp_nsyn_opcode ("fldmias"); 11527 else 11528 do_vfp_nsyn_opcode ("fldmiad"); 11529} 11530 11531/* Fix up Neon data-processing instructions, ORing in the correct bits for 11532 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */ 11533 11534static unsigned 11535neon_dp_fixup (unsigned i) 11536{ 11537 if (thumb_mode) 11538 { 11539 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */ 11540 if (i & (1 << 24)) 11541 i |= 1 << 28; 11542 11543 i &= ~(1 << 24); 11544 11545 i |= 0xef000000; 11546 } 11547 else 11548 i |= 0xf2000000; 11549 11550 return i; 11551} 11552 11553/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3 11554 (0, 1, 2, 3). */ 11555 11556static unsigned 11557neon_logbits (unsigned x) 11558{ 11559 return ffs (x) - 4; 11560} 11561 11562#define LOW4(R) ((R) & 0xf) 11563#define HI1(R) (((R) >> 4) & 1) 11564 11565/* Encode insns with bit pattern: 11566 11567 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| 11568 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm | 11569 11570 SIZE is passed in bits. -1 means size field isn't changed, in case it has a 11571 different meaning for some instruction. */ 11572 11573static void 11574neon_three_same (int isquad, int ubit, int size) 11575{ 11576 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11577 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11578 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 11579 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 11580 inst.instruction |= LOW4 (inst.operands[2].reg); 11581 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 11582 inst.instruction |= (isquad != 0) << 6; 11583 inst.instruction |= (ubit != 0) << 24; 11584 if (size != -1) 11585 inst.instruction |= neon_logbits (size) << 20; 11586 11587 inst.instruction = neon_dp_fixup (inst.instruction); 11588} 11589 11590/* Encode instructions of the form: 11591 11592 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0| 11593 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm | 11594 11595 Don't write size if SIZE == -1. */ 11596 11597static void 11598neon_two_same (int qbit, int ubit, int size) 11599{ 11600 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11601 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11602 inst.instruction |= LOW4 (inst.operands[1].reg); 11603 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11604 inst.instruction |= (qbit != 0) << 6; 11605 inst.instruction |= (ubit != 0) << 24; 11606 11607 if (size != -1) 11608 inst.instruction |= neon_logbits (size) << 18; 11609 11610 inst.instruction = neon_dp_fixup (inst.instruction); 11611} 11612 11613/* Neon instruction encoders, in approximate order of appearance. */ 11614 11615static void 11616do_neon_dyadic_i_su (void) 11617{ 11618 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11619 struct neon_type_el et = neon_check_type (3, rs, 11620 N_EQK, N_EQK, N_SU_32 | N_KEY); 11621 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11622} 11623 11624static void 11625do_neon_dyadic_i64_su (void) 11626{ 11627 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11628 struct neon_type_el et = neon_check_type (3, rs, 11629 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11630 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11631} 11632 11633static void 11634neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et, 11635 unsigned immbits) 11636{ 11637 unsigned size = et.size >> 3; 11638 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 11639 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 11640 inst.instruction |= LOW4 (inst.operands[1].reg); 11641 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 11642 inst.instruction |= (isquad != 0) << 6; 11643 inst.instruction |= immbits << 16; 11644 inst.instruction |= (size >> 3) << 7; 11645 inst.instruction |= (size & 0x7) << 19; 11646 if (write_ubit) 11647 inst.instruction |= (uval != 0) << 24; 11648 11649 inst.instruction = neon_dp_fixup (inst.instruction); 11650} 11651 11652static void 11653do_neon_shl_imm (void) 11654{ 11655 if (!inst.operands[2].isreg) 11656 { 11657 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11658 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL); 11659 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11660 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm); 11661 } 11662 else 11663 { 11664 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11665 struct neon_type_el et = neon_check_type (3, rs, 11666 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11667 unsigned int tmp; 11668 11669 /* VSHL/VQSHL 3-register variants have syntax such as: 11670 vshl.xx Dd, Dm, Dn 11671 whereas other 3-register operations encoded by neon_three_same have 11672 syntax like: 11673 vadd.xx Dd, Dn, Dm 11674 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg 11675 here. */ 11676 tmp = inst.operands[2].reg; 11677 inst.operands[2].reg = inst.operands[1].reg; 11678 inst.operands[1].reg = tmp; 11679 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11680 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11681 } 11682} 11683 11684static void 11685do_neon_qshl_imm (void) 11686{ 11687 if (!inst.operands[2].isreg) 11688 { 11689 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 11690 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 11691 11692 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11693 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 11694 inst.operands[2].imm); 11695 } 11696 else 11697 { 11698 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11699 struct neon_type_el et = neon_check_type (3, rs, 11700 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN); 11701 unsigned int tmp; 11702 11703 /* See note in do_neon_shl_imm. */ 11704 tmp = inst.operands[2].reg; 11705 inst.operands[2].reg = inst.operands[1].reg; 11706 inst.operands[1].reg = tmp; 11707 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11708 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11709 } 11710} 11711 11712static void 11713do_neon_rshl (void) 11714{ 11715 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11716 struct neon_type_el et = neon_check_type (3, rs, 11717 N_EQK, N_EQK, N_SU_ALL | N_KEY); 11718 unsigned int tmp; 11719 11720 tmp = inst.operands[2].reg; 11721 inst.operands[2].reg = inst.operands[1].reg; 11722 inst.operands[1].reg = tmp; 11723 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size); 11724} 11725 11726static int 11727neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size) 11728{ 11729 /* Handle .I8 pseudo-instructions. */ 11730 if (size == 8) 11731 { 11732 /* Unfortunately, this will make everything apart from zero out-of-range. 11733 FIXME is this the intended semantics? There doesn't seem much point in 11734 accepting .I8 if so. */ 11735 immediate |= immediate << 8; 11736 size = 16; 11737 } 11738 11739 if (size >= 32) 11740 { 11741 if (immediate == (immediate & 0x000000ff)) 11742 { 11743 *immbits = immediate; 11744 return 0x1; 11745 } 11746 else if (immediate == (immediate & 0x0000ff00)) 11747 { 11748 *immbits = immediate >> 8; 11749 return 0x3; 11750 } 11751 else if (immediate == (immediate & 0x00ff0000)) 11752 { 11753 *immbits = immediate >> 16; 11754 return 0x5; 11755 } 11756 else if (immediate == (immediate & 0xff000000)) 11757 { 11758 *immbits = immediate >> 24; 11759 return 0x7; 11760 } 11761 if ((immediate & 0xffff) != (immediate >> 16)) 11762 goto bad_immediate; 11763 immediate &= 0xffff; 11764 } 11765 11766 if (immediate == (immediate & 0x000000ff)) 11767 { 11768 *immbits = immediate; 11769 return 0x9; 11770 } 11771 else if (immediate == (immediate & 0x0000ff00)) 11772 { 11773 *immbits = immediate >> 8; 11774 return 0xb; 11775 } 11776 11777 bad_immediate: 11778 first_error (_("immediate value out of range")); 11779 return FAIL; 11780} 11781 11782/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits 11783 A, B, C, D. */ 11784 11785static int 11786neon_bits_same_in_bytes (unsigned imm) 11787{ 11788 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff) 11789 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00) 11790 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000) 11791 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000); 11792} 11793 11794/* For immediate of above form, return 0bABCD. */ 11795 11796static unsigned 11797neon_squash_bits (unsigned imm) 11798{ 11799 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14) 11800 | ((imm & 0x01000000) >> 21); 11801} 11802 11803/* Compress quarter-float representation to 0b...000 abcdefgh. */ 11804 11805static unsigned 11806neon_qfloat_bits (unsigned imm) 11807{ 11808 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80); 11809} 11810 11811/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into 11812 the instruction. *OP is passed as the initial value of the op field, and 11813 may be set to a different value depending on the constant (i.e. 11814 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not 11815 MVN). If the immediate looks like a repeated parttern then also 11816 try smaller element sizes. */ 11817 11818static int 11819neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p, 11820 unsigned *immbits, int *op, int size, 11821 enum neon_el_type type) 11822{ 11823 /* Only permit float immediates (including 0.0/-0.0) if the operand type is 11824 float. */ 11825 if (type == NT_float && !float_p) 11826 return FAIL; 11827 11828 if (type == NT_float && is_quarter_float (immlo) && immhi == 0) 11829 { 11830 if (size != 32 || *op == 1) 11831 return FAIL; 11832 *immbits = neon_qfloat_bits (immlo); 11833 return 0xf; 11834 } 11835 11836 if (size == 64) 11837 { 11838 if (neon_bits_same_in_bytes (immhi) 11839 && neon_bits_same_in_bytes (immlo)) 11840 { 11841 if (*op == 1) 11842 return FAIL; 11843 *immbits = (neon_squash_bits (immhi) << 4) 11844 | neon_squash_bits (immlo); 11845 *op = 1; 11846 return 0xe; 11847 } 11848 11849 if (immhi != immlo) 11850 return FAIL; 11851 } 11852 11853 if (size >= 32) 11854 { 11855 if (immlo == (immlo & 0x000000ff)) 11856 { 11857 *immbits = immlo; 11858 return 0x0; 11859 } 11860 else if (immlo == (immlo & 0x0000ff00)) 11861 { 11862 *immbits = immlo >> 8; 11863 return 0x2; 11864 } 11865 else if (immlo == (immlo & 0x00ff0000)) 11866 { 11867 *immbits = immlo >> 16; 11868 return 0x4; 11869 } 11870 else if (immlo == (immlo & 0xff000000)) 11871 { 11872 *immbits = immlo >> 24; 11873 return 0x6; 11874 } 11875 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff)) 11876 { 11877 *immbits = (immlo >> 8) & 0xff; 11878 return 0xc; 11879 } 11880 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff)) 11881 { 11882 *immbits = (immlo >> 16) & 0xff; 11883 return 0xd; 11884 } 11885 11886 if ((immlo & 0xffff) != (immlo >> 16)) 11887 return FAIL; 11888 immlo &= 0xffff; 11889 } 11890 11891 if (size >= 16) 11892 { 11893 if (immlo == (immlo & 0x000000ff)) 11894 { 11895 *immbits = immlo; 11896 return 0x8; 11897 } 11898 else if (immlo == (immlo & 0x0000ff00)) 11899 { 11900 *immbits = immlo >> 8; 11901 return 0xa; 11902 } 11903 11904 if ((immlo & 0xff) != (immlo >> 8)) 11905 return FAIL; 11906 immlo &= 0xff; 11907 } 11908 11909 if (immlo == (immlo & 0x000000ff)) 11910 { 11911 /* Don't allow MVN with 8-bit immediate. */ 11912 if (*op == 1) 11913 return FAIL; 11914 *immbits = immlo; 11915 return 0xe; 11916 } 11917 11918 return FAIL; 11919} 11920 11921/* Write immediate bits [7:0] to the following locations: 11922 11923 |28/24|23 19|18 16|15 4|3 0| 11924 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h| 11925 11926 This function is used by VMOV/VMVN/VORR/VBIC. */ 11927 11928static void 11929neon_write_immbits (unsigned immbits) 11930{ 11931 inst.instruction |= immbits & 0xf; 11932 inst.instruction |= ((immbits >> 4) & 0x7) << 16; 11933 inst.instruction |= ((immbits >> 7) & 0x1) << 24; 11934} 11935 11936/* Invert low-order SIZE bits of XHI:XLO. */ 11937 11938static void 11939neon_invert_size (unsigned *xlo, unsigned *xhi, int size) 11940{ 11941 unsigned immlo = xlo ? *xlo : 0; 11942 unsigned immhi = xhi ? *xhi : 0; 11943 11944 switch (size) 11945 { 11946 case 8: 11947 immlo = (~immlo) & 0xff; 11948 break; 11949 11950 case 16: 11951 immlo = (~immlo) & 0xffff; 11952 break; 11953 11954 case 64: 11955 immhi = (~immhi) & 0xffffffff; 11956 /* fall through. */ 11957 11958 case 32: 11959 immlo = (~immlo) & 0xffffffff; 11960 break; 11961 11962 default: 11963 abort (); 11964 } 11965 11966 if (xlo) 11967 *xlo = immlo; 11968 11969 if (xhi) 11970 *xhi = immhi; 11971} 11972 11973static void 11974do_neon_logic (void) 11975{ 11976 if (inst.operands[2].present && inst.operands[2].isreg) 11977 { 11978 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 11979 neon_check_type (3, rs, N_IGNORE_TYPE); 11980 /* U bit and size field were set as part of the bitmask. */ 11981 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 11982 neon_three_same (neon_quad (rs), 0, -1); 11983 } 11984 else 11985 { 11986 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 11987 struct neon_type_el et = neon_check_type (2, rs, 11988 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 11989 enum neon_opc opcode = inst.instruction & 0x0fffffff; 11990 unsigned immbits; 11991 int cmode; 11992 11993 if (et.type == NT_invtype) 11994 return; 11995 11996 inst.instruction = NEON_ENC_IMMED (inst.instruction); 11997 11998 immbits = inst.operands[1].imm; 11999 if (et.size == 64) 12000 { 12001 /* .i64 is a pseudo-op, so the immediate must be a repeating 12002 pattern. */ 12003 if (immbits != (inst.operands[1].regisimm ? 12004 inst.operands[1].reg : 0)) 12005 { 12006 /* Set immbits to an invalid constant. */ 12007 immbits = 0xdeadbeef; 12008 } 12009 } 12010 12011 switch (opcode) 12012 { 12013 case N_MNEM_vbic: 12014 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 12015 break; 12016 12017 case N_MNEM_vorr: 12018 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 12019 break; 12020 12021 case N_MNEM_vand: 12022 /* Pseudo-instruction for VBIC. */ 12023 neon_invert_size (&immbits, 0, et.size); 12024 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 12025 break; 12026 12027 case N_MNEM_vorn: 12028 /* Pseudo-instruction for VORR. */ 12029 neon_invert_size (&immbits, 0, et.size); 12030 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size); 12031 break; 12032 12033 default: 12034 abort (); 12035 } 12036 12037 if (cmode == FAIL) 12038 return; 12039 12040 inst.instruction |= neon_quad (rs) << 6; 12041 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12042 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12043 inst.instruction |= cmode << 8; 12044 neon_write_immbits (immbits); 12045 12046 inst.instruction = neon_dp_fixup (inst.instruction); 12047 } 12048} 12049 12050static void 12051do_neon_bitfield (void) 12052{ 12053 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12054 neon_check_type (3, rs, N_IGNORE_TYPE); 12055 neon_three_same (neon_quad (rs), 0, -1); 12056} 12057 12058static void 12059neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types, 12060 unsigned destbits) 12061{ 12062 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12063 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK, 12064 types | N_KEY); 12065 if (et.type == NT_float) 12066 { 12067 inst.instruction = NEON_ENC_FLOAT (inst.instruction); 12068 neon_three_same (neon_quad (rs), 0, -1); 12069 } 12070 else 12071 { 12072 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12073 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size); 12074 } 12075} 12076 12077static void 12078do_neon_dyadic_if_su (void) 12079{ 12080 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 12081} 12082 12083static void 12084do_neon_dyadic_if_su_d (void) 12085{ 12086 /* This version only allow D registers, but that constraint is enforced during 12087 operand parsing so we don't need to do anything extra here. */ 12088 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0); 12089} 12090 12091static void 12092do_neon_dyadic_if_i_d (void) 12093{ 12094 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12095 affected if we specify unsigned args. */ 12096 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12097} 12098 12099enum vfp_or_neon_is_neon_bits 12100{ 12101 NEON_CHECK_CC = 1, 12102 NEON_CHECK_ARCH = 2 12103}; 12104 12105/* Call this function if an instruction which may have belonged to the VFP or 12106 Neon instruction sets, but turned out to be a Neon instruction (due to the 12107 operand types involved, etc.). We have to check and/or fix-up a couple of 12108 things: 12109 12110 - Make sure the user hasn't attempted to make a Neon instruction 12111 conditional. 12112 - Alter the value in the condition code field if necessary. 12113 - Make sure that the arch supports Neon instructions. 12114 12115 Which of these operations take place depends on bits from enum 12116 vfp_or_neon_is_neon_bits. 12117 12118 WARNING: This function has side effects! If NEON_CHECK_CC is used and the 12119 current instruction's condition is COND_ALWAYS, the condition field is 12120 changed to inst.uncond_value. This is necessary because instructions shared 12121 between VFP and Neon may be conditional for the VFP variants only, and the 12122 unconditional Neon version must have, e.g., 0xF in the condition field. */ 12123 12124static int 12125vfp_or_neon_is_neon (unsigned check) 12126{ 12127 /* Conditions are always legal in Thumb mode (IT blocks). */ 12128 if (!thumb_mode && (check & NEON_CHECK_CC)) 12129 { 12130 if (inst.cond != COND_ALWAYS) 12131 { 12132 first_error (_(BAD_COND)); 12133 return FAIL; 12134 } 12135 if (inst.uncond_value != -1) 12136 inst.instruction |= inst.uncond_value << 28; 12137 } 12138 12139 if ((check & NEON_CHECK_ARCH) 12140 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)) 12141 { 12142 first_error (_(BAD_FPU)); 12143 return FAIL; 12144 } 12145 12146 return SUCCESS; 12147} 12148 12149static void 12150do_neon_addsub_if_i (void) 12151{ 12152 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS) 12153 return; 12154 12155 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12156 return; 12157 12158 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12159 affected if we specify unsigned args. */ 12160 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0); 12161} 12162 12163/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the 12164 result to be: 12165 V<op> A,B (A is operand 0, B is operand 2) 12166 to mean: 12167 V<op> A,B,A 12168 not: 12169 V<op> A,B,B 12170 so handle that case specially. */ 12171 12172static void 12173neon_exchange_operands (void) 12174{ 12175 void *scratch = alloca (sizeof (inst.operands[0])); 12176 if (inst.operands[1].present) 12177 { 12178 /* Swap operands[1] and operands[2]. */ 12179 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0])); 12180 inst.operands[1] = inst.operands[2]; 12181 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0])); 12182 } 12183 else 12184 { 12185 inst.operands[1] = inst.operands[2]; 12186 inst.operands[2] = inst.operands[0]; 12187 } 12188} 12189 12190static void 12191neon_compare (unsigned regtypes, unsigned immtypes, int invert) 12192{ 12193 if (inst.operands[2].isreg) 12194 { 12195 if (invert) 12196 neon_exchange_operands (); 12197 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ); 12198 } 12199 else 12200 { 12201 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12202 struct neon_type_el et = neon_check_type (2, rs, 12203 N_EQK | N_SIZ, immtypes | N_KEY); 12204 12205 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12206 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12207 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12208 inst.instruction |= LOW4 (inst.operands[1].reg); 12209 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12210 inst.instruction |= neon_quad (rs) << 6; 12211 inst.instruction |= (et.type == NT_float) << 10; 12212 inst.instruction |= neon_logbits (et.size) << 18; 12213 12214 inst.instruction = neon_dp_fixup (inst.instruction); 12215 } 12216} 12217 12218static void 12219do_neon_cmp (void) 12220{ 12221 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE); 12222} 12223 12224static void 12225do_neon_cmp_inv (void) 12226{ 12227 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE); 12228} 12229 12230static void 12231do_neon_ceq (void) 12232{ 12233 neon_compare (N_IF_32, N_IF_32, FALSE); 12234} 12235 12236/* For multiply instructions, we have the possibility of 16-bit or 32-bit 12237 scalars, which are encoded in 5 bits, M : Rm. 12238 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in 12239 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the 12240 index in M. */ 12241 12242static unsigned 12243neon_scalar_for_mul (unsigned scalar, unsigned elsize) 12244{ 12245 unsigned regno = NEON_SCALAR_REG (scalar); 12246 unsigned elno = NEON_SCALAR_INDEX (scalar); 12247 12248 switch (elsize) 12249 { 12250 case 16: 12251 if (regno > 7 || elno > 3) 12252 goto bad_scalar; 12253 return regno | (elno << 3); 12254 12255 case 32: 12256 if (regno > 15 || elno > 1) 12257 goto bad_scalar; 12258 return regno | (elno << 4); 12259 12260 default: 12261 bad_scalar: 12262 first_error (_("scalar out of range for multiply instruction")); 12263 } 12264 12265 return 0; 12266} 12267 12268/* Encode multiply / multiply-accumulate scalar instructions. */ 12269 12270static void 12271neon_mul_mac (struct neon_type_el et, int ubit) 12272{ 12273 unsigned scalar; 12274 12275 /* Give a more helpful error message if we have an invalid type. */ 12276 if (et.type == NT_invtype) 12277 return; 12278 12279 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size); 12280 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12281 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12282 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12283 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12284 inst.instruction |= LOW4 (scalar); 12285 inst.instruction |= HI1 (scalar) << 5; 12286 inst.instruction |= (et.type == NT_float) << 8; 12287 inst.instruction |= neon_logbits (et.size) << 20; 12288 inst.instruction |= (ubit != 0) << 24; 12289 12290 inst.instruction = neon_dp_fixup (inst.instruction); 12291} 12292 12293static void 12294do_neon_mac_maybe_scalar (void) 12295{ 12296 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS) 12297 return; 12298 12299 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12300 return; 12301 12302 if (inst.operands[2].isscalar) 12303 { 12304 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12305 struct neon_type_el et = neon_check_type (3, rs, 12306 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY); 12307 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12308 neon_mul_mac (et, neon_quad (rs)); 12309 } 12310 else 12311 { 12312 /* The "untyped" case can't happen. Do this to stop the "U" bit being 12313 affected if we specify unsigned args. */ 12314 neon_dyadic_misc (NT_untyped, N_IF_32, 0); 12315 } 12316} 12317 12318static void 12319do_neon_tst (void) 12320{ 12321 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12322 struct neon_type_el et = neon_check_type (3, rs, 12323 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); 12324 neon_three_same (neon_quad (rs), 0, et.size); 12325} 12326 12327/* VMUL with 3 registers allows the P8 type. The scalar version supports the 12328 same types as the MAC equivalents. The polynomial type for this instruction 12329 is encoded the same as the integer type. */ 12330 12331static void 12332do_neon_mul (void) 12333{ 12334 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS) 12335 return; 12336 12337 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12338 return; 12339 12340 if (inst.operands[2].isscalar) 12341 do_neon_mac_maybe_scalar (); 12342 else 12343 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0); 12344} 12345 12346static void 12347do_neon_qdmulh (void) 12348{ 12349 if (inst.operands[2].isscalar) 12350 { 12351 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); 12352 struct neon_type_el et = neon_check_type (3, rs, 12353 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12354 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12355 neon_mul_mac (et, neon_quad (rs)); 12356 } 12357 else 12358 { 12359 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12360 struct neon_type_el et = neon_check_type (3, rs, 12361 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY); 12362 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12363 /* The U bit (rounding) comes from bit mask. */ 12364 neon_three_same (neon_quad (rs), 0, et.size); 12365 } 12366} 12367 12368static void 12369do_neon_fcmp_absolute (void) 12370{ 12371 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12372 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12373 /* Size field comes from bit mask. */ 12374 neon_three_same (neon_quad (rs), 1, -1); 12375} 12376 12377static void 12378do_neon_fcmp_absolute_inv (void) 12379{ 12380 neon_exchange_operands (); 12381 do_neon_fcmp_absolute (); 12382} 12383 12384static void 12385do_neon_step (void) 12386{ 12387 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); 12388 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY); 12389 neon_three_same (neon_quad (rs), 0, -1); 12390} 12391 12392static void 12393do_neon_abs_neg (void) 12394{ 12395 enum neon_shape rs; 12396 struct neon_type_el et; 12397 12398 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS) 12399 return; 12400 12401 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12402 return; 12403 12404 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12405 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY); 12406 12407 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12408 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12409 inst.instruction |= LOW4 (inst.operands[1].reg); 12410 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12411 inst.instruction |= neon_quad (rs) << 6; 12412 inst.instruction |= (et.type == NT_float) << 10; 12413 inst.instruction |= neon_logbits (et.size) << 18; 12414 12415 inst.instruction = neon_dp_fixup (inst.instruction); 12416} 12417 12418static void 12419do_neon_sli (void) 12420{ 12421 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12422 struct neon_type_el et = neon_check_type (2, rs, 12423 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12424 int imm = inst.operands[2].imm; 12425 constraint (imm < 0 || (unsigned)imm >= et.size, 12426 _("immediate out of range for insert")); 12427 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12428} 12429 12430static void 12431do_neon_sri (void) 12432{ 12433 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12434 struct neon_type_el et = neon_check_type (2, rs, 12435 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 12436 int imm = inst.operands[2].imm; 12437 constraint (imm < 1 || (unsigned)imm > et.size, 12438 _("immediate out of range for insert")); 12439 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm); 12440} 12441 12442static void 12443do_neon_qshlu_imm (void) 12444{ 12445 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 12446 struct neon_type_el et = neon_check_type (2, rs, 12447 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY); 12448 int imm = inst.operands[2].imm; 12449 constraint (imm < 0 || (unsigned)imm >= et.size, 12450 _("immediate out of range for shift")); 12451 /* Only encodes the 'U present' variant of the instruction. 12452 In this case, signed types have OP (bit 8) set to 0. 12453 Unsigned types have OP set to 1. */ 12454 inst.instruction |= (et.type == NT_unsigned) << 8; 12455 /* The rest of the bits are the same as other immediate shifts. */ 12456 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm); 12457} 12458 12459static void 12460do_neon_qmovn (void) 12461{ 12462 struct neon_type_el et = neon_check_type (2, NS_DQ, 12463 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12464 /* Saturating move where operands can be signed or unsigned, and the 12465 destination has the same signedness. */ 12466 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12467 if (et.type == NT_unsigned) 12468 inst.instruction |= 0xc0; 12469 else 12470 inst.instruction |= 0x80; 12471 neon_two_same (0, 1, et.size / 2); 12472} 12473 12474static void 12475do_neon_qmovun (void) 12476{ 12477 struct neon_type_el et = neon_check_type (2, NS_DQ, 12478 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12479 /* Saturating move with unsigned results. Operands must be signed. */ 12480 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12481 neon_two_same (0, 1, et.size / 2); 12482} 12483 12484static void 12485do_neon_rshift_sat_narrow (void) 12486{ 12487 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12488 or unsigned. If operands are unsigned, results must also be unsigned. */ 12489 struct neon_type_el et = neon_check_type (2, NS_DQI, 12490 N_EQK | N_HLF, N_SU_16_64 | N_KEY); 12491 int imm = inst.operands[2].imm; 12492 /* This gets the bounds check, size encoding and immediate bits calculation 12493 right. */ 12494 et.size /= 2; 12495 12496 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for 12497 VQMOVN.I<size> <Dd>, <Qm>. */ 12498 if (imm == 0) 12499 { 12500 inst.operands[2].present = 0; 12501 inst.instruction = N_MNEM_vqmovn; 12502 do_neon_qmovn (); 12503 return; 12504 } 12505 12506 constraint (imm < 1 || (unsigned)imm > et.size, 12507 _("immediate out of range")); 12508 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm); 12509} 12510 12511static void 12512do_neon_rshift_sat_narrow_u (void) 12513{ 12514 /* FIXME: Types for narrowing. If operands are signed, results can be signed 12515 or unsigned. If operands are unsigned, results must also be unsigned. */ 12516 struct neon_type_el et = neon_check_type (2, NS_DQI, 12517 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY); 12518 int imm = inst.operands[2].imm; 12519 /* This gets the bounds check, size encoding and immediate bits calculation 12520 right. */ 12521 et.size /= 2; 12522 12523 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for 12524 VQMOVUN.I<size> <Dd>, <Qm>. */ 12525 if (imm == 0) 12526 { 12527 inst.operands[2].present = 0; 12528 inst.instruction = N_MNEM_vqmovun; 12529 do_neon_qmovun (); 12530 return; 12531 } 12532 12533 constraint (imm < 1 || (unsigned)imm > et.size, 12534 _("immediate out of range")); 12535 /* FIXME: The manual is kind of unclear about what value U should have in 12536 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it 12537 must be 1. */ 12538 neon_imm_shift (TRUE, 1, 0, et, et.size - imm); 12539} 12540 12541static void 12542do_neon_movn (void) 12543{ 12544 struct neon_type_el et = neon_check_type (2, NS_DQ, 12545 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12546 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12547 neon_two_same (0, 1, et.size / 2); 12548} 12549 12550static void 12551do_neon_rshift_narrow (void) 12552{ 12553 struct neon_type_el et = neon_check_type (2, NS_DQI, 12554 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY); 12555 int imm = inst.operands[2].imm; 12556 /* This gets the bounds check, size encoding and immediate bits calculation 12557 right. */ 12558 et.size /= 2; 12559 12560 /* If immediate is zero then we are a pseudo-instruction for 12561 VMOVN.I<size> <Dd>, <Qm> */ 12562 if (imm == 0) 12563 { 12564 inst.operands[2].present = 0; 12565 inst.instruction = N_MNEM_vmovn; 12566 do_neon_movn (); 12567 return; 12568 } 12569 12570 constraint (imm < 1 || (unsigned)imm > et.size, 12571 _("immediate out of range for narrowing operation")); 12572 neon_imm_shift (FALSE, 0, 0, et, et.size - imm); 12573} 12574 12575static void 12576do_neon_shll (void) 12577{ 12578 /* FIXME: Type checking when lengthening. */ 12579 struct neon_type_el et = neon_check_type (2, NS_QDI, 12580 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY); 12581 unsigned imm = inst.operands[2].imm; 12582 12583 if (imm == et.size) 12584 { 12585 /* Maximum shift variant. */ 12586 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12587 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12588 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12589 inst.instruction |= LOW4 (inst.operands[1].reg); 12590 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12591 inst.instruction |= neon_logbits (et.size) << 18; 12592 12593 inst.instruction = neon_dp_fixup (inst.instruction); 12594 } 12595 else 12596 { 12597 /* A more-specific type check for non-max versions. */ 12598 et = neon_check_type (2, NS_QDI, 12599 N_EQK | N_DBL, N_SU_32 | N_KEY); 12600 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12601 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm); 12602 } 12603} 12604 12605/* Check the various types for the VCVT instruction, and return which version 12606 the current instruction is. */ 12607 12608static int 12609neon_cvt_flavour (enum neon_shape rs) 12610{ 12611#define CVT_VAR(C,X,Y) \ 12612 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \ 12613 if (et.type != NT_invtype) \ 12614 { \ 12615 inst.error = NULL; \ 12616 return (C); \ 12617 } 12618 struct neon_type_el et; 12619 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF 12620 || rs == NS_FF) ? N_VFP : 0; 12621 /* The instruction versions which take an immediate take one register 12622 argument, which is extended to the width of the full register. Thus the 12623 "source" and "destination" registers must have the same width. Hack that 12624 here by making the size equal to the key (wider, in this case) operand. */ 12625 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0; 12626 12627 CVT_VAR (0, N_S32, N_F32); 12628 CVT_VAR (1, N_U32, N_F32); 12629 CVT_VAR (2, N_F32, N_S32); 12630 CVT_VAR (3, N_F32, N_U32); 12631 12632 whole_reg = N_VFP; 12633 12634 /* VFP instructions. */ 12635 CVT_VAR (4, N_F32, N_F64); 12636 CVT_VAR (5, N_F64, N_F32); 12637 CVT_VAR (6, N_S32, N_F64 | key); 12638 CVT_VAR (7, N_U32, N_F64 | key); 12639 CVT_VAR (8, N_F64 | key, N_S32); 12640 CVT_VAR (9, N_F64 | key, N_U32); 12641 /* VFP instructions with bitshift. */ 12642 CVT_VAR (10, N_F32 | key, N_S16); 12643 CVT_VAR (11, N_F32 | key, N_U16); 12644 CVT_VAR (12, N_F64 | key, N_S16); 12645 CVT_VAR (13, N_F64 | key, N_U16); 12646 CVT_VAR (14, N_S16, N_F32 | key); 12647 CVT_VAR (15, N_U16, N_F32 | key); 12648 CVT_VAR (16, N_S16, N_F64 | key); 12649 CVT_VAR (17, N_U16, N_F64 | key); 12650 12651 return -1; 12652#undef CVT_VAR 12653} 12654 12655/* Neon-syntax VFP conversions. */ 12656 12657static void 12658do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) 12659{ 12660 const char *opname = 0; 12661 12662 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI) 12663 { 12664 /* Conversions with immediate bitshift. */ 12665 const char *enc[] = 12666 { 12667 "ftosls", 12668 "ftouls", 12669 "fsltos", 12670 "fultos", 12671 NULL, 12672 NULL, 12673 "ftosld", 12674 "ftould", 12675 "fsltod", 12676 "fultod", 12677 "fshtos", 12678 "fuhtos", 12679 "fshtod", 12680 "fuhtod", 12681 "ftoshs", 12682 "ftouhs", 12683 "ftoshd", 12684 "ftouhd" 12685 }; 12686 12687 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12688 { 12689 opname = enc[flavour]; 12690 constraint (inst.operands[0].reg != inst.operands[1].reg, 12691 _("operands 0 and 1 must be the same register")); 12692 inst.operands[1] = inst.operands[2]; 12693 memset (&inst.operands[2], '\0', sizeof (inst.operands[2])); 12694 } 12695 } 12696 else 12697 { 12698 /* Conversions without bitshift. */ 12699 const char *enc[] = 12700 { 12701 "ftosizs", 12702 "ftouizs", 12703 "fsitos", 12704 "fuitos", 12705 "fcvtsd", 12706 "fcvtds", 12707 "ftosizd", 12708 "ftouizd", 12709 "fsitod", 12710 "fuitod" 12711 }; 12712 12713 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc)) 12714 opname = enc[flavour]; 12715 } 12716 12717 if (opname) 12718 do_vfp_nsyn_opcode (opname); 12719} 12720 12721static void 12722do_vfp_nsyn_cvtz (void) 12723{ 12724 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL); 12725 int flavour = neon_cvt_flavour (rs); 12726 const char *enc[] = 12727 { 12728 "ftosizs", 12729 "ftouizs", 12730 NULL, 12731 NULL, 12732 NULL, 12733 NULL, 12734 "ftosizd", 12735 "ftouizd" 12736 }; 12737 12738 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) 12739 do_vfp_nsyn_opcode (enc[flavour]); 12740} 12741 12742static void 12743do_neon_cvt (void) 12744{ 12745 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, 12746 NS_FD, NS_DF, NS_FF, NS_NULL); 12747 int flavour = neon_cvt_flavour (rs); 12748 12749 /* VFP rather than Neon conversions. */ 12750 if (flavour >= 4) 12751 { 12752 do_vfp_nsyn_cvt (rs, flavour); 12753 return; 12754 } 12755 12756 switch (rs) 12757 { 12758 case NS_DDI: 12759 case NS_QQI: 12760 { 12761 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12762 return; 12763 12764 /* Fixed-point conversion with #0 immediate is encoded as an 12765 integer conversion. */ 12766 if (inst.operands[2].present && inst.operands[2].imm == 0) 12767 goto int_encode; 12768 unsigned immbits = 32 - inst.operands[2].imm; 12769 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 }; 12770 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12771 if (flavour != -1) 12772 inst.instruction |= enctab[flavour]; 12773 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12774 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12775 inst.instruction |= LOW4 (inst.operands[1].reg); 12776 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12777 inst.instruction |= neon_quad (rs) << 6; 12778 inst.instruction |= 1 << 21; 12779 inst.instruction |= immbits << 16; 12780 12781 inst.instruction = neon_dp_fixup (inst.instruction); 12782 } 12783 break; 12784 12785 case NS_DD: 12786 case NS_QQ: 12787 int_encode: 12788 { 12789 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 }; 12790 12791 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12792 12793 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 12794 return; 12795 12796 if (flavour != -1) 12797 inst.instruction |= enctab[flavour]; 12798 12799 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12800 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12801 inst.instruction |= LOW4 (inst.operands[1].reg); 12802 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12803 inst.instruction |= neon_quad (rs) << 6; 12804 inst.instruction |= 2 << 18; 12805 12806 inst.instruction = neon_dp_fixup (inst.instruction); 12807 } 12808 break; 12809 12810 default: 12811 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ 12812 do_vfp_nsyn_cvt (rs, flavour); 12813 } 12814} 12815 12816static void 12817neon_move_immediate (void) 12818{ 12819 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); 12820 struct neon_type_el et = neon_check_type (2, rs, 12821 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK); 12822 unsigned immlo, immhi = 0, immbits; 12823 int op, cmode, float_p; 12824 12825 constraint (et.type == NT_invtype, 12826 _("operand size must be specified for immediate VMOV")); 12827 12828 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */ 12829 op = (inst.instruction & (1 << 5)) != 0; 12830 12831 immlo = inst.operands[1].imm; 12832 if (inst.operands[1].regisimm) 12833 immhi = inst.operands[1].reg; 12834 12835 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0, 12836 _("immediate has bits set outside the operand size")); 12837 12838 float_p = inst.operands[1].immisfloat; 12839 12840 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op, 12841 et.size, et.type)) == FAIL) 12842 { 12843 /* Invert relevant bits only. */ 12844 neon_invert_size (&immlo, &immhi, et.size); 12845 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable 12846 with one or the other; those cases are caught by 12847 neon_cmode_for_move_imm. */ 12848 op = !op; 12849 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, 12850 &op, et.size, et.type)) == FAIL) 12851 { 12852 first_error (_("immediate out of range")); 12853 return; 12854 } 12855 } 12856 12857 inst.instruction &= ~(1 << 5); 12858 inst.instruction |= op << 5; 12859 12860 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12861 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12862 inst.instruction |= neon_quad (rs) << 6; 12863 inst.instruction |= cmode << 8; 12864 12865 neon_write_immbits (immbits); 12866} 12867 12868static void 12869do_neon_mvn (void) 12870{ 12871 if (inst.operands[1].isreg) 12872 { 12873 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 12874 12875 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12876 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12877 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12878 inst.instruction |= LOW4 (inst.operands[1].reg); 12879 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 12880 inst.instruction |= neon_quad (rs) << 6; 12881 } 12882 else 12883 { 12884 inst.instruction = NEON_ENC_IMMED (inst.instruction); 12885 neon_move_immediate (); 12886 } 12887 12888 inst.instruction = neon_dp_fixup (inst.instruction); 12889} 12890 12891/* Encode instructions of form: 12892 12893 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0| 12894 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | 12895 12896*/ 12897 12898static void 12899neon_mixed_length (struct neon_type_el et, unsigned size) 12900{ 12901 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 12902 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 12903 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 12904 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 12905 inst.instruction |= LOW4 (inst.operands[2].reg); 12906 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 12907 inst.instruction |= (et.type == NT_unsigned) << 24; 12908 inst.instruction |= neon_logbits (size) << 20; 12909 12910 inst.instruction = neon_dp_fixup (inst.instruction); 12911} 12912 12913static void 12914do_neon_dyadic_long (void) 12915{ 12916 /* FIXME: Type checking for lengthening op. */ 12917 struct neon_type_el et = neon_check_type (3, NS_QDD, 12918 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY); 12919 neon_mixed_length (et, et.size); 12920} 12921 12922static void 12923do_neon_abal (void) 12924{ 12925 struct neon_type_el et = neon_check_type (3, NS_QDD, 12926 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY); 12927 neon_mixed_length (et, et.size); 12928} 12929 12930static void 12931neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes) 12932{ 12933 if (inst.operands[2].isscalar) 12934 { 12935 struct neon_type_el et = neon_check_type (3, NS_QDS, 12936 N_EQK | N_DBL, N_EQK, regtypes | N_KEY); 12937 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 12938 neon_mul_mac (et, et.type == NT_unsigned); 12939 } 12940 else 12941 { 12942 struct neon_type_el et = neon_check_type (3, NS_QDD, 12943 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY); 12944 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12945 neon_mixed_length (et, et.size); 12946 } 12947} 12948 12949static void 12950do_neon_mac_maybe_scalar_long (void) 12951{ 12952 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32); 12953} 12954 12955static void 12956do_neon_dyadic_wide (void) 12957{ 12958 struct neon_type_el et = neon_check_type (3, NS_QQD, 12959 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY); 12960 neon_mixed_length (et, et.size); 12961} 12962 12963static void 12964do_neon_dyadic_narrow (void) 12965{ 12966 struct neon_type_el et = neon_check_type (3, NS_QDD, 12967 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY); 12968 /* Operand sign is unimportant, and the U bit is part of the opcode, 12969 so force the operand type to integer. */ 12970 et.type = NT_integer; 12971 neon_mixed_length (et, et.size / 2); 12972} 12973 12974static void 12975do_neon_mul_sat_scalar_long (void) 12976{ 12977 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32); 12978} 12979 12980static void 12981do_neon_vmull (void) 12982{ 12983 if (inst.operands[2].isscalar) 12984 do_neon_mac_maybe_scalar_long (); 12985 else 12986 { 12987 struct neon_type_el et = neon_check_type (3, NS_QDD, 12988 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY); 12989 if (et.type == NT_poly) 12990 inst.instruction = NEON_ENC_POLY (inst.instruction); 12991 else 12992 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 12993 /* For polynomial encoding, size field must be 0b00 and the U bit must be 12994 zero. Should be OK as-is. */ 12995 neon_mixed_length (et, et.size); 12996 } 12997} 12998 12999static void 13000do_neon_ext (void) 13001{ 13002 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); 13003 struct neon_type_el et = neon_check_type (3, rs, 13004 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); 13005 unsigned imm = (inst.operands[3].imm * et.size) / 8; 13006 constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range")); 13007 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13008 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13009 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13010 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13011 inst.instruction |= LOW4 (inst.operands[2].reg); 13012 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13013 inst.instruction |= neon_quad (rs) << 6; 13014 inst.instruction |= imm << 8; 13015 13016 inst.instruction = neon_dp_fixup (inst.instruction); 13017} 13018 13019static void 13020do_neon_rev (void) 13021{ 13022 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13023 struct neon_type_el et = neon_check_type (2, rs, 13024 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13025 unsigned op = (inst.instruction >> 7) & 3; 13026 /* N (width of reversed regions) is encoded as part of the bitmask. We 13027 extract it here to check the elements to be reversed are smaller. 13028 Otherwise we'd get a reserved instruction. */ 13029 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0; 13030 assert (elsize != 0); 13031 constraint (et.size >= elsize, 13032 _("elements must be smaller than reversal region")); 13033 neon_two_same (neon_quad (rs), 1, et.size); 13034} 13035 13036static void 13037do_neon_dup (void) 13038{ 13039 if (inst.operands[1].isscalar) 13040 { 13041 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); 13042 struct neon_type_el et = neon_check_type (2, rs, 13043 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13044 unsigned sizebits = et.size >> 3; 13045 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg); 13046 int logsize = neon_logbits (et.size); 13047 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize; 13048 13049 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL) 13050 return; 13051 13052 inst.instruction = NEON_ENC_SCALAR (inst.instruction); 13053 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13054 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13055 inst.instruction |= LOW4 (dm); 13056 inst.instruction |= HI1 (dm) << 5; 13057 inst.instruction |= neon_quad (rs) << 6; 13058 inst.instruction |= x << 17; 13059 inst.instruction |= sizebits << 16; 13060 13061 inst.instruction = neon_dp_fixup (inst.instruction); 13062 } 13063 else 13064 { 13065 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); 13066 struct neon_type_el et = neon_check_type (2, rs, 13067 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13068 /* Duplicate ARM register to lanes of vector. */ 13069 inst.instruction = NEON_ENC_ARMREG (inst.instruction); 13070 switch (et.size) 13071 { 13072 case 8: inst.instruction |= 0x400000; break; 13073 case 16: inst.instruction |= 0x000020; break; 13074 case 32: inst.instruction |= 0x000000; break; 13075 default: break; 13076 } 13077 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13078 inst.instruction |= LOW4 (inst.operands[0].reg) << 16; 13079 inst.instruction |= HI1 (inst.operands[0].reg) << 7; 13080 inst.instruction |= neon_quad (rs) << 21; 13081 /* The encoding for this instruction is identical for the ARM and Thumb 13082 variants, except for the condition field. */ 13083 do_vfp_cond_or_thumb (); 13084 } 13085} 13086 13087/* VMOV has particularly many variations. It can be one of: 13088 0. VMOV<c><q> <Qd>, <Qm> 13089 1. VMOV<c><q> <Dd>, <Dm> 13090 (Register operations, which are VORR with Rm = Rn.) 13091 2. VMOV<c><q>.<dt> <Qd>, #<imm> 13092 3. VMOV<c><q>.<dt> <Dd>, #<imm> 13093 (Immediate loads.) 13094 4. VMOV<c><q>.<size> <Dn[x]>, <Rd> 13095 (ARM register to scalar.) 13096 5. VMOV<c><q> <Dm>, <Rd>, <Rn> 13097 (Two ARM registers to vector.) 13098 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]> 13099 (Scalar to ARM register.) 13100 7. VMOV<c><q> <Rd>, <Rn>, <Dm> 13101 (Vector to two ARM registers.) 13102 8. VMOV.F32 <Sd>, <Sm> 13103 9. VMOV.F64 <Dd>, <Dm> 13104 (VFP register moves.) 13105 10. VMOV.F32 <Sd>, #imm 13106 11. VMOV.F64 <Dd>, #imm 13107 (VFP float immediate load.) 13108 12. VMOV <Rd>, <Sm> 13109 (VFP single to ARM reg.) 13110 13. VMOV <Sd>, <Rm> 13111 (ARM reg to VFP single.) 13112 14. VMOV <Rd>, <Re>, <Sn>, <Sm> 13113 (Two ARM regs to two VFP singles.) 13114 15. VMOV <Sd>, <Se>, <Rn>, <Rm> 13115 (Two VFP singles to two ARM regs.) 13116 13117 These cases can be disambiguated using neon_select_shape, except cases 1/9 13118 and 3/11 which depend on the operand type too. 13119 13120 All the encoded bits are hardcoded by this function. 13121 13122 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!). 13123 Cases 5, 7 may be used with VFPv2 and above. 13124 13125 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you 13126 can specify a type where it doesn't make sense to, and is ignored). 13127*/ 13128 13129static void 13130do_neon_mov (void) 13131{ 13132 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD, 13133 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR, 13134 NS_NULL); 13135 struct neon_type_el et; 13136 const char *ldconst = 0; 13137 13138 switch (rs) 13139 { 13140 case NS_DD: /* case 1/9. */ 13141 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13142 /* It is not an error here if no type is given. */ 13143 inst.error = NULL; 13144 if (et.type == NT_float && et.size == 64) 13145 { 13146 do_vfp_nsyn_opcode ("fcpyd"); 13147 break; 13148 } 13149 /* fall through. */ 13150 13151 case NS_QQ: /* case 0/1. */ 13152 { 13153 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13154 return; 13155 /* The architecture manual I have doesn't explicitly state which 13156 value the U bit should have for register->register moves, but 13157 the equivalent VORR instruction has U = 0, so do that. */ 13158 inst.instruction = 0x0200110; 13159 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13160 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13161 inst.instruction |= LOW4 (inst.operands[1].reg); 13162 inst.instruction |= HI1 (inst.operands[1].reg) << 5; 13163 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13164 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13165 inst.instruction |= neon_quad (rs) << 6; 13166 13167 inst.instruction = neon_dp_fixup (inst.instruction); 13168 } 13169 break; 13170 13171 case NS_DI: /* case 3/11. */ 13172 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY); 13173 inst.error = NULL; 13174 if (et.type == NT_float && et.size == 64) 13175 { 13176 /* case 11 (fconstd). */ 13177 ldconst = "fconstd"; 13178 goto encode_fconstd; 13179 } 13180 /* fall through. */ 13181 13182 case NS_QI: /* case 2/3. */ 13183 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL) 13184 return; 13185 inst.instruction = 0x0800010; 13186 neon_move_immediate (); 13187 inst.instruction = neon_dp_fixup (inst.instruction); 13188 break; 13189 13190 case NS_SR: /* case 4. */ 13191 { 13192 unsigned bcdebits = 0; 13193 struct neon_type_el et = neon_check_type (2, NS_NULL, 13194 N_8 | N_16 | N_32 | N_KEY, N_EQK); 13195 int logsize = neon_logbits (et.size); 13196 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg); 13197 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg); 13198 13199 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13200 _(BAD_FPU)); 13201 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13202 && et.size != 32, _(BAD_FPU)); 13203 constraint (et.type == NT_invtype, _("bad type for scalar")); 13204 constraint (x >= 64 / et.size, _("scalar index out of range")); 13205 13206 switch (et.size) 13207 { 13208 case 8: bcdebits = 0x8; break; 13209 case 16: bcdebits = 0x1; break; 13210 case 32: bcdebits = 0x0; break; 13211 default: ; 13212 } 13213 13214 bcdebits |= x << logsize; 13215 13216 inst.instruction = 0xe000b10; 13217 do_vfp_cond_or_thumb (); 13218 inst.instruction |= LOW4 (dn) << 16; 13219 inst.instruction |= HI1 (dn) << 7; 13220 inst.instruction |= inst.operands[1].reg << 12; 13221 inst.instruction |= (bcdebits & 3) << 5; 13222 inst.instruction |= (bcdebits >> 2) << 21; 13223 } 13224 break; 13225 13226 case NS_DRR: /* case 5 (fmdrr). */ 13227 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13228 _(BAD_FPU)); 13229 13230 inst.instruction = 0xc400b10; 13231 do_vfp_cond_or_thumb (); 13232 inst.instruction |= LOW4 (inst.operands[0].reg); 13233 inst.instruction |= HI1 (inst.operands[0].reg) << 5; 13234 inst.instruction |= inst.operands[1].reg << 12; 13235 inst.instruction |= inst.operands[2].reg << 16; 13236 break; 13237 13238 case NS_RS: /* case 6. */ 13239 { 13240 struct neon_type_el et = neon_check_type (2, NS_NULL, 13241 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY); 13242 unsigned logsize = neon_logbits (et.size); 13243 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg); 13244 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg); 13245 unsigned abcdebits = 0; 13246 13247 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1), 13248 _(BAD_FPU)); 13249 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1) 13250 && et.size != 32, _(BAD_FPU)); 13251 constraint (et.type == NT_invtype, _("bad type for scalar")); 13252 constraint (x >= 64 / et.size, _("scalar index out of range")); 13253 13254 switch (et.size) 13255 { 13256 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break; 13257 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break; 13258 case 32: abcdebits = 0x00; break; 13259 default: ; 13260 } 13261 13262 abcdebits |= x << logsize; 13263 inst.instruction = 0xe100b10; 13264 do_vfp_cond_or_thumb (); 13265 inst.instruction |= LOW4 (dn) << 16; 13266 inst.instruction |= HI1 (dn) << 7; 13267 inst.instruction |= inst.operands[0].reg << 12; 13268 inst.instruction |= (abcdebits & 3) << 5; 13269 inst.instruction |= (abcdebits >> 2) << 21; 13270 } 13271 break; 13272 13273 case NS_RRD: /* case 7 (fmrrd). */ 13274 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2), 13275 _(BAD_FPU)); 13276 13277 inst.instruction = 0xc500b10; 13278 do_vfp_cond_or_thumb (); 13279 inst.instruction |= inst.operands[0].reg << 12; 13280 inst.instruction |= inst.operands[1].reg << 16; 13281 inst.instruction |= LOW4 (inst.operands[2].reg); 13282 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13283 break; 13284 13285 case NS_FF: /* case 8 (fcpys). */ 13286 do_vfp_nsyn_opcode ("fcpys"); 13287 break; 13288 13289 case NS_FI: /* case 10 (fconsts). */ 13290 ldconst = "fconsts"; 13291 encode_fconstd: 13292 if (is_quarter_float (inst.operands[1].imm)) 13293 { 13294 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm); 13295 do_vfp_nsyn_opcode (ldconst); 13296 } 13297 else 13298 first_error (_("immediate out of range")); 13299 break; 13300 13301 case NS_RF: /* case 12 (fmrs). */ 13302 do_vfp_nsyn_opcode ("fmrs"); 13303 break; 13304 13305 case NS_FR: /* case 13 (fmsr). */ 13306 do_vfp_nsyn_opcode ("fmsr"); 13307 break; 13308 13309 /* The encoders for the fmrrs and fmsrr instructions expect three operands 13310 (one of which is a list), but we have parsed four. Do some fiddling to 13311 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2 13312 expect. */ 13313 case NS_RRFF: /* case 14 (fmrrs). */ 13314 constraint (inst.operands[3].reg != inst.operands[2].reg + 1, 13315 _("VFP registers must be adjacent")); 13316 inst.operands[2].imm = 2; 13317 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13318 do_vfp_nsyn_opcode ("fmrrs"); 13319 break; 13320 13321 case NS_FFRR: /* case 15 (fmsrr). */ 13322 constraint (inst.operands[1].reg != inst.operands[0].reg + 1, 13323 _("VFP registers must be adjacent")); 13324 inst.operands[1] = inst.operands[2]; 13325 inst.operands[2] = inst.operands[3]; 13326 inst.operands[0].imm = 2; 13327 memset (&inst.operands[3], '\0', sizeof (inst.operands[3])); 13328 do_vfp_nsyn_opcode ("fmsrr"); 13329 break; 13330 13331 default: 13332 abort (); 13333 } 13334} 13335 13336static void 13337do_neon_rshift_round_imm (void) 13338{ 13339 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); 13340 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY); 13341 int imm = inst.operands[2].imm; 13342 13343 /* imm == 0 case is encoded as VMOV for V{R}SHR. */ 13344 if (imm == 0) 13345 { 13346 inst.operands[2].present = 0; 13347 do_neon_mov (); 13348 return; 13349 } 13350 13351 constraint (imm < 1 || (unsigned)imm > et.size, 13352 _("immediate out of range for shift")); 13353 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, 13354 et.size - imm); 13355} 13356 13357static void 13358do_neon_movl (void) 13359{ 13360 struct neon_type_el et = neon_check_type (2, NS_QD, 13361 N_EQK | N_DBL, N_SU_32 | N_KEY); 13362 unsigned sizebits = et.size >> 3; 13363 inst.instruction |= sizebits << 19; 13364 neon_two_same (0, et.type == NT_unsigned, -1); 13365} 13366 13367static void 13368do_neon_trn (void) 13369{ 13370 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13371 struct neon_type_el et = neon_check_type (2, rs, 13372 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13373 inst.instruction = NEON_ENC_INTEGER (inst.instruction); 13374 neon_two_same (neon_quad (rs), 1, et.size); 13375} 13376 13377static void 13378do_neon_zip_uzp (void) 13379{ 13380 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13381 struct neon_type_el et = neon_check_type (2, rs, 13382 N_EQK, N_8 | N_16 | N_32 | N_KEY); 13383 if (rs == NS_DD && et.size == 32) 13384 { 13385 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */ 13386 inst.instruction = N_MNEM_vtrn; 13387 do_neon_trn (); 13388 return; 13389 } 13390 neon_two_same (neon_quad (rs), 1, et.size); 13391} 13392 13393static void 13394do_neon_sat_abs_neg (void) 13395{ 13396 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13397 struct neon_type_el et = neon_check_type (2, rs, 13398 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13399 neon_two_same (neon_quad (rs), 1, et.size); 13400} 13401 13402static void 13403do_neon_pair_long (void) 13404{ 13405 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13406 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY); 13407 /* Unsigned is encoded in OP field (bit 7) for these instruction. */ 13408 inst.instruction |= (et.type == NT_unsigned) << 7; 13409 neon_two_same (neon_quad (rs), 1, et.size); 13410} 13411 13412static void 13413do_neon_recip_est (void) 13414{ 13415 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13416 struct neon_type_el et = neon_check_type (2, rs, 13417 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY); 13418 inst.instruction |= (et.type == NT_float) << 8; 13419 neon_two_same (neon_quad (rs), 1, et.size); 13420} 13421 13422static void 13423do_neon_cls (void) 13424{ 13425 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13426 struct neon_type_el et = neon_check_type (2, rs, 13427 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY); 13428 neon_two_same (neon_quad (rs), 1, et.size); 13429} 13430 13431static void 13432do_neon_clz (void) 13433{ 13434 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13435 struct neon_type_el et = neon_check_type (2, rs, 13436 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY); 13437 neon_two_same (neon_quad (rs), 1, et.size); 13438} 13439 13440static void 13441do_neon_cnt (void) 13442{ 13443 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13444 struct neon_type_el et = neon_check_type (2, rs, 13445 N_EQK | N_INT, N_8 | N_KEY); 13446 neon_two_same (neon_quad (rs), 1, et.size); 13447} 13448 13449static void 13450do_neon_swp (void) 13451{ 13452 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); 13453 neon_two_same (neon_quad (rs), 1, -1); 13454} 13455 13456static void 13457do_neon_tbl_tbx (void) 13458{ 13459 unsigned listlenbits; 13460 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY); 13461 13462 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4) 13463 { 13464 first_error (_("bad list length for table lookup")); 13465 return; 13466 } 13467 13468 listlenbits = inst.operands[1].imm - 1; 13469 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13470 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13471 inst.instruction |= LOW4 (inst.operands[1].reg) << 16; 13472 inst.instruction |= HI1 (inst.operands[1].reg) << 7; 13473 inst.instruction |= LOW4 (inst.operands[2].reg); 13474 inst.instruction |= HI1 (inst.operands[2].reg) << 5; 13475 inst.instruction |= listlenbits << 8; 13476 13477 inst.instruction = neon_dp_fixup (inst.instruction); 13478} 13479 13480static void 13481do_neon_ldm_stm (void) 13482{ 13483 /* P, U and L bits are part of bitmask. */ 13484 int is_dbmode = (inst.instruction & (1 << 24)) != 0; 13485 unsigned offsetbits = inst.operands[1].imm * 2; 13486 13487 if (inst.operands[1].issingle) 13488 { 13489 do_vfp_nsyn_ldm_stm (is_dbmode); 13490 return; 13491 } 13492 13493 constraint (is_dbmode && !inst.operands[0].writeback, 13494 _("writeback (!) must be used for VLDMDB and VSTMDB")); 13495 13496 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16, 13497 _("register list must contain at least 1 and at most 16 " 13498 "registers")); 13499 13500 inst.instruction |= inst.operands[0].reg << 16; 13501 inst.instruction |= inst.operands[0].writeback << 21; 13502 inst.instruction |= LOW4 (inst.operands[1].reg) << 12; 13503 inst.instruction |= HI1 (inst.operands[1].reg) << 22; 13504 13505 inst.instruction |= offsetbits; 13506 13507 do_vfp_cond_or_thumb (); 13508} 13509 13510static void 13511do_neon_ldr_str (void) 13512{ 13513 int is_ldr = (inst.instruction & (1 << 20)) != 0; 13514 13515 if (inst.operands[0].issingle) 13516 { 13517 if (is_ldr) 13518 do_vfp_nsyn_opcode ("flds"); 13519 else 13520 do_vfp_nsyn_opcode ("fsts"); 13521 } 13522 else 13523 { 13524 if (is_ldr) 13525 do_vfp_nsyn_opcode ("fldd"); 13526 else 13527 do_vfp_nsyn_opcode ("fstd"); 13528 } 13529} 13530 13531/* "interleave" version also handles non-interleaving register VLD1/VST1 13532 instructions. */ 13533 13534static void 13535do_neon_ld_st_interleave (void) 13536{ 13537 struct neon_type_el et = neon_check_type (1, NS_NULL, 13538 N_8 | N_16 | N_32 | N_64); 13539 unsigned alignbits = 0; 13540 unsigned idx; 13541 /* The bits in this table go: 13542 0: register stride of one (0) or two (1) 13543 1,2: register list length, minus one (1, 2, 3, 4). 13544 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>). 13545 We use -1 for invalid entries. */ 13546 const int typetable[] = 13547 { 13548 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */ 13549 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */ 13550 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */ 13551 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */ 13552 }; 13553 int typebits; 13554 13555 if (et.type == NT_invtype) 13556 return; 13557 13558 if (inst.operands[1].immisalign) 13559 switch (inst.operands[1].imm >> 8) 13560 { 13561 case 64: alignbits = 1; break; 13562 case 128: 13563 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13564 goto bad_alignment; 13565 alignbits = 2; 13566 break; 13567 case 256: 13568 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3) 13569 goto bad_alignment; 13570 alignbits = 3; 13571 break; 13572 default: 13573 bad_alignment: 13574 first_error (_("bad alignment")); 13575 return; 13576 } 13577 13578 inst.instruction |= alignbits << 4; 13579 inst.instruction |= neon_logbits (et.size) << 6; 13580 13581 /* Bits [4:6] of the immediate in a list specifier encode register stride 13582 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of 13583 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look 13584 up the right value for "type" in a table based on this value and the given 13585 list style, then stick it back. */ 13586 idx = ((inst.operands[0].imm >> 4) & 7) 13587 | (((inst.instruction >> 8) & 3) << 3); 13588 13589 typebits = typetable[idx]; 13590 13591 constraint (typebits == -1, _("bad list type for instruction")); 13592 13593 inst.instruction &= ~0xf00; 13594 inst.instruction |= typebits << 8; 13595} 13596 13597/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup. 13598 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0 13599 otherwise. The variable arguments are a list of pairs of legal (size, align) 13600 values, terminated with -1. */ 13601 13602static int 13603neon_alignment_bit (int size, int align, int *do_align, ...) 13604{ 13605 va_list ap; 13606 int result = FAIL, thissize, thisalign; 13607 13608 if (!inst.operands[1].immisalign) 13609 { 13610 *do_align = 0; 13611 return SUCCESS; 13612 } 13613 13614 va_start (ap, do_align); 13615 13616 do 13617 { 13618 thissize = va_arg (ap, int); 13619 if (thissize == -1) 13620 break; 13621 thisalign = va_arg (ap, int); 13622 13623 if (size == thissize && align == thisalign) 13624 result = SUCCESS; 13625 } 13626 while (result != SUCCESS); 13627 13628 va_end (ap); 13629 13630 if (result == SUCCESS) 13631 *do_align = 1; 13632 else 13633 first_error (_("unsupported alignment for instruction")); 13634 13635 return result; 13636} 13637 13638static void 13639do_neon_ld_st_lane (void) 13640{ 13641 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13642 int align_good, do_align = 0; 13643 int logsize = neon_logbits (et.size); 13644 int align = inst.operands[1].imm >> 8; 13645 int n = (inst.instruction >> 8) & 3; 13646 int max_el = 64 / et.size; 13647 13648 if (et.type == NT_invtype) 13649 return; 13650 13651 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1, 13652 _("bad list length")); 13653 constraint (NEON_LANE (inst.operands[0].imm) >= max_el, 13654 _("scalar index out of range")); 13655 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2 13656 && et.size == 8, 13657 _("stride of 2 unavailable when element size is 8")); 13658 13659 switch (n) 13660 { 13661 case 0: /* VLD1 / VST1. */ 13662 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16, 13663 32, 32, -1); 13664 if (align_good == FAIL) 13665 return; 13666 if (do_align) 13667 { 13668 unsigned alignbits = 0; 13669 switch (et.size) 13670 { 13671 case 16: alignbits = 0x1; break; 13672 case 32: alignbits = 0x3; break; 13673 default: ; 13674 } 13675 inst.instruction |= alignbits << 4; 13676 } 13677 break; 13678 13679 case 1: /* VLD2 / VST2. */ 13680 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32, 13681 32, 64, -1); 13682 if (align_good == FAIL) 13683 return; 13684 if (do_align) 13685 inst.instruction |= 1 << 4; 13686 break; 13687 13688 case 2: /* VLD3 / VST3. */ 13689 constraint (inst.operands[1].immisalign, 13690 _("can't use alignment with this instruction")); 13691 break; 13692 13693 case 3: /* VLD4 / VST4. */ 13694 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13695 16, 64, 32, 64, 32, 128, -1); 13696 if (align_good == FAIL) 13697 return; 13698 if (do_align) 13699 { 13700 unsigned alignbits = 0; 13701 switch (et.size) 13702 { 13703 case 8: alignbits = 0x1; break; 13704 case 16: alignbits = 0x1; break; 13705 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break; 13706 default: ; 13707 } 13708 inst.instruction |= alignbits << 4; 13709 } 13710 break; 13711 13712 default: ; 13713 } 13714 13715 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */ 13716 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13717 inst.instruction |= 1 << (4 + logsize); 13718 13719 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5); 13720 inst.instruction |= logsize << 10; 13721} 13722 13723/* Encode single n-element structure to all lanes VLD<n> instructions. */ 13724 13725static void 13726do_neon_ld_dup (void) 13727{ 13728 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32); 13729 int align_good, do_align = 0; 13730 13731 if (et.type == NT_invtype) 13732 return; 13733 13734 switch ((inst.instruction >> 8) & 3) 13735 { 13736 case 0: /* VLD1. */ 13737 assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2); 13738 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13739 &do_align, 16, 16, 32, 32, -1); 13740 if (align_good == FAIL) 13741 return; 13742 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm)) 13743 { 13744 case 1: break; 13745 case 2: inst.instruction |= 1 << 5; break; 13746 default: first_error (_("bad list length")); return; 13747 } 13748 inst.instruction |= neon_logbits (et.size) << 6; 13749 break; 13750 13751 case 1: /* VLD2. */ 13752 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8, 13753 &do_align, 8, 16, 16, 32, 32, 64, -1); 13754 if (align_good == FAIL) 13755 return; 13756 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2, 13757 _("bad list length")); 13758 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13759 inst.instruction |= 1 << 5; 13760 inst.instruction |= neon_logbits (et.size) << 6; 13761 break; 13762 13763 case 2: /* VLD3. */ 13764 constraint (inst.operands[1].immisalign, 13765 _("can't use alignment with this instruction")); 13766 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3, 13767 _("bad list length")); 13768 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13769 inst.instruction |= 1 << 5; 13770 inst.instruction |= neon_logbits (et.size) << 6; 13771 break; 13772 13773 case 3: /* VLD4. */ 13774 { 13775 int align = inst.operands[1].imm >> 8; 13776 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32, 13777 16, 64, 32, 64, 32, 128, -1); 13778 if (align_good == FAIL) 13779 return; 13780 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4, 13781 _("bad list length")); 13782 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2) 13783 inst.instruction |= 1 << 5; 13784 if (et.size == 32 && align == 128) 13785 inst.instruction |= 0x3 << 6; 13786 else 13787 inst.instruction |= neon_logbits (et.size) << 6; 13788 } 13789 break; 13790 13791 default: ; 13792 } 13793 13794 inst.instruction |= do_align << 4; 13795} 13796 13797/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those 13798 apart from bits [11:4]. */ 13799 13800static void 13801do_neon_ldx_stx (void) 13802{ 13803 switch (NEON_LANE (inst.operands[0].imm)) 13804 { 13805 case NEON_INTERLEAVE_LANES: 13806 inst.instruction = NEON_ENC_INTERLV (inst.instruction); 13807 do_neon_ld_st_interleave (); 13808 break; 13809 13810 case NEON_ALL_LANES: 13811 inst.instruction = NEON_ENC_DUP (inst.instruction); 13812 do_neon_ld_dup (); 13813 break; 13814 13815 default: 13816 inst.instruction = NEON_ENC_LANE (inst.instruction); 13817 do_neon_ld_st_lane (); 13818 } 13819 13820 /* L bit comes from bit mask. */ 13821 inst.instruction |= LOW4 (inst.operands[0].reg) << 12; 13822 inst.instruction |= HI1 (inst.operands[0].reg) << 22; 13823 inst.instruction |= inst.operands[1].reg << 16; 13824 13825 if (inst.operands[1].postind) 13826 { 13827 int postreg = inst.operands[1].imm & 0xf; 13828 constraint (!inst.operands[1].immisreg, 13829 _("post-index must be a register")); 13830 constraint (postreg == 0xd || postreg == 0xf, 13831 _("bad register for post-index")); 13832 inst.instruction |= postreg; 13833 } 13834 else if (inst.operands[1].writeback) 13835 { 13836 inst.instruction |= 0xd; 13837 } 13838 else 13839 inst.instruction |= 0xf; 13840 13841 if (thumb_mode) 13842 inst.instruction |= 0xf9000000; 13843 else 13844 inst.instruction |= 0xf4000000; 13845} 13846 13847 13848/* Overall per-instruction processing. */ 13849 13850/* We need to be able to fix up arbitrary expressions in some statements. 13851 This is so that we can handle symbols that are an arbitrary distance from 13852 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask), 13853 which returns part of an address in a form which will be valid for 13854 a data instruction. We do this by pushing the expression into a symbol 13855 in the expr_section, and creating a fix for that. */ 13856 13857static void 13858fix_new_arm (fragS * frag, 13859 int where, 13860 short int size, 13861 expressionS * exp, 13862 int pc_rel, 13863 int reloc) 13864{ 13865 fixS * new_fix; 13866 13867 switch (exp->X_op) 13868 { 13869 case O_constant: 13870 case O_symbol: 13871 case O_add: 13872 case O_subtract: 13873 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc); 13874 break; 13875 13876 default: 13877 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, 13878 pc_rel, reloc); 13879 break; 13880 } 13881 13882 /* Mark whether the fix is to a THUMB instruction, or an ARM 13883 instruction. */ 13884 new_fix->tc_fix_data = thumb_mode; 13885} 13886 13887/* Create a frg for an instruction requiring relaxation. */ 13888static void 13889output_relax_insn (void) 13890{ 13891 char * to; 13892 symbolS *sym; 13893 int offset; 13894 13895 /* The size of the instruction is unknown, so tie the debug info to the 13896 start of the instruction. */ 13897 dwarf2_emit_insn (0); 13898 13899 switch (inst.reloc.exp.X_op) 13900 { 13901 case O_symbol: 13902 sym = inst.reloc.exp.X_add_symbol; 13903 offset = inst.reloc.exp.X_add_number; 13904 break; 13905 case O_constant: 13906 sym = NULL; 13907 offset = inst.reloc.exp.X_add_number; 13908 break; 13909 default: 13910 sym = make_expr_symbol (&inst.reloc.exp); 13911 offset = 0; 13912 break; 13913 } 13914 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE, 13915 inst.relax, sym, offset, NULL/*offset, opcode*/); 13916 md_number_to_chars (to, inst.instruction, THUMB_SIZE); 13917} 13918 13919/* Write a 32-bit thumb instruction to buf. */ 13920static void 13921put_thumb32_insn (char * buf, unsigned long insn) 13922{ 13923 md_number_to_chars (buf, insn >> 16, THUMB_SIZE); 13924 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE); 13925} 13926 13927static void 13928output_inst (const char * str) 13929{ 13930 char * to = NULL; 13931 13932 if (inst.error) 13933 { 13934 as_bad ("%s -- `%s'", inst.error, str); 13935 return; 13936 } 13937 if (inst.relax) { 13938 output_relax_insn(); 13939 return; 13940 } 13941 if (inst.size == 0) 13942 return; 13943 13944 to = frag_more (inst.size); 13945 13946 if (thumb_mode && (inst.size > THUMB_SIZE)) 13947 { 13948 assert (inst.size == (2 * THUMB_SIZE)); 13949 put_thumb32_insn (to, inst.instruction); 13950 } 13951 else if (inst.size > INSN_SIZE) 13952 { 13953 assert (inst.size == (2 * INSN_SIZE)); 13954 md_number_to_chars (to, inst.instruction, INSN_SIZE); 13955 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE); 13956 } 13957 else 13958 md_number_to_chars (to, inst.instruction, inst.size); 13959 13960 if (inst.reloc.type != BFD_RELOC_UNUSED) 13961 fix_new_arm (frag_now, to - frag_now->fr_literal, 13962 inst.size, & inst.reloc.exp, inst.reloc.pc_rel, 13963 inst.reloc.type); 13964 13965 dwarf2_emit_insn (inst.size); 13966} 13967 13968/* Tag values used in struct asm_opcode's tag field. */ 13969enum opcode_tag 13970{ 13971 OT_unconditional, /* Instruction cannot be conditionalized. 13972 The ARM condition field is still 0xE. */ 13973 OT_unconditionalF, /* Instruction cannot be conditionalized 13974 and carries 0xF in its ARM condition field. */ 13975 OT_csuffix, /* Instruction takes a conditional suffix. */ 13976 OT_csuffixF, /* Some forms of the instruction take a conditional 13977 suffix, others place 0xF where the condition field 13978 would be. */ 13979 OT_cinfix3, /* Instruction takes a conditional infix, 13980 beginning at character index 3. (In 13981 unified mode, it becomes a suffix.) */ 13982 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for 13983 tsts, cmps, cmns, and teqs. */ 13984 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at 13985 character index 3, even in unified mode. Used for 13986 legacy instructions where suffix and infix forms 13987 may be ambiguous. */ 13988 OT_csuf_or_in3, /* Instruction takes either a conditional 13989 suffix or an infix at character index 3. */ 13990 OT_odd_infix_unc, /* This is the unconditional variant of an 13991 instruction that takes a conditional infix 13992 at an unusual position. In unified mode, 13993 this variant will accept a suffix. */ 13994 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0 13995 are the conditional variants of instructions that 13996 take conditional infixes in unusual positions. 13997 The infix appears at character index 13998 (tag - OT_odd_infix_0). These are not accepted 13999 in unified mode. */ 14000}; 14001 14002/* Subroutine of md_assemble, responsible for looking up the primary 14003 opcode from the mnemonic the user wrote. STR points to the 14004 beginning of the mnemonic. 14005 14006 This is not simply a hash table lookup, because of conditional 14007 variants. Most instructions have conditional variants, which are 14008 expressed with a _conditional affix_ to the mnemonic. If we were 14009 to encode each conditional variant as a literal string in the opcode 14010 table, it would have approximately 20,000 entries. 14011 14012 Most mnemonics take this affix as a suffix, and in unified syntax, 14013 'most' is upgraded to 'all'. However, in the divided syntax, some 14014 instructions take the affix as an infix, notably the s-variants of 14015 the arithmetic instructions. Of those instructions, all but six 14016 have the infix appear after the third character of the mnemonic. 14017 14018 Accordingly, the algorithm for looking up primary opcodes given 14019 an identifier is: 14020 14021 1. Look up the identifier in the opcode table. 14022 If we find a match, go to step U. 14023 14024 2. Look up the last two characters of the identifier in the 14025 conditions table. If we find a match, look up the first N-2 14026 characters of the identifier in the opcode table. If we 14027 find a match, go to step CE. 14028 14029 3. Look up the fourth and fifth characters of the identifier in 14030 the conditions table. If we find a match, extract those 14031 characters from the identifier, and look up the remaining 14032 characters in the opcode table. If we find a match, go 14033 to step CM. 14034 14035 4. Fail. 14036 14037 U. Examine the tag field of the opcode structure, in case this is 14038 one of the six instructions with its conditional infix in an 14039 unusual place. If it is, the tag tells us where to find the 14040 infix; look it up in the conditions table and set inst.cond 14041 accordingly. Otherwise, this is an unconditional instruction. 14042 Again set inst.cond accordingly. Return the opcode structure. 14043 14044 CE. Examine the tag field to make sure this is an instruction that 14045 should receive a conditional suffix. If it is not, fail. 14046 Otherwise, set inst.cond from the suffix we already looked up, 14047 and return the opcode structure. 14048 14049 CM. Examine the tag field to make sure this is an instruction that 14050 should receive a conditional infix after the third character. 14051 If it is not, fail. Otherwise, undo the edits to the current 14052 line of input and proceed as for case CE. */ 14053 14054static const struct asm_opcode * 14055opcode_lookup (char **str) 14056{ 14057 char *end, *base; 14058 char *affix; 14059 const struct asm_opcode *opcode; 14060 const struct asm_cond *cond; 14061 char save[2]; 14062 bfd_boolean neon_supported; 14063 14064 neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1); 14065 14066 /* Scan up to the end of the mnemonic, which must end in white space, 14067 '.' (in unified mode, or for Neon instructions), or end of string. */ 14068 for (base = end = *str; *end != '\0'; end++) 14069 if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.')) 14070 break; 14071 14072 if (end == base) 14073 return 0; 14074 14075 /* Handle a possible width suffix and/or Neon type suffix. */ 14076 if (end[0] == '.') 14077 { 14078 int offset = 2; 14079 14080 /* The .w and .n suffixes are only valid if the unified syntax is in 14081 use. */ 14082 if (unified_syntax && end[1] == 'w') 14083 inst.size_req = 4; 14084 else if (unified_syntax && end[1] == 'n') 14085 inst.size_req = 2; 14086 else 14087 offset = 0; 14088 14089 inst.vectype.elems = 0; 14090 14091 *str = end + offset; 14092 14093 if (end[offset] == '.') 14094 { 14095 /* See if we have a Neon type suffix (possible in either unified or 14096 non-unified ARM syntax mode). */ 14097 if (parse_neon_type (&inst.vectype, str) == FAIL) 14098 return 0; 14099 } 14100 else if (end[offset] != '\0' && end[offset] != ' ') 14101 return 0; 14102 } 14103 else 14104 *str = end; 14105 14106 /* Look for unaffixed or special-case affixed mnemonic. */ 14107 opcode = hash_find_n (arm_ops_hsh, base, end - base); 14108 if (opcode) 14109 { 14110 /* step U */ 14111 if (opcode->tag < OT_odd_infix_0) 14112 { 14113 inst.cond = COND_ALWAYS; 14114 return opcode; 14115 } 14116 14117 if (unified_syntax) 14118 as_warn (_("conditional infixes are deprecated in unified syntax")); 14119 affix = base + (opcode->tag - OT_odd_infix_0); 14120 cond = hash_find_n (arm_cond_hsh, affix, 2); 14121 assert (cond); 14122 14123 inst.cond = cond->value; 14124 return opcode; 14125 } 14126 14127 /* Cannot have a conditional suffix on a mnemonic of less than two 14128 characters. */ 14129 if (end - base < 3) 14130 return 0; 14131 14132 /* Look for suffixed mnemonic. */ 14133 affix = end - 2; 14134 cond = hash_find_n (arm_cond_hsh, affix, 2); 14135 opcode = hash_find_n (arm_ops_hsh, base, affix - base); 14136 if (opcode && cond) 14137 { 14138 /* step CE */ 14139 switch (opcode->tag) 14140 { 14141 case OT_cinfix3_legacy: 14142 /* Ignore conditional suffixes matched on infix only mnemonics. */ 14143 break; 14144 14145 case OT_cinfix3: 14146 case OT_cinfix3_deprecated: 14147 case OT_odd_infix_unc: 14148 if (!unified_syntax) 14149 return 0; 14150 /* else fall through */ 14151 14152 case OT_csuffix: 14153 case OT_csuffixF: 14154 case OT_csuf_or_in3: 14155 inst.cond = cond->value; 14156 return opcode; 14157 14158 case OT_unconditional: 14159 case OT_unconditionalF: 14160 if (thumb_mode) 14161 { 14162 inst.cond = cond->value; 14163 } 14164 else 14165 { 14166 /* delayed diagnostic */ 14167 inst.error = BAD_COND; 14168 inst.cond = COND_ALWAYS; 14169 } 14170 return opcode; 14171 14172 default: 14173 return 0; 14174 } 14175 } 14176 14177 /* Cannot have a usual-position infix on a mnemonic of less than 14178 six characters (five would be a suffix). */ 14179 if (end - base < 6) 14180 return 0; 14181 14182 /* Look for infixed mnemonic in the usual position. */ 14183 affix = base + 3; 14184 cond = hash_find_n (arm_cond_hsh, affix, 2); 14185 if (!cond) 14186 return 0; 14187 14188 memcpy (save, affix, 2); 14189 memmove (affix, affix + 2, (end - affix) - 2); 14190 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2); 14191 memmove (affix + 2, affix, (end - affix) - 2); 14192 memcpy (affix, save, 2); 14193 14194 if (opcode 14195 && (opcode->tag == OT_cinfix3 14196 || opcode->tag == OT_cinfix3_deprecated 14197 || opcode->tag == OT_csuf_or_in3 14198 || opcode->tag == OT_cinfix3_legacy)) 14199 { 14200 /* step CM */ 14201 if (unified_syntax 14202 && (opcode->tag == OT_cinfix3 14203 || opcode->tag == OT_cinfix3_deprecated)) 14204 as_warn (_("conditional infixes are deprecated in unified syntax")); 14205 14206 inst.cond = cond->value; 14207 return opcode; 14208 } 14209 14210 return 0; 14211} 14212 14213void 14214md_assemble (char *str) 14215{ 14216 char *p = str; 14217 const struct asm_opcode * opcode; 14218 14219 /* Align the previous label if needed. */ 14220 if (last_label_seen != NULL) 14221 { 14222 symbol_set_frag (last_label_seen, frag_now); 14223 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ()); 14224 S_SET_SEGMENT (last_label_seen, now_seg); 14225 } 14226 14227 memset (&inst, '\0', sizeof (inst)); 14228 inst.reloc.type = BFD_RELOC_UNUSED; 14229 14230 opcode = opcode_lookup (&p); 14231 if (!opcode) 14232 { 14233 /* It wasn't an instruction, but it might be a register alias of 14234 the form alias .req reg, or a Neon .dn/.qn directive. */ 14235 if (!create_register_alias (str, p) 14236 && !create_neon_reg_alias (str, p)) 14237 as_bad (_("bad instruction `%s'"), str); 14238 14239 return; 14240 } 14241 14242 if (opcode->tag == OT_cinfix3_deprecated) 14243 as_warn (_("s suffix on comparison instruction is deprecated")); 14244 14245 /* The value which unconditional instructions should have in place of the 14246 condition field. */ 14247 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1; 14248 14249 if (thumb_mode) 14250 { 14251 arm_feature_set variant; 14252 14253 variant = cpu_variant; 14254 /* Only allow coprocessor instructions on Thumb-2 capable devices. */ 14255 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2)) 14256 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard); 14257 /* Check that this instruction is supported for this CPU. */ 14258 if (!opcode->tvariant 14259 || (thumb_mode == 1 14260 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))) 14261 { 14262 as_bad (_("selected processor does not support `%s'"), str); 14263 return; 14264 } 14265 if (inst.cond != COND_ALWAYS && !unified_syntax 14266 && opcode->tencode != do_t_branch) 14267 { 14268 as_bad (_("Thumb does not support conditional execution")); 14269 return; 14270 } 14271 14272 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req) 14273 { 14274 /* Implicit require narrow instructions on Thumb-1. This avoids 14275 relaxation accidentally introducing Thumb-2 instructions. */ 14276 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23) 14277 inst.size_req = 2; 14278 } 14279 14280 /* Check conditional suffixes. */ 14281 if (current_it_mask) 14282 { 14283 int cond; 14284 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1; 14285 current_it_mask <<= 1; 14286 current_it_mask &= 0x1f; 14287 /* The BKPT instruction is unconditional even in an IT block. */ 14288 if (!inst.error 14289 && cond != inst.cond && opcode->tencode != do_t_bkpt) 14290 { 14291 as_bad (_("incorrect condition in IT block")); 14292 return; 14293 } 14294 } 14295 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch) 14296 { 14297 as_bad (_("thumb conditional instrunction not in IT block")); 14298 return; 14299 } 14300 14301 mapping_state (MAP_THUMB); 14302 inst.instruction = opcode->tvalue; 14303 14304 if (!parse_operands (p, opcode->operands)) 14305 opcode->tencode (); 14306 14307 /* Clear current_it_mask at the end of an IT block. */ 14308 if (current_it_mask == 0x10) 14309 current_it_mask = 0; 14310 14311 if (!(inst.error || inst.relax)) 14312 { 14313 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff); 14314 inst.size = (inst.instruction > 0xffff ? 4 : 2); 14315 if (inst.size_req && inst.size_req != inst.size) 14316 { 14317 as_bad (_("cannot honor width suffix -- `%s'"), str); 14318 return; 14319 } 14320 } 14321 14322 /* Something has gone badly wrong if we try to relax a fixed size 14323 instruction. */ 14324 assert (inst.size_req == 0 || !inst.relax); 14325 14326 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14327 *opcode->tvariant); 14328 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly 14329 set those bits when Thumb-2 32-bit instructions are seen. ie. 14330 anything other than bl/blx. 14331 This is overly pessimistic for relaxable instructions. */ 14332 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800) 14333 || inst.relax) 14334 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, 14335 arm_ext_v6t2); 14336 } 14337 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 14338 { 14339 /* Check that this instruction is supported for this CPU. */ 14340 if (!opcode->avariant || 14341 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)) 14342 { 14343 as_bad (_("selected processor does not support `%s'"), str); 14344 return; 14345 } 14346 if (inst.size_req) 14347 { 14348 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str); 14349 return; 14350 } 14351 14352 mapping_state (MAP_ARM); 14353 inst.instruction = opcode->avalue; 14354 if (opcode->tag == OT_unconditionalF) 14355 inst.instruction |= 0xF << 28; 14356 else 14357 inst.instruction |= inst.cond << 28; 14358 inst.size = INSN_SIZE; 14359 if (!parse_operands (p, opcode->operands)) 14360 opcode->aencode (); 14361 /* Arm mode bx is marked as both v4T and v5 because it's still required 14362 on a hypothetical non-thumb v5 core. */ 14363 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t) 14364 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5)) 14365 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t); 14366 else 14367 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, 14368 *opcode->avariant); 14369 } 14370 else 14371 { 14372 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor " 14373 "-- `%s'"), str); 14374 return; 14375 } 14376 output_inst (str); 14377} 14378 14379/* Various frobbings of labels and their addresses. */ 14380 14381void 14382arm_start_line_hook (void) 14383{ 14384 last_label_seen = NULL; 14385} 14386 14387void 14388arm_frob_label (symbolS * sym) 14389{ 14390 last_label_seen = sym; 14391 14392 ARM_SET_THUMB (sym, thumb_mode); 14393 14394#if defined OBJ_COFF || defined OBJ_ELF 14395 ARM_SET_INTERWORK (sym, support_interwork); 14396#endif 14397 14398 /* Note - do not allow local symbols (.Lxxx) to be labeled 14399 as Thumb functions. This is because these labels, whilst 14400 they exist inside Thumb code, are not the entry points for 14401 possible ARM->Thumb calls. Also, these labels can be used 14402 as part of a computed goto or switch statement. eg gcc 14403 can generate code that looks like this: 14404 14405 ldr r2, [pc, .Laaa] 14406 lsl r3, r3, #2 14407 ldr r2, [r3, r2] 14408 mov pc, r2 14409 14410 .Lbbb: .word .Lxxx 14411 .Lccc: .word .Lyyy 14412 ..etc... 14413 .Laaa: .word Lbbb 14414 14415 The first instruction loads the address of the jump table. 14416 The second instruction converts a table index into a byte offset. 14417 The third instruction gets the jump address out of the table. 14418 The fourth instruction performs the jump. 14419 14420 If the address stored at .Laaa is that of a symbol which has the 14421 Thumb_Func bit set, then the linker will arrange for this address 14422 to have the bottom bit set, which in turn would mean that the 14423 address computation performed by the third instruction would end 14424 up with the bottom bit set. Since the ARM is capable of unaligned 14425 word loads, the instruction would then load the incorrect address 14426 out of the jump table, and chaos would ensue. */ 14427 if (label_is_thumb_function_name 14428 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L') 14429 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) 14430 { 14431 /* When the address of a Thumb function is taken the bottom 14432 bit of that address should be set. This will allow 14433 interworking between Arm and Thumb functions to work 14434 correctly. */ 14435 14436 THUMB_SET_FUNC (sym, 1); 14437 14438 label_is_thumb_function_name = FALSE; 14439 } 14440 14441 dwarf2_emit_label (sym); 14442} 14443 14444int 14445arm_data_in_code (void) 14446{ 14447 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5)) 14448 { 14449 *input_line_pointer = '/'; 14450 input_line_pointer += 5; 14451 *input_line_pointer = 0; 14452 return 1; 14453 } 14454 14455 return 0; 14456} 14457 14458char * 14459arm_canonicalize_symbol_name (char * name) 14460{ 14461 int len; 14462 14463 if (thumb_mode && (len = strlen (name)) > 5 14464 && streq (name + len - 5, "/data")) 14465 *(name + len - 5) = 0; 14466 14467 return name; 14468} 14469 14470/* Table of all register names defined by default. The user can 14471 define additional names with .req. Note that all register names 14472 should appear in both upper and lowercase variants. Some registers 14473 also have mixed-case names. */ 14474 14475#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 } 14476#define REGNUM(p,n,t) REGDEF(p##n, n, t) 14477#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t) 14478#define REGSET(p,t) \ 14479 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \ 14480 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \ 14481 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \ 14482 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t) 14483#define REGSETH(p,t) \ 14484 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \ 14485 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \ 14486 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \ 14487 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t) 14488#define REGSET2(p,t) \ 14489 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \ 14490 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \ 14491 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \ 14492 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t) 14493 14494static const struct reg_entry reg_names[] = 14495{ 14496 /* ARM integer registers. */ 14497 REGSET(r, RN), REGSET(R, RN), 14498 14499 /* ATPCS synonyms. */ 14500 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN), 14501 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN), 14502 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN), 14503 14504 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN), 14505 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN), 14506 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN), 14507 14508 /* Well-known aliases. */ 14509 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN), 14510 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN), 14511 14512 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN), 14513 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN), 14514 14515 /* Coprocessor numbers. */ 14516 REGSET(p, CP), REGSET(P, CP), 14517 14518 /* Coprocessor register numbers. The "cr" variants are for backward 14519 compatibility. */ 14520 REGSET(c, CN), REGSET(C, CN), 14521 REGSET(cr, CN), REGSET(CR, CN), 14522 14523 /* FPA registers. */ 14524 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN), 14525 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN), 14526 14527 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN), 14528 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN), 14529 14530 /* VFP SP registers. */ 14531 REGSET(s,VFS), REGSET(S,VFS), 14532 REGSETH(s,VFS), REGSETH(S,VFS), 14533 14534 /* VFP DP Registers. */ 14535 REGSET(d,VFD), REGSET(D,VFD), 14536 /* Extra Neon DP registers. */ 14537 REGSETH(d,VFD), REGSETH(D,VFD), 14538 14539 /* Neon QP registers. */ 14540 REGSET2(q,NQ), REGSET2(Q,NQ), 14541 14542 /* VFP control registers. */ 14543 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC), 14544 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC), 14545 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC), 14546 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC), 14547 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC), 14548 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC), 14549 14550 /* Maverick DSP coprocessor registers. */ 14551 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), 14552 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX), 14553 14554 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX), 14555 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX), 14556 REGDEF(dspsc,0,DSPSC), 14557 14558 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX), 14559 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX), 14560 REGDEF(DSPSC,0,DSPSC), 14561 14562 /* iWMMXt data registers - p0, c0-15. */ 14563 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR), 14564 14565 /* iWMMXt control registers - p1, c0-3. */ 14566 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC), 14567 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC), 14568 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC), 14569 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC), 14570 14571 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */ 14572 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG), 14573 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG), 14574 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG), 14575 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG), 14576 14577 /* XScale accumulator registers. */ 14578 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE), 14579}; 14580#undef REGDEF 14581#undef REGNUM 14582#undef REGSET 14583 14584/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled 14585 within psr_required_here. */ 14586static const struct asm_psr psrs[] = 14587{ 14588 /* Backward compatibility notation. Note that "all" is no longer 14589 truly all possible PSR bits. */ 14590 {"all", PSR_c | PSR_f}, 14591 {"flg", PSR_f}, 14592 {"ctl", PSR_c}, 14593 14594 /* Individual flags. */ 14595 {"f", PSR_f}, 14596 {"c", PSR_c}, 14597 {"x", PSR_x}, 14598 {"s", PSR_s}, 14599 /* Combinations of flags. */ 14600 {"fs", PSR_f | PSR_s}, 14601 {"fx", PSR_f | PSR_x}, 14602 {"fc", PSR_f | PSR_c}, 14603 {"sf", PSR_s | PSR_f}, 14604 {"sx", PSR_s | PSR_x}, 14605 {"sc", PSR_s | PSR_c}, 14606 {"xf", PSR_x | PSR_f}, 14607 {"xs", PSR_x | PSR_s}, 14608 {"xc", PSR_x | PSR_c}, 14609 {"cf", PSR_c | PSR_f}, 14610 {"cs", PSR_c | PSR_s}, 14611 {"cx", PSR_c | PSR_x}, 14612 {"fsx", PSR_f | PSR_s | PSR_x}, 14613 {"fsc", PSR_f | PSR_s | PSR_c}, 14614 {"fxs", PSR_f | PSR_x | PSR_s}, 14615 {"fxc", PSR_f | PSR_x | PSR_c}, 14616 {"fcs", PSR_f | PSR_c | PSR_s}, 14617 {"fcx", PSR_f | PSR_c | PSR_x}, 14618 {"sfx", PSR_s | PSR_f | PSR_x}, 14619 {"sfc", PSR_s | PSR_f | PSR_c}, 14620 {"sxf", PSR_s | PSR_x | PSR_f}, 14621 {"sxc", PSR_s | PSR_x | PSR_c}, 14622 {"scf", PSR_s | PSR_c | PSR_f}, 14623 {"scx", PSR_s | PSR_c | PSR_x}, 14624 {"xfs", PSR_x | PSR_f | PSR_s}, 14625 {"xfc", PSR_x | PSR_f | PSR_c}, 14626 {"xsf", PSR_x | PSR_s | PSR_f}, 14627 {"xsc", PSR_x | PSR_s | PSR_c}, 14628 {"xcf", PSR_x | PSR_c | PSR_f}, 14629 {"xcs", PSR_x | PSR_c | PSR_s}, 14630 {"cfs", PSR_c | PSR_f | PSR_s}, 14631 {"cfx", PSR_c | PSR_f | PSR_x}, 14632 {"csf", PSR_c | PSR_s | PSR_f}, 14633 {"csx", PSR_c | PSR_s | PSR_x}, 14634 {"cxf", PSR_c | PSR_x | PSR_f}, 14635 {"cxs", PSR_c | PSR_x | PSR_s}, 14636 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c}, 14637 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x}, 14638 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c}, 14639 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s}, 14640 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x}, 14641 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s}, 14642 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c}, 14643 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x}, 14644 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c}, 14645 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f}, 14646 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x}, 14647 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f}, 14648 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c}, 14649 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s}, 14650 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c}, 14651 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f}, 14652 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s}, 14653 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f}, 14654 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x}, 14655 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s}, 14656 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x}, 14657 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f}, 14658 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s}, 14659 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f}, 14660}; 14661 14662/* Table of V7M psr names. */ 14663static const struct asm_psr v7m_psrs[] = 14664{ 14665 {"apsr", 0 }, {"APSR", 0 }, 14666 {"iapsr", 1 }, {"IAPSR", 1 }, 14667 {"eapsr", 2 }, {"EAPSR", 2 }, 14668 {"psr", 3 }, {"PSR", 3 }, 14669 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 }, 14670 {"ipsr", 5 }, {"IPSR", 5 }, 14671 {"epsr", 6 }, {"EPSR", 6 }, 14672 {"iepsr", 7 }, {"IEPSR", 7 }, 14673 {"msp", 8 }, {"MSP", 8 }, 14674 {"psp", 9 }, {"PSP", 9 }, 14675 {"primask", 16}, {"PRIMASK", 16}, 14676 {"basepri", 17}, {"BASEPRI", 17}, 14677 {"basepri_max", 18}, {"BASEPRI_MAX", 18}, 14678 {"faultmask", 19}, {"FAULTMASK", 19}, 14679 {"control", 20}, {"CONTROL", 20} 14680}; 14681 14682/* Table of all shift-in-operand names. */ 14683static const struct asm_shift_name shift_names [] = 14684{ 14685 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL }, 14686 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL }, 14687 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR }, 14688 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR }, 14689 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR }, 14690 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX } 14691}; 14692 14693/* Table of all explicit relocation names. */ 14694#ifdef OBJ_ELF 14695static struct reloc_entry reloc_names[] = 14696{ 14697 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 }, 14698 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF }, 14699 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 }, 14700 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 }, 14701 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 }, 14702 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 }, 14703 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32}, 14704 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32}, 14705 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32}, 14706 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32}, 14707 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32} 14708}; 14709#endif 14710 14711/* Table of all conditional affixes. 0xF is not defined as a condition code. */ 14712static const struct asm_cond conds[] = 14713{ 14714 {"eq", 0x0}, 14715 {"ne", 0x1}, 14716 {"cs", 0x2}, {"hs", 0x2}, 14717 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3}, 14718 {"mi", 0x4}, 14719 {"pl", 0x5}, 14720 {"vs", 0x6}, 14721 {"vc", 0x7}, 14722 {"hi", 0x8}, 14723 {"ls", 0x9}, 14724 {"ge", 0xa}, 14725 {"lt", 0xb}, 14726 {"gt", 0xc}, 14727 {"le", 0xd}, 14728 {"al", 0xe} 14729}; 14730 14731static struct asm_barrier_opt barrier_opt_names[] = 14732{ 14733 { "sy", 0xf }, 14734 { "un", 0x7 }, 14735 { "st", 0xe }, 14736 { "unst", 0x6 } 14737}; 14738 14739/* Table of ARM-format instructions. */ 14740 14741/* Macros for gluing together operand strings. N.B. In all cases 14742 other than OPS0, the trailing OP_stop comes from default 14743 zero-initialization of the unspecified elements of the array. */ 14744#define OPS0() { OP_stop, } 14745#define OPS1(a) { OP_##a, } 14746#define OPS2(a,b) { OP_##a,OP_##b, } 14747#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, } 14748#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, } 14749#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, } 14750#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, } 14751 14752/* These macros abstract out the exact format of the mnemonic table and 14753 save some repeated characters. */ 14754 14755/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */ 14756#define TxCE(mnem, op, top, nops, ops, ae, te) \ 14757 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \ 14758 THUMB_VARIANT, do_##ae, do_##te } 14759 14760/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for 14761 a T_MNEM_xyz enumerator. */ 14762#define TCE(mnem, aop, top, nops, ops, ae, te) \ 14763 TxCE(mnem, aop, 0x##top, nops, ops, ae, te) 14764#define tCE(mnem, aop, top, nops, ops, ae, te) \ 14765 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14766 14767/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional 14768 infix after the third character. */ 14769#define TxC3(mnem, op, top, nops, ops, ae, te) \ 14770 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \ 14771 THUMB_VARIANT, do_##ae, do_##te } 14772#define TxC3w(mnem, op, top, nops, ops, ae, te) \ 14773 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \ 14774 THUMB_VARIANT, do_##ae, do_##te } 14775#define TC3(mnem, aop, top, nops, ops, ae, te) \ 14776 TxC3(mnem, aop, 0x##top, nops, ops, ae, te) 14777#define TC3w(mnem, aop, top, nops, ops, ae, te) \ 14778 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te) 14779#define tC3(mnem, aop, top, nops, ops, ae, te) \ 14780 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14781#define tC3w(mnem, aop, top, nops, ops, ae, te) \ 14782 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te) 14783 14784/* Mnemonic with a conditional infix in an unusual place. Each and every variant has to 14785 appear in the condition table. */ 14786#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \ 14787 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14788 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te } 14789 14790#define TxCM(m1, m2, op, top, nops, ops, ae, te) \ 14791 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \ 14792 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \ 14793 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \ 14794 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \ 14795 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \ 14796 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \ 14797 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \ 14798 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \ 14799 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \ 14800 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \ 14801 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \ 14802 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \ 14803 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \ 14804 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \ 14805 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \ 14806 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \ 14807 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \ 14808 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \ 14809 TxCM_(m1, al, m2, op, top, nops, ops, ae, te) 14810 14811#define TCM(m1,m2, aop, top, nops, ops, ae, te) \ 14812 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te) 14813#define tCM(m1,m2, aop, top, nops, ops, ae, te) \ 14814 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te) 14815 14816/* Mnemonic that cannot be conditionalized. The ARM condition-code 14817 field is still 0xE. Many of the Thumb variants can be executed 14818 conditionally, so this is checked separately. */ 14819#define TUE(mnem, op, top, nops, ops, ae, te) \ 14820 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \ 14821 THUMB_VARIANT, do_##ae, do_##te } 14822 14823/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM 14824 condition code field. */ 14825#define TUF(mnem, op, top, nops, ops, ae, te) \ 14826 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \ 14827 THUMB_VARIANT, do_##ae, do_##te } 14828 14829/* ARM-only variants of all the above. */ 14830#define CE(mnem, op, nops, ops, ae) \ 14831 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14832 14833#define C3(mnem, op, nops, ops, ae) \ 14834 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14835 14836/* Legacy mnemonics that always have conditional infix after the third 14837 character. */ 14838#define CL(mnem, op, nops, ops, ae) \ 14839 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14840 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14841 14842/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */ 14843#define cCE(mnem, op, nops, ops, ae) \ 14844 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14845 14846/* Legacy coprocessor instructions where conditional infix and conditional 14847 suffix are ambiguous. For consistency this includes all FPA instructions, 14848 not just the potentially ambiguous ones. */ 14849#define cCL(mnem, op, nops, ops, ae) \ 14850 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \ 14851 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14852 14853/* Coprocessor, takes either a suffix or a position-3 infix 14854 (for an FPA corner case). */ 14855#define C3E(mnem, op, nops, ops, ae) \ 14856 { #mnem, OPS##nops ops, OT_csuf_or_in3, \ 14857 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae } 14858 14859#define xCM_(m1, m2, m3, op, nops, ops, ae) \ 14860 { #m1 #m2 #m3, OPS##nops ops, \ 14861 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \ 14862 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL } 14863 14864#define CM(m1, m2, op, nops, ops, ae) \ 14865 xCM_(m1, , m2, op, nops, ops, ae), \ 14866 xCM_(m1, eq, m2, op, nops, ops, ae), \ 14867 xCM_(m1, ne, m2, op, nops, ops, ae), \ 14868 xCM_(m1, cs, m2, op, nops, ops, ae), \ 14869 xCM_(m1, hs, m2, op, nops, ops, ae), \ 14870 xCM_(m1, cc, m2, op, nops, ops, ae), \ 14871 xCM_(m1, ul, m2, op, nops, ops, ae), \ 14872 xCM_(m1, lo, m2, op, nops, ops, ae), \ 14873 xCM_(m1, mi, m2, op, nops, ops, ae), \ 14874 xCM_(m1, pl, m2, op, nops, ops, ae), \ 14875 xCM_(m1, vs, m2, op, nops, ops, ae), \ 14876 xCM_(m1, vc, m2, op, nops, ops, ae), \ 14877 xCM_(m1, hi, m2, op, nops, ops, ae), \ 14878 xCM_(m1, ls, m2, op, nops, ops, ae), \ 14879 xCM_(m1, ge, m2, op, nops, ops, ae), \ 14880 xCM_(m1, lt, m2, op, nops, ops, ae), \ 14881 xCM_(m1, gt, m2, op, nops, ops, ae), \ 14882 xCM_(m1, le, m2, op, nops, ops, ae), \ 14883 xCM_(m1, al, m2, op, nops, ops, ae) 14884 14885#define UE(mnem, op, nops, ops, ae) \ 14886 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14887 14888#define UF(mnem, op, nops, ops, ae) \ 14889 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL } 14890 14891/* Neon data-processing. ARM versions are unconditional with cond=0xf. 14892 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we 14893 use the same encoding function for each. */ 14894#define NUF(mnem, op, nops, ops, enc) \ 14895 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \ 14896 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14897 14898/* Neon data processing, version which indirects through neon_enc_tab for 14899 the various overloaded versions of opcodes. */ 14900#define nUF(mnem, op, nops, ops, enc) \ 14901 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \ 14902 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14903 14904/* Neon insn with conditional suffix for the ARM version, non-overloaded 14905 version. */ 14906#define NCE_tag(mnem, op, nops, ops, enc, tag) \ 14907 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \ 14908 THUMB_VARIANT, do_##enc, do_##enc } 14909 14910#define NCE(mnem, op, nops, ops, enc) \ 14911 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14912 14913#define NCEF(mnem, op, nops, ops, enc) \ 14914 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14915 14916/* Neon insn with conditional suffix for the ARM version, overloaded types. */ 14917#define nCE_tag(mnem, op, nops, ops, enc, tag) \ 14918 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \ 14919 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc } 14920 14921#define nCE(mnem, op, nops, ops, enc) \ 14922 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix) 14923 14924#define nCEF(mnem, op, nops, ops, enc) \ 14925 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF) 14926 14927#define do_0 0 14928 14929/* Thumb-only, unconditional. */ 14930#define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te) 14931 14932static const struct asm_opcode insns[] = 14933{ 14934#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */ 14935#define THUMB_VARIANT &arm_ext_v4t 14936 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c), 14937 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c), 14938 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c), 14939 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c), 14940 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub), 14941 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub), 14942 tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub), 14943 tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub), 14944 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c), 14945 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c), 14946 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3), 14947 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3), 14948 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c), 14949 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c), 14950 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3), 14951 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3), 14952 14953 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism 14954 for setting PSR flag bits. They are obsolete in V6 and do not 14955 have Thumb equivalents. */ 14956 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14957 tC3w(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst), 14958 CL(tstp, 110f000, 2, (RR, SH), cmp), 14959 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14960 tC3w(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp), 14961 CL(cmpp, 150f000, 2, (RR, SH), cmp), 14962 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14963 tC3w(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst), 14964 CL(cmnp, 170f000, 2, (RR, SH), cmp), 14965 14966 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp), 14967 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp), 14968 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst), 14969 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst), 14970 14971 tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst), 14972 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14973 tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst), 14974 tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst), 14975 14976 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14977 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14978 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14979 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14980 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14981 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), 14982 14983 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), 14984 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi), 14985 tCE(b, a000000, b, 1, (EXPr), branch, t_branch), 14986 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23), 14987 14988 /* Pseudo ops. */ 14989 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr), 14990 C3(adrl, 28f0000, 2, (RR, EXP), adrl), 14991 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), 14992 14993 /* Thumb-compatibility pseudo ops. */ 14994 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), 14995 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift), 14996 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), 14997 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), 14998 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), 14999 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), 15000 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), 15001 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), 15002 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), 15003 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg), 15004 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop), 15005 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop), 15006 15007 /* These may simplify to neg. */ 15008 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb), 15009 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb), 15010 15011 TCE(rrx, 1a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rd_rm), 15012 TCE(rrxs, 1b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rd_rm), 15013 15014#undef THUMB_VARIANT 15015#define THUMB_VARIANT &arm_ext_v6 15016 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), 15017 15018 /* V1 instructions with no Thumb analogue prior to V6T2. */ 15019#undef THUMB_VARIANT 15020#define THUMB_VARIANT &arm_ext_v6t2 15021 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 15022 TC3w(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst), 15023 CL(teqp, 130f000, 2, (RR, SH), cmp), 15024 15025 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt), 15026 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt), 15027 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt), 15028 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt), 15029 15030 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15031 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15032 15033 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15034 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), 15035 15036 /* V1 instructions with no Thumb analogue at all. */ 15037 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit), 15038 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit), 15039 15040 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm), 15041 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm), 15042 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm), 15043 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm), 15044 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm), 15045 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm), 15046 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm), 15047 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm), 15048 15049#undef ARM_VARIANT 15050#define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */ 15051#undef THUMB_VARIANT 15052#define THUMB_VARIANT &arm_ext_v4t 15053 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 15054 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul), 15055 15056#undef THUMB_VARIANT 15057#define THUMB_VARIANT &arm_ext_v6t2 15058 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15059 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas), 15060 15061 /* Generic coprocessor instructions. */ 15062 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15063 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15064 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15065 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15066 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15067 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15068 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), 15069 15070#undef ARM_VARIANT 15071#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ 15072 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 15073 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn), 15074 15075#undef ARM_VARIANT 15076#define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */ 15077 TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs), 15078 TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr), 15079 15080#undef ARM_VARIANT 15081#define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */ 15082 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15083 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15084 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15085 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15086 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15087 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15088 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull), 15089 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull), 15090 15091#undef ARM_VARIANT 15092#define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */ 15093#undef THUMB_VARIANT 15094#define THUMB_VARIANT &arm_ext_v4t 15095 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15096 tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15097 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15098 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15099 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15100 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst), 15101 15102#undef ARM_VARIANT 15103#define ARM_VARIANT &arm_ext_v4t_5 15104 /* ARM Architecture 4T. */ 15105 /* Note: bx (and blx) are required on V5, even if the processor does 15106 not support Thumb. */ 15107 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx), 15108 15109#undef ARM_VARIANT 15110#define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */ 15111#undef THUMB_VARIANT 15112#define THUMB_VARIANT &arm_ext_v5t 15113 /* Note: blx has 2 variants; the .value coded here is for 15114 BLX(2). Only this variant has conditional execution. */ 15115 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx), 15116 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt), 15117 15118#undef THUMB_VARIANT 15119#define THUMB_VARIANT &arm_ext_v6t2 15120 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz), 15121 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15122 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15123 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15124 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), 15125 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), 15126 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), 15127 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), 15128 15129#undef ARM_VARIANT 15130#define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ 15131 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15132 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15133 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15134 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15135 15136 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15137 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla), 15138 15139 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15140 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15141 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15142 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal), 15143 15144 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15145 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15146 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15147 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15148 15149 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15150 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15151 15152 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15153 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15154 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15155 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn), 15156 15157#undef ARM_VARIANT 15158#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */ 15159 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld), 15160 TC3(ldrd, 00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15161 TC3(strd, 00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd), 15162 15163 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15164 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15165 15166#undef ARM_VARIANT 15167#define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */ 15168 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj), 15169 15170#undef ARM_VARIANT 15171#define ARM_VARIANT &arm_ext_v6 /* ARM V6. */ 15172#undef THUMB_VARIANT 15173#define THUMB_VARIANT &arm_ext_v6 15174 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi), 15175 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi), 15176 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15177 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15178 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev), 15179 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15180 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15181 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15182 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15183 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend), 15184 15185#undef THUMB_VARIANT 15186#define THUMB_VARIANT &arm_ext_v6t2 15187 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex), 15188 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex), 15189 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15190 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), 15191 15192 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat), 15193 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat), 15194 15195/* ARM V6 not included in V7M (eg. integer SIMD). */ 15196#undef THUMB_VARIANT 15197#define THUMB_VARIANT &arm_ext_v6_notm 15198 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps), 15199 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt), 15200 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb), 15201 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15202 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15203 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15204 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15205 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15206 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15207 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15208 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15209 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15210 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15211 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15212 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15213 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15214 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15215 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15216 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15217 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15218 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15219 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15220 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15221 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15222 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15223 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15224 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15225 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15226 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15227 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15228 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15229 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15230 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15231 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15232 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15233 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15234 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15235 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15236 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15237 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15238 UF(rfeib, 9900a00, 1, (RRw), rfe), 15239 UF(rfeda, 8100a00, 1, (RRw), rfe), 15240 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15241 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe), 15242 UF(rfefa, 9900a00, 1, (RRw), rfe), 15243 UF(rfeea, 8100a00, 1, (RRw), rfe), 15244 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe), 15245 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15246 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15247 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15248 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15249 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15250 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15251 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), 15252 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), 15253 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), 15254 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15255 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15256 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15257 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15258 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15259 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15260 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15261 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), 15262 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15263 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15264 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15265 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15266 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15267 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15268 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15269 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15270 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15271 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15272 TUF(srsia, 8c00500, e980c000, 2, (oRRw, I31w), srs, srs), 15273 UF(srsib, 9c00500, 2, (oRRw, I31w), srs), 15274 UF(srsda, 8400500, 2, (oRRw, I31w), srs), 15275 TUF(srsdb, 9400500, e800c000, 2, (oRRw, I31w), srs, srs), 15276 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16), 15277 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal), 15278 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), 15279 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), 15280 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16), 15281 15282#undef ARM_VARIANT 15283#define ARM_VARIANT &arm_ext_v6k 15284#undef THUMB_VARIANT 15285#define THUMB_VARIANT &arm_ext_v6k 15286 tCE(yield, 320f001, yield, 0, (), noargs, t_hint), 15287 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint), 15288 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint), 15289 tCE(sev, 320f004, sev, 0, (), noargs, t_hint), 15290 15291#undef THUMB_VARIANT 15292#define THUMB_VARIANT &arm_ext_v6_notm 15293 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd), 15294 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd), 15295 15296#undef THUMB_VARIANT 15297#define THUMB_VARIANT &arm_ext_v6t2 15298 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15299 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), 15300 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15301 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn), 15302 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs), 15303 15304#undef ARM_VARIANT 15305#define ARM_VARIANT &arm_ext_v6z 15306 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc), 15307 15308#undef ARM_VARIANT 15309#define ARM_VARIANT &arm_ext_v6t2 15310 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc), 15311 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi), 15312 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15313 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), 15314 15315 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), 15316 TCE(movw, 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), 15317 TCE(movt, 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), 15318 TCE(rbit, 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), 15319 15320 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15321 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15322 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15323 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt), 15324 15325 UT(cbnz, b900, 2, (RR, EXP), t_cbz), 15326 UT(cbz, b100, 2, (RR, EXP), t_cbz), 15327 /* ARM does not really have an IT instruction, so always allow it. */ 15328#undef ARM_VARIANT 15329#define ARM_VARIANT &arm_ext_v1 15330 TUE(it, 0, bf08, 1, (COND), it, t_it), 15331 TUE(itt, 0, bf0c, 1, (COND), it, t_it), 15332 TUE(ite, 0, bf04, 1, (COND), it, t_it), 15333 TUE(ittt, 0, bf0e, 1, (COND), it, t_it), 15334 TUE(itet, 0, bf06, 1, (COND), it, t_it), 15335 TUE(itte, 0, bf0a, 1, (COND), it, t_it), 15336 TUE(itee, 0, bf02, 1, (COND), it, t_it), 15337 TUE(itttt, 0, bf0f, 1, (COND), it, t_it), 15338 TUE(itett, 0, bf07, 1, (COND), it, t_it), 15339 TUE(ittet, 0, bf0b, 1, (COND), it, t_it), 15340 TUE(iteet, 0, bf03, 1, (COND), it, t_it), 15341 TUE(ittte, 0, bf0d, 1, (COND), it, t_it), 15342 TUE(itete, 0, bf05, 1, (COND), it, t_it), 15343 TUE(ittee, 0, bf09, 1, (COND), it, t_it), 15344 TUE(iteee, 0, bf01, 1, (COND), it, t_it), 15345 15346 /* Thumb2 only instructions. */ 15347#undef ARM_VARIANT 15348#define ARM_VARIANT NULL 15349 15350 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15351 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), 15352 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), 15353 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), 15354 15355 /* Thumb-2 hardware division instructions (R and M profiles only). */ 15356#undef THUMB_VARIANT 15357#define THUMB_VARIANT &arm_ext_div 15358 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div), 15359 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div), 15360 15361 /* ARM V7 instructions. */ 15362#undef ARM_VARIANT 15363#define ARM_VARIANT &arm_ext_v7 15364#undef THUMB_VARIANT 15365#define THUMB_VARIANT &arm_ext_v7 15366 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld), 15367 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg), 15368 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier), 15369 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier), 15370 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier), 15371 15372#undef ARM_VARIANT 15373#define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */ 15374 cCE(wfs, e200110, 1, (RR), rd), 15375 cCE(rfs, e300110, 1, (RR), rd), 15376 cCE(wfc, e400110, 1, (RR), rd), 15377 cCE(rfc, e500110, 1, (RR), rd), 15378 15379 cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr), 15380 cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr), 15381 cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr), 15382 cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr), 15383 15384 cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr), 15385 cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr), 15386 cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr), 15387 cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr), 15388 15389 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm), 15390 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm), 15391 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm), 15392 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm), 15393 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm), 15394 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm), 15395 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm), 15396 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm), 15397 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm), 15398 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm), 15399 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm), 15400 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm), 15401 15402 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm), 15403 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm), 15404 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm), 15405 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm), 15406 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm), 15407 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm), 15408 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm), 15409 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm), 15410 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm), 15411 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm), 15412 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm), 15413 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm), 15414 15415 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm), 15416 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm), 15417 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm), 15418 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm), 15419 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm), 15420 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm), 15421 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm), 15422 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm), 15423 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm), 15424 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm), 15425 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm), 15426 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm), 15427 15428 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm), 15429 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm), 15430 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm), 15431 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm), 15432 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm), 15433 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm), 15434 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm), 15435 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm), 15436 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm), 15437 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm), 15438 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm), 15439 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm), 15440 15441 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm), 15442 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm), 15443 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm), 15444 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm), 15445 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm), 15446 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm), 15447 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm), 15448 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm), 15449 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm), 15450 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm), 15451 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm), 15452 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm), 15453 15454 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm), 15455 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm), 15456 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm), 15457 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm), 15458 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm), 15459 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm), 15460 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm), 15461 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm), 15462 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm), 15463 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm), 15464 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm), 15465 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm), 15466 15467 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm), 15468 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm), 15469 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm), 15470 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm), 15471 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm), 15472 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm), 15473 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm), 15474 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm), 15475 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm), 15476 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm), 15477 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm), 15478 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm), 15479 15480 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm), 15481 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm), 15482 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm), 15483 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm), 15484 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm), 15485 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm), 15486 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm), 15487 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm), 15488 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm), 15489 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm), 15490 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm), 15491 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm), 15492 15493 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm), 15494 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm), 15495 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm), 15496 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm), 15497 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm), 15498 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm), 15499 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm), 15500 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm), 15501 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm), 15502 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm), 15503 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm), 15504 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm), 15505 15506 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm), 15507 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm), 15508 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm), 15509 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm), 15510 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm), 15511 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm), 15512 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm), 15513 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm), 15514 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm), 15515 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm), 15516 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm), 15517 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm), 15518 15519 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm), 15520 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm), 15521 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm), 15522 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm), 15523 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm), 15524 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm), 15525 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm), 15526 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm), 15527 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm), 15528 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm), 15529 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm), 15530 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm), 15531 15532 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm), 15533 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm), 15534 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm), 15535 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm), 15536 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm), 15537 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm), 15538 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm), 15539 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm), 15540 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm), 15541 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm), 15542 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm), 15543 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm), 15544 15545 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm), 15546 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm), 15547 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm), 15548 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm), 15549 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm), 15550 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm), 15551 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm), 15552 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm), 15553 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm), 15554 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm), 15555 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm), 15556 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm), 15557 15558 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm), 15559 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm), 15560 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm), 15561 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm), 15562 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm), 15563 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm), 15564 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm), 15565 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm), 15566 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm), 15567 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm), 15568 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm), 15569 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm), 15570 15571 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm), 15572 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm), 15573 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm), 15574 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm), 15575 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm), 15576 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm), 15577 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm), 15578 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm), 15579 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm), 15580 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm), 15581 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm), 15582 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm), 15583 15584 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm), 15585 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm), 15586 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm), 15587 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm), 15588 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm), 15589 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm), 15590 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm), 15591 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm), 15592 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm), 15593 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm), 15594 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm), 15595 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm), 15596 15597 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm), 15598 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm), 15599 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm), 15600 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm), 15601 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm), 15602 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15603 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15604 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15605 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm), 15606 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm), 15607 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm), 15608 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm), 15609 15610 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm), 15611 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm), 15612 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm), 15613 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm), 15614 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm), 15615 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15616 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15617 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15618 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm), 15619 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm), 15620 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm), 15621 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm), 15622 15623 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm), 15624 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm), 15625 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm), 15626 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm), 15627 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm), 15628 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15629 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15630 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15631 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm), 15632 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm), 15633 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm), 15634 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm), 15635 15636 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm), 15637 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm), 15638 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm), 15639 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm), 15640 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm), 15641 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15642 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15643 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15644 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm), 15645 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm), 15646 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm), 15647 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm), 15648 15649 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm), 15650 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm), 15651 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm), 15652 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm), 15653 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm), 15654 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15655 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15656 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15657 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm), 15658 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm), 15659 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm), 15660 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm), 15661 15662 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm), 15663 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm), 15664 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm), 15665 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm), 15666 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm), 15667 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15668 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15669 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15670 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm), 15671 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm), 15672 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm), 15673 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm), 15674 15675 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm), 15676 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm), 15677 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm), 15678 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm), 15679 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm), 15680 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15681 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15682 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15683 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm), 15684 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm), 15685 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm), 15686 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm), 15687 15688 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm), 15689 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm), 15690 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm), 15691 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm), 15692 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm), 15693 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15694 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15695 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15696 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm), 15697 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm), 15698 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm), 15699 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm), 15700 15701 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm), 15702 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm), 15703 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm), 15704 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm), 15705 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm), 15706 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15707 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15708 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15709 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm), 15710 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm), 15711 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm), 15712 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm), 15713 15714 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm), 15715 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm), 15716 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm), 15717 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm), 15718 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm), 15719 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15720 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15721 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15722 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm), 15723 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm), 15724 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm), 15725 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm), 15726 15727 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15728 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15729 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15730 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15731 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15732 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15733 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15734 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15735 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15736 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15737 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15738 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15739 15740 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15741 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15742 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15743 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15744 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15745 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15746 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15747 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15748 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15749 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15750 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15751 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15752 15753 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm), 15754 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm), 15755 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm), 15756 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm), 15757 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm), 15758 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm), 15759 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm), 15760 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm), 15761 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm), 15762 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm), 15763 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm), 15764 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm), 15765 15766 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp), 15767 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp), 15768 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp), 15769 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp), 15770 15771 cCL(flts, e000110, 2, (RF, RR), rn_rd), 15772 cCL(fltsp, e000130, 2, (RF, RR), rn_rd), 15773 cCL(fltsm, e000150, 2, (RF, RR), rn_rd), 15774 cCL(fltsz, e000170, 2, (RF, RR), rn_rd), 15775 cCL(fltd, e000190, 2, (RF, RR), rn_rd), 15776 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd), 15777 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd), 15778 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd), 15779 cCL(flte, e080110, 2, (RF, RR), rn_rd), 15780 cCL(fltep, e080130, 2, (RF, RR), rn_rd), 15781 cCL(fltem, e080150, 2, (RF, RR), rn_rd), 15782 cCL(fltez, e080170, 2, (RF, RR), rn_rd), 15783 15784 /* The implementation of the FIX instruction is broken on some 15785 assemblers, in that it accepts a precision specifier as well as a 15786 rounding specifier, despite the fact that this is meaningless. 15787 To be more compatible, we accept it as well, though of course it 15788 does not set any bits. */ 15789 cCE(fix, e100110, 2, (RR, RF), rd_rm), 15790 cCL(fixp, e100130, 2, (RR, RF), rd_rm), 15791 cCL(fixm, e100150, 2, (RR, RF), rd_rm), 15792 cCL(fixz, e100170, 2, (RR, RF), rd_rm), 15793 cCL(fixsp, e100130, 2, (RR, RF), rd_rm), 15794 cCL(fixsm, e100150, 2, (RR, RF), rd_rm), 15795 cCL(fixsz, e100170, 2, (RR, RF), rd_rm), 15796 cCL(fixdp, e100130, 2, (RR, RF), rd_rm), 15797 cCL(fixdm, e100150, 2, (RR, RF), rd_rm), 15798 cCL(fixdz, e100170, 2, (RR, RF), rd_rm), 15799 cCL(fixep, e100130, 2, (RR, RF), rd_rm), 15800 cCL(fixem, e100150, 2, (RR, RF), rd_rm), 15801 cCL(fixez, e100170, 2, (RR, RF), rd_rm), 15802 15803 /* Instructions that were new with the real FPA, call them V2. */ 15804#undef ARM_VARIANT 15805#define ARM_VARIANT &fpu_fpa_ext_v2 15806 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15807 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15808 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15809 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15810 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15811 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm), 15812 15813#undef ARM_VARIANT 15814#define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */ 15815 /* Moves and type conversions. */ 15816 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic), 15817 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp), 15818 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg), 15819 cCE(fmstat, ef1fa10, 0, (), noargs), 15820 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic), 15821 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic), 15822 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic), 15823 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15824 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic), 15825 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic), 15826 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn), 15827 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd), 15828 cCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vfp_vmrs), 15829 cCE(vmsr, ee00a10, 2, (RVC, RR), vfp_vmsr), 15830 15831 /* Memory operations. */ 15832 cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15833 cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst), 15834 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15835 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15836 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15837 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15838 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15839 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15840 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15841 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15842 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15843 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia), 15844 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15845 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb), 15846 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15847 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia), 15848 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15849 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb), 15850 15851 /* Monadic operations. */ 15852 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic), 15853 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic), 15854 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic), 15855 15856 /* Dyadic operations. */ 15857 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15858 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15859 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15860 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15861 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15862 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15863 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15864 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15865 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic), 15866 15867 /* Comparisons. */ 15868 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic), 15869 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z), 15870 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic), 15871 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z), 15872 15873#undef ARM_VARIANT 15874#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */ 15875 /* Moves and type conversions. */ 15876 cCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15877 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15878 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15879 cCE(fmdhr, e200b10, 2, (RVD, RR), vfp_dp_rn_rd), 15880 cCE(fmdlr, e000b10, 2, (RVD, RR), vfp_dp_rn_rd), 15881 cCE(fmrdh, e300b10, 2, (RR, RVD), vfp_dp_rd_rn), 15882 cCE(fmrdl, e100b10, 2, (RR, RVD), vfp_dp_rd_rn), 15883 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt), 15884 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt), 15885 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15886 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15887 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt), 15888 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt), 15889 15890 /* Memory operations. */ 15891 cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15892 cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst), 15893 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15894 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15895 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15896 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15897 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15898 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia), 15899 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15900 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb), 15901 15902 /* Monadic operations. */ 15903 cCE(fabsd, eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15904 cCE(fnegd, eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15905 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15906 15907 /* Dyadic operations. */ 15908 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15909 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15910 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15911 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15912 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15913 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15914 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15915 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15916 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm), 15917 15918 /* Comparisons. */ 15919 cCE(fcmpd, eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm), 15920 cCE(fcmpzd, eb50b40, 1, (RVD), vfp_dp_rd), 15921 cCE(fcmped, eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm), 15922 cCE(fcmpezd, eb50bc0, 1, (RVD), vfp_dp_rd), 15923 15924#undef ARM_VARIANT 15925#define ARM_VARIANT &fpu_vfp_ext_v2 15926 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2), 15927 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2), 15928 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn), 15929 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm), 15930 15931/* Instructions which may belong to either the Neon or VFP instruction sets. 15932 Individual encoder functions perform additional architecture checks. */ 15933#undef ARM_VARIANT 15934#define ARM_VARIANT &fpu_vfp_ext_v1xd 15935#undef THUMB_VARIANT 15936#define THUMB_VARIANT &fpu_vfp_ext_v1xd 15937 /* These mnemonics are unique to VFP. */ 15938 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt), 15939 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div), 15940 nCE(vnmul, vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15941 nCE(vnmla, vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15942 nCE(vnmls, vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul), 15943 nCE(vcmp, vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15944 nCE(vcmpe, vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp), 15945 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push), 15946 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop), 15947 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz), 15948 15949 /* Mnemonics shared by Neon and VFP. */ 15950 nCEF(vmul, vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul), 15951 nCEF(vmla, vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15952 nCEF(vmls, vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar), 15953 15954 nCEF(vadd, vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15955 nCEF(vsub, vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i), 15956 15957 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15958 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg), 15959 15960 NCE(vldm, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15961 NCE(vldmia, c900b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15962 NCE(vldmdb, d100b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15963 NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15964 NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15965 NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm), 15966 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15967 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), 15968 15969 nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), 15970 15971 /* NOTE: All VMOV encoding is special-cased! */ 15972 NCE(vmov, 0, 1, (VMOV), neon_mov), 15973 NCE(vmovq, 0, 1, (VMOV), neon_mov), 15974 15975#undef THUMB_VARIANT 15976#define THUMB_VARIANT &fpu_neon_ext_v1 15977#undef ARM_VARIANT 15978#define ARM_VARIANT &fpu_neon_ext_v1 15979 /* Data processing with three registers of the same length. */ 15980 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */ 15981 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su), 15982 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su), 15983 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15984 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15985 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15986 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15987 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su), 15988 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su), 15989 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */ 15990 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 15991 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 15992 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su), 15993 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su), 15994 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 15995 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl), 15996 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl), 15997 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl), 15998 /* If not immediate, fall back to neon_dyadic_i64_su. 15999 shl_imm should accept I8 I16 I32 I64, 16000 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */ 16001 nUF(vshl, vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm), 16002 nUF(vshlq, vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm), 16003 nUF(vqshl, vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm), 16004 nUF(vqshlq, vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm), 16005 /* Logic ops, types optional & ignored. */ 16006 nUF(vand, vand, 2, (RNDQ, NILO), neon_logic), 16007 nUF(vandq, vand, 2, (RNQ, NILO), neon_logic), 16008 nUF(vbic, vbic, 2, (RNDQ, NILO), neon_logic), 16009 nUF(vbicq, vbic, 2, (RNQ, NILO), neon_logic), 16010 nUF(vorr, vorr, 2, (RNDQ, NILO), neon_logic), 16011 nUF(vorrq, vorr, 2, (RNQ, NILO), neon_logic), 16012 nUF(vorn, vorn, 2, (RNDQ, NILO), neon_logic), 16013 nUF(vornq, vorn, 2, (RNQ, NILO), neon_logic), 16014 nUF(veor, veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic), 16015 nUF(veorq, veor, 3, (RNQ, oRNQ, RNQ), neon_logic), 16016 /* Bitfield ops, untyped. */ 16017 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 16018 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 16019 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 16020 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 16021 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield), 16022 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield), 16023 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */ 16024 nUF(vabd, vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 16025 nUF(vabdq, vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 16026 nUF(vmax, vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 16027 nUF(vmaxq, vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 16028 nUF(vmin, vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su), 16029 nUF(vminq, vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su), 16030 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall 16031 back to neon_dyadic_if_su. */ 16032 nUF(vcge, vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 16033 nUF(vcgeq, vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 16034 nUF(vcgt, vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp), 16035 nUF(vcgtq, vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp), 16036 nUF(vclt, vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 16037 nUF(vcltq, vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 16038 nUF(vcle, vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv), 16039 nUF(vcleq, vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv), 16040 /* Comparison. Type I8 I16 I32 F32. */ 16041 nUF(vceq, vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq), 16042 nUF(vceqq, vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq), 16043 /* As above, D registers only. */ 16044 nUF(vpmax, vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 16045 nUF(vpmin, vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d), 16046 /* Int and float variants, signedness unimportant. */ 16047 nUF(vmlaq, vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 16048 nUF(vmlsq, vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar), 16049 nUF(vpadd, vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d), 16050 /* Add/sub take types I8 I16 I32 I64 F32. */ 16051 nUF(vaddq, vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 16052 nUF(vsubq, vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i), 16053 /* vtst takes sizes 8, 16, 32. */ 16054 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst), 16055 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst), 16056 /* VMUL takes I8 I16 I32 F32 P8. */ 16057 nUF(vmulq, vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul), 16058 /* VQD{R}MULH takes S16 S32. */ 16059 nUF(vqdmulh, vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 16060 nUF(vqdmulhq, vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 16061 nUF(vqrdmulh, vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh), 16062 nUF(vqrdmulhq, vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh), 16063 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 16064 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 16065 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute), 16066 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute), 16067 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 16068 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 16069 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv), 16070 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv), 16071 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 16072 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step), 16073 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step), 16074 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step), 16075 16076 /* Two address, int/float. Types S8 S16 S32 F32. */ 16077 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg), 16078 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg), 16079 16080 /* Data processing with two registers and a shift amount. */ 16081 /* Right shifts, and variants with rounding. 16082 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */ 16083 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 16084 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 16085 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm), 16086 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm), 16087 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16088 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16089 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm), 16090 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm), 16091 /* Shift and insert. Sizes accepted 8 16 32 64. */ 16092 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli), 16093 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli), 16094 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri), 16095 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri), 16096 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */ 16097 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm), 16098 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm), 16099 /* Right shift immediate, saturating & narrowing, with rounding variants. 16100 Types accepted S16 S32 S64 U16 U32 U64. */ 16101 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 16102 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow), 16103 /* As above, unsigned. Types accepted S16 S32 S64. */ 16104 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 16105 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u), 16106 /* Right shift narrowing. Types accepted I16 I32 I64. */ 16107 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow), 16108 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow), 16109 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */ 16110 nUF(vshll, vshll, 3, (RNQ, RND, I32), neon_shll), 16111 /* CVT with optional immediate for fixed-point variant. */ 16112 nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt), 16113 16114 nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn), 16115 nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn), 16116 16117 /* Data processing, three registers of different lengths. */ 16118 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */ 16119 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal), 16120 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long), 16121 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long), 16122 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long), 16123 /* If not scalar, fall back to neon_dyadic_long. 16124 Vector types as above, scalar types S16 S32 U16 U32. */ 16125 nUF(vmlal, vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16126 nUF(vmlsl, vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long), 16127 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */ 16128 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16129 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide), 16130 /* Dyadic, narrowing insns. Types I16 I32 I64. */ 16131 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16132 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16133 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16134 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow), 16135 /* Saturating doubling multiplies. Types S16 S32. */ 16136 nUF(vqdmlal, vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16137 nUF(vqdmlsl, vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16138 nUF(vqdmull, vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long), 16139 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types 16140 S16 S32 U16 U32. */ 16141 nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), 16142 16143 /* Extract. Size 8. */ 16144 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext), 16145 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext), 16146 16147 /* Two registers, miscellaneous. */ 16148 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */ 16149 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev), 16150 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev), 16151 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev), 16152 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev), 16153 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev), 16154 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev), 16155 /* Vector replicate. Sizes 8 16 32. */ 16156 nCE(vdup, vdup, 2, (RNDQ, RR_RNSC), neon_dup), 16157 nCE(vdupq, vdup, 2, (RNQ, RR_RNSC), neon_dup), 16158 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */ 16159 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl), 16160 /* VMOVN. Types I16 I32 I64. */ 16161 nUF(vmovn, vmovn, 2, (RND, RNQ), neon_movn), 16162 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */ 16163 nUF(vqmovn, vqmovn, 2, (RND, RNQ), neon_qmovn), 16164 /* VQMOVUN. Types S16 S32 S64. */ 16165 nUF(vqmovun, vqmovun, 2, (RND, RNQ), neon_qmovun), 16166 /* VZIP / VUZP. Sizes 8 16 32. */ 16167 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp), 16168 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp), 16169 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp), 16170 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp), 16171 /* VQABS / VQNEG. Types S8 S16 S32. */ 16172 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16173 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg), 16174 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg), 16175 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg), 16176 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */ 16177 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long), 16178 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long), 16179 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long), 16180 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long), 16181 /* Reciprocal estimates. Types U32 F32. */ 16182 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est), 16183 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est), 16184 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est), 16185 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est), 16186 /* VCLS. Types S8 S16 S32. */ 16187 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls), 16188 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls), 16189 /* VCLZ. Types I8 I16 I32. */ 16190 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz), 16191 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz), 16192 /* VCNT. Size 8. */ 16193 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt), 16194 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt), 16195 /* Two address, untyped. */ 16196 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp), 16197 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp), 16198 /* VTRN. Sizes 8 16 32. */ 16199 nUF(vtrn, vtrn, 2, (RNDQ, RNDQ), neon_trn), 16200 nUF(vtrnq, vtrn, 2, (RNQ, RNQ), neon_trn), 16201 16202 /* Table lookup. Size 8. */ 16203 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16204 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx), 16205 16206#undef THUMB_VARIANT 16207#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext 16208#undef ARM_VARIANT 16209#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext 16210 /* Neon element/structure load/store. */ 16211 nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16212 nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx), 16213 nUF(vld2, vld2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16214 nUF(vst2, vst2, 2, (NSTRLST, ADDR), neon_ldx_stx), 16215 nUF(vld3, vld3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16216 nUF(vst3, vst3, 2, (NSTRLST, ADDR), neon_ldx_stx), 16217 nUF(vld4, vld4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16218 nUF(vst4, vst4, 2, (NSTRLST, ADDR), neon_ldx_stx), 16219 16220#undef THUMB_VARIANT 16221#define THUMB_VARIANT &fpu_vfp_ext_v3 16222#undef ARM_VARIANT 16223#define ARM_VARIANT &fpu_vfp_ext_v3 16224 cCE(fconsts, eb00a00, 2, (RVS, I255), vfp_sp_const), 16225 cCE(fconstd, eb00b00, 2, (RVD, I255), vfp_dp_const), 16226 cCE(fshtos, eba0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16227 cCE(fshtod, eba0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16228 cCE(fsltos, eba0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16229 cCE(fsltod, eba0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16230 cCE(fuhtos, ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16231 cCE(fuhtod, ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16232 cCE(fultos, ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16233 cCE(fultod, ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16234 cCE(ftoshs, ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16235 cCE(ftoshd, ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16236 cCE(ftosls, ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16237 cCE(ftosld, ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16238 cCE(ftouhs, ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16), 16239 cCE(ftouhd, ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16), 16240 cCE(ftouls, ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32), 16241 cCE(ftould, ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32), 16242 16243#undef THUMB_VARIANT 16244#undef ARM_VARIANT 16245#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */ 16246 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16247 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16248 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16249 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16250 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16251 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia), 16252 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar), 16253 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra), 16254 16255#undef ARM_VARIANT 16256#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */ 16257 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc), 16258 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc), 16259 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc), 16260 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd), 16261 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd), 16262 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd), 16263 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc), 16264 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc), 16265 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc), 16266 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16267 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16268 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm), 16269 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16270 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16271 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm), 16272 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16273 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16274 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr), 16275 cCE(tmcr, e000110, 2, (RIWC_RIWG, RR), rn_rd), 16276 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn), 16277 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16278 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16279 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16280 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16281 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16282 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia), 16283 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn), 16284 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn), 16285 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn), 16286 cCE(tmrc, e100110, 2, (RR, RIWC_RIWG), rd_rn), 16287 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm), 16288 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc), 16289 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc), 16290 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc), 16291 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn), 16292 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn), 16293 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn), 16294 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16295 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16296 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16297 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16298 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16299 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16300 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16301 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16302 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16303 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni), 16304 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16305 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16306 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16307 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16308 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16309 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16310 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16311 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16312 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16313 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16314 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16315 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16316 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16317 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16318 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16319 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16320 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16321 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16322 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16323 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16324 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16325 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16326 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16327 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16328 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16329 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16330 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16331 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16332 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16333 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16334 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16335 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16336 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16337 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16338 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16339 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16340 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16341 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16342 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16343 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16344 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16345 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov), 16346 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16347 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16348 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16349 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16350 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16351 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16352 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16353 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16354 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16355 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16356 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16357 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16358 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16359 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16360 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16361 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16362 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16363 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16364 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16365 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16366 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16367 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh), 16368 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16369 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16370 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16371 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16372 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16373 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16374 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16375 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16376 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16377 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16378 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16379 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16380 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16381 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16382 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16383 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16384 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5), 16385 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm), 16386 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16387 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh), 16388 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw), 16389 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd), 16390 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16391 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16392 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16393 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16394 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16395 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16396 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16397 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16398 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16399 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn), 16400 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn), 16401 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn), 16402 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn), 16403 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn), 16404 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn), 16405 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16406 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16407 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16408 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn), 16409 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn), 16410 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn), 16411 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn), 16412 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn), 16413 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn), 16414 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16415 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16416 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16417 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16418 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero), 16419 16420#undef ARM_VARIANT 16421#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */ 16422 cCE(torvscb, e13f190, 1, (RR), iwmmxt_tandorc), 16423 cCE(torvsch, e53f190, 1, (RR), iwmmxt_tandorc), 16424 cCE(torvscw, e93f190, 1, (RR), iwmmxt_tandorc), 16425 cCE(wabsb, e2001c0, 2, (RIWR, RIWR), rd_rn), 16426 cCE(wabsh, e6001c0, 2, (RIWR, RIWR), rd_rn), 16427 cCE(wabsw, ea001c0, 2, (RIWR, RIWR), rd_rn), 16428 cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16429 cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16430 cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16431 cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16432 cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16433 cCE(waddhc, e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16434 cCE(waddwc, ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16435 cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16436 cCE(wavg4, e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16437 cCE(wavg4r, e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16438 cCE(wmaddsn, ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16439 cCE(wmaddsx, eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16440 cCE(wmaddun, ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16441 cCE(wmaddux, e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16442 cCE(wmerge, e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge), 16443 cCE(wmiabb, e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16444 cCE(wmiabt, e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16445 cCE(wmiatb, e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16446 cCE(wmiatt, e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16447 cCE(wmiabbn, e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16448 cCE(wmiabtn, e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16449 cCE(wmiatbn, e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16450 cCE(wmiattn, e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16451 cCE(wmiawbb, e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16452 cCE(wmiawbt, e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16453 cCE(wmiawtb, ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16454 cCE(wmiawtt, eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16455 cCE(wmiawbbn, ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16456 cCE(wmiawbtn, ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16457 cCE(wmiawtbn, ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16458 cCE(wmiawttn, ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16459 cCE(wmulsmr, ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16460 cCE(wmulumr, ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16461 cCE(wmulwumr, ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16462 cCE(wmulwsmr, ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16463 cCE(wmulwum, ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16464 cCE(wmulwsm, ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16465 cCE(wmulwl, eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16466 cCE(wqmiabb, e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16467 cCE(wqmiabt, e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16468 cCE(wqmiatb, ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16469 cCE(wqmiatt, eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16470 cCE(wqmiabbn, ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16471 cCE(wqmiabtn, ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16472 cCE(wqmiatbn, ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16473 cCE(wqmiattn, ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16474 cCE(wqmulm, e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16475 cCE(wqmulmr, e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16476 cCE(wqmulwm, ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16477 cCE(wqmulwmr, ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16478 cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm), 16479 16480#undef ARM_VARIANT 16481#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */ 16482 cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16483 cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16484 cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16485 cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16486 cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr), 16487 cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr), 16488 cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr), 16489 cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr), 16490 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd), 16491 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn), 16492 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd), 16493 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn), 16494 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd), 16495 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn), 16496 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd), 16497 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn), 16498 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd), 16499 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn), 16500 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn), 16501 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn), 16502 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn), 16503 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn), 16504 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn), 16505 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn), 16506 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn), 16507 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn), 16508 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn), 16509 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn), 16510 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc), 16511 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd), 16512 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn), 16513 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn), 16514 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn), 16515 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn), 16516 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn), 16517 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn), 16518 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn), 16519 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn), 16520 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn), 16521 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn), 16522 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn), 16523 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn), 16524 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple), 16525 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple), 16526 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift), 16527 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift), 16528 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm), 16529 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm), 16530 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm), 16531 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm), 16532 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn), 16533 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn), 16534 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn), 16535 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn), 16536 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm), 16537 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm), 16538 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm), 16539 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm), 16540 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm), 16541 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm), 16542 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn), 16543 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn), 16544 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn), 16545 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn), 16546 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16547 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16548 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16549 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16550 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16551 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm), 16552 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16553 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm), 16554 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16555 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad), 16556 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16557 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad), 16558}; 16559#undef ARM_VARIANT 16560#undef THUMB_VARIANT 16561#undef TCE 16562#undef TCM 16563#undef TUE 16564#undef TUF 16565#undef TCC 16566#undef cCE 16567#undef cCL 16568#undef C3E 16569#undef CE 16570#undef CM 16571#undef UE 16572#undef UF 16573#undef UT 16574#undef NUF 16575#undef nUF 16576#undef NCE 16577#undef nCE 16578#undef OPS0 16579#undef OPS1 16580#undef OPS2 16581#undef OPS3 16582#undef OPS4 16583#undef OPS5 16584#undef OPS6 16585#undef do_0 16586 16587/* MD interface: bits in the object file. */ 16588 16589/* Turn an integer of n bytes (in val) into a stream of bytes appropriate 16590 for use in the a.out file, and stores them in the array pointed to by buf. 16591 This knows about the endian-ness of the target machine and does 16592 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) 16593 2 (short) and 4 (long) Floating numbers are put out as a series of 16594 LITTLENUMS (shorts, here at least). */ 16595 16596void 16597md_number_to_chars (char * buf, valueT val, int n) 16598{ 16599 if (target_big_endian) 16600 number_to_chars_bigendian (buf, val, n); 16601 else 16602 number_to_chars_littleendian (buf, val, n); 16603} 16604 16605static valueT 16606md_chars_to_number (char * buf, int n) 16607{ 16608 valueT result = 0; 16609 unsigned char * where = (unsigned char *) buf; 16610 16611 if (target_big_endian) 16612 { 16613 while (n--) 16614 { 16615 result <<= 8; 16616 result |= (*where++ & 255); 16617 } 16618 } 16619 else 16620 { 16621 while (n--) 16622 { 16623 result <<= 8; 16624 result |= (where[n] & 255); 16625 } 16626 } 16627 16628 return result; 16629} 16630 16631/* MD interface: Sections. */ 16632 16633/* Estimate the size of a frag before relaxing. Assume everything fits in 16634 2 bytes. */ 16635 16636int 16637md_estimate_size_before_relax (fragS * fragp, 16638 segT segtype ATTRIBUTE_UNUSED) 16639{ 16640 fragp->fr_var = 2; 16641 return 2; 16642} 16643 16644/* Convert a machine dependent frag. */ 16645 16646void 16647md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp) 16648{ 16649 unsigned long insn; 16650 unsigned long old_op; 16651 char *buf; 16652 expressionS exp; 16653 fixS *fixp; 16654 int reloc_type; 16655 int pc_rel; 16656 int opcode; 16657 16658 buf = fragp->fr_literal + fragp->fr_fix; 16659 16660 old_op = bfd_get_16(abfd, buf); 16661 if (fragp->fr_symbol) { 16662 exp.X_op = O_symbol; 16663 exp.X_add_symbol = fragp->fr_symbol; 16664 } else { 16665 exp.X_op = O_constant; 16666 } 16667 exp.X_add_number = fragp->fr_offset; 16668 opcode = fragp->fr_subtype; 16669 switch (opcode) 16670 { 16671 case T_MNEM_ldr_pc: 16672 case T_MNEM_ldr_pc2: 16673 case T_MNEM_ldr_sp: 16674 case T_MNEM_str_sp: 16675 case T_MNEM_ldr: 16676 case T_MNEM_ldrb: 16677 case T_MNEM_ldrh: 16678 case T_MNEM_str: 16679 case T_MNEM_strb: 16680 case T_MNEM_strh: 16681 if (fragp->fr_var == 4) 16682 { 16683 insn = THUMB_OP32(opcode); 16684 if ((old_op >> 12) == 4 || (old_op >> 12) == 9) 16685 { 16686 insn |= (old_op & 0x700) << 4; 16687 } 16688 else 16689 { 16690 insn |= (old_op & 7) << 12; 16691 insn |= (old_op & 0x38) << 13; 16692 } 16693 insn |= 0x00000c00; 16694 put_thumb32_insn (buf, insn); 16695 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM; 16696 } 16697 else 16698 { 16699 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET; 16700 } 16701 pc_rel = (opcode == T_MNEM_ldr_pc2); 16702 break; 16703 case T_MNEM_adr: 16704 if (fragp->fr_var == 4) 16705 { 16706 insn = THUMB_OP32 (opcode); 16707 insn |= (old_op & 0xf0) << 4; 16708 put_thumb32_insn (buf, insn); 16709 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12; 16710 } 16711 else 16712 { 16713 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16714 exp.X_add_number -= 4; 16715 } 16716 pc_rel = 1; 16717 break; 16718 case T_MNEM_mov: 16719 case T_MNEM_movs: 16720 case T_MNEM_cmp: 16721 case T_MNEM_cmn: 16722 if (fragp->fr_var == 4) 16723 { 16724 int r0off = (opcode == T_MNEM_mov 16725 || opcode == T_MNEM_movs) ? 0 : 8; 16726 insn = THUMB_OP32 (opcode); 16727 insn = (insn & 0xe1ffffff) | 0x10000000; 16728 insn |= (old_op & 0x700) << r0off; 16729 put_thumb32_insn (buf, insn); 16730 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16731 } 16732 else 16733 { 16734 reloc_type = BFD_RELOC_ARM_THUMB_IMM; 16735 } 16736 pc_rel = 0; 16737 break; 16738 case T_MNEM_b: 16739 if (fragp->fr_var == 4) 16740 { 16741 insn = THUMB_OP32(opcode); 16742 put_thumb32_insn (buf, insn); 16743 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25; 16744 } 16745 else 16746 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12; 16747 pc_rel = 1; 16748 break; 16749 case T_MNEM_bcond: 16750 if (fragp->fr_var == 4) 16751 { 16752 insn = THUMB_OP32(opcode); 16753 insn |= (old_op & 0xf00) << 14; 16754 put_thumb32_insn (buf, insn); 16755 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20; 16756 } 16757 else 16758 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9; 16759 pc_rel = 1; 16760 break; 16761 case T_MNEM_add_sp: 16762 case T_MNEM_add_pc: 16763 case T_MNEM_inc_sp: 16764 case T_MNEM_dec_sp: 16765 if (fragp->fr_var == 4) 16766 { 16767 /* ??? Choose between add and addw. */ 16768 insn = THUMB_OP32 (opcode); 16769 insn |= (old_op & 0xf0) << 4; 16770 put_thumb32_insn (buf, insn); 16771 if (opcode == T_MNEM_add_pc) 16772 reloc_type = BFD_RELOC_ARM_T32_IMM12; 16773 else 16774 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16775 } 16776 else 16777 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16778 pc_rel = 0; 16779 break; 16780 16781 case T_MNEM_addi: 16782 case T_MNEM_addis: 16783 case T_MNEM_subi: 16784 case T_MNEM_subis: 16785 if (fragp->fr_var == 4) 16786 { 16787 insn = THUMB_OP32 (opcode); 16788 insn |= (old_op & 0xf0) << 4; 16789 insn |= (old_op & 0xf) << 16; 16790 put_thumb32_insn (buf, insn); 16791 if (insn & (1 << 20)) 16792 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM; 16793 else 16794 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE; 16795 } 16796 else 16797 reloc_type = BFD_RELOC_ARM_THUMB_ADD; 16798 pc_rel = 0; 16799 break; 16800 default: 16801 abort(); 16802 } 16803 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel, 16804 reloc_type); 16805 fixp->fx_file = fragp->fr_file; 16806 fixp->fx_line = fragp->fr_line; 16807 fragp->fr_fix += fragp->fr_var; 16808} 16809 16810/* Return the size of a relaxable immediate operand instruction. 16811 SHIFT and SIZE specify the form of the allowable immediate. */ 16812static int 16813relax_immediate (fragS *fragp, int size, int shift) 16814{ 16815 offsetT offset; 16816 offsetT mask; 16817 offsetT low; 16818 16819 /* ??? Should be able to do better than this. */ 16820 if (fragp->fr_symbol) 16821 return 4; 16822 16823 low = (1 << shift) - 1; 16824 mask = (1 << (shift + size)) - (1 << shift); 16825 offset = fragp->fr_offset; 16826 /* Force misaligned offsets to 32-bit variant. */ 16827 if (offset & low) 16828 return 4; 16829 if (offset & ~mask) 16830 return 4; 16831 return 2; 16832} 16833 16834/* Get the address of a symbol during relaxation. */ 16835static addressT 16836relaxed_symbol_addr(fragS *fragp, long stretch) 16837{ 16838 fragS *sym_frag; 16839 addressT addr; 16840 symbolS *sym; 16841 16842 sym = fragp->fr_symbol; 16843 sym_frag = symbol_get_frag (sym); 16844 know (S_GET_SEGMENT (sym) != absolute_section 16845 || sym_frag == &zero_address_frag); 16846 addr = S_GET_VALUE (sym) + fragp->fr_offset; 16847 16848 /* If frag has yet to be reached on this pass, assume it will 16849 move by STRETCH just as we did. If this is not so, it will 16850 be because some frag between grows, and that will force 16851 another pass. */ 16852 16853 if (stretch != 0 16854 && sym_frag->relax_marker != fragp->relax_marker) 16855 addr += stretch; 16856 16857 return addr; 16858} 16859 16860/* Return the size of a relaxable adr pseudo-instruction or PC-relative 16861 load. */ 16862static int 16863relax_adr (fragS *fragp, asection *sec, long stretch) 16864{ 16865 addressT addr; 16866 offsetT val; 16867 16868 /* Assume worst case for symbols not known to be in the same section. */ 16869 if (!S_IS_DEFINED(fragp->fr_symbol) 16870 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16871 return 4; 16872 16873 val = relaxed_symbol_addr(fragp, stretch); 16874 addr = fragp->fr_address + fragp->fr_fix; 16875 addr = (addr + 4) & ~3; 16876 /* Force misaligned targets to 32-bit variant. */ 16877 if (val & 3) 16878 return 4; 16879 val -= addr; 16880 if (val < 0 || val > 1020) 16881 return 4; 16882 return 2; 16883} 16884 16885/* Return the size of a relaxable add/sub immediate instruction. */ 16886static int 16887relax_addsub (fragS *fragp, asection *sec) 16888{ 16889 char *buf; 16890 int op; 16891 16892 buf = fragp->fr_literal + fragp->fr_fix; 16893 op = bfd_get_16(sec->owner, buf); 16894 if ((op & 0xf) == ((op >> 4) & 0xf)) 16895 return relax_immediate (fragp, 8, 0); 16896 else 16897 return relax_immediate (fragp, 3, 0); 16898} 16899 16900 16901/* Return the size of a relaxable branch instruction. BITS is the 16902 size of the offset field in the narrow instruction. */ 16903 16904static int 16905relax_branch (fragS *fragp, asection *sec, int bits, long stretch) 16906{ 16907 addressT addr; 16908 offsetT val; 16909 offsetT limit; 16910 16911 /* Assume worst case for symbols not known to be in the same section. */ 16912 if (!S_IS_DEFINED(fragp->fr_symbol) 16913 || sec != S_GET_SEGMENT (fragp->fr_symbol)) 16914 return 4; 16915 16916 val = relaxed_symbol_addr(fragp, stretch); 16917 addr = fragp->fr_address + fragp->fr_fix + 4; 16918 val -= addr; 16919 16920 /* Offset is a signed value *2 */ 16921 limit = 1 << bits; 16922 if (val >= limit || val < -limit) 16923 return 4; 16924 return 2; 16925} 16926 16927 16928/* Relax a machine dependent frag. This returns the amount by which 16929 the current size of the frag should change. */ 16930 16931int 16932arm_relax_frag (asection *sec, fragS *fragp, long stretch) 16933{ 16934 int oldsize; 16935 int newsize; 16936 16937 oldsize = fragp->fr_var; 16938 switch (fragp->fr_subtype) 16939 { 16940 case T_MNEM_ldr_pc2: 16941 newsize = relax_adr(fragp, sec, stretch); 16942 break; 16943 case T_MNEM_ldr_pc: 16944 case T_MNEM_ldr_sp: 16945 case T_MNEM_str_sp: 16946 newsize = relax_immediate(fragp, 8, 2); 16947 break; 16948 case T_MNEM_ldr: 16949 case T_MNEM_str: 16950 newsize = relax_immediate(fragp, 5, 2); 16951 break; 16952 case T_MNEM_ldrh: 16953 case T_MNEM_strh: 16954 newsize = relax_immediate(fragp, 5, 1); 16955 break; 16956 case T_MNEM_ldrb: 16957 case T_MNEM_strb: 16958 newsize = relax_immediate(fragp, 5, 0); 16959 break; 16960 case T_MNEM_adr: 16961 newsize = relax_adr(fragp, sec, stretch); 16962 break; 16963 case T_MNEM_mov: 16964 case T_MNEM_movs: 16965 case T_MNEM_cmp: 16966 case T_MNEM_cmn: 16967 newsize = relax_immediate(fragp, 8, 0); 16968 break; 16969 case T_MNEM_b: 16970 newsize = relax_branch(fragp, sec, 11, stretch); 16971 break; 16972 case T_MNEM_bcond: 16973 newsize = relax_branch(fragp, sec, 8, stretch); 16974 break; 16975 case T_MNEM_add_sp: 16976 case T_MNEM_add_pc: 16977 newsize = relax_immediate (fragp, 8, 2); 16978 break; 16979 case T_MNEM_inc_sp: 16980 case T_MNEM_dec_sp: 16981 newsize = relax_immediate (fragp, 7, 2); 16982 break; 16983 case T_MNEM_addi: 16984 case T_MNEM_addis: 16985 case T_MNEM_subi: 16986 case T_MNEM_subis: 16987 newsize = relax_addsub (fragp, sec); 16988 break; 16989 default: 16990 abort(); 16991 } 16992 16993 fragp->fr_var = newsize; 16994 /* Freeze wide instructions that are at or before the same location as 16995 in the previous pass. This avoids infinite loops. 16996 Don't freeze them unconditionally because targets may be artificialy 16997 misaligned by the expansion of preceeding frags. */ 16998 if (stretch <= 0 && newsize > 2) 16999 { 17000 md_convert_frag (sec->owner, sec, fragp); 17001 frag_wane(fragp); 17002 } 17003 17004 return newsize - oldsize; 17005} 17006 17007/* Round up a section size to the appropriate boundary. */ 17008 17009valueT 17010md_section_align (segT segment ATTRIBUTE_UNUSED, 17011 valueT size) 17012{ 17013#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 17014 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 17015 { 17016 /* For a.out, force the section size to be aligned. If we don't do 17017 this, BFD will align it for us, but it will not write out the 17018 final bytes of the section. This may be a bug in BFD, but it is 17019 easier to fix it here since that is how the other a.out targets 17020 work. */ 17021 int align; 17022 17023 align = bfd_get_section_alignment (stdoutput, segment); 17024 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 17025 } 17026#endif 17027 17028 return size; 17029} 17030 17031/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 17032 of an rs_align_code fragment. */ 17033 17034void 17035arm_handle_align (fragS * fragP) 17036{ 17037 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 }; 17038 static char const thumb_noop[2] = { 0xc0, 0x46 }; 17039 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 }; 17040 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 }; 17041 17042 int bytes, fix, noop_size; 17043 char * p; 17044 const char * noop; 17045 17046 if (fragP->fr_type != rs_align_code) 17047 return; 17048 17049 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 17050 p = fragP->fr_literal + fragP->fr_fix; 17051 fix = 0; 17052 17053 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE) 17054 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE; 17055 17056 if (fragP->tc_frag_data) 17057 { 17058 if (target_big_endian) 17059 noop = thumb_bigend_noop; 17060 else 17061 noop = thumb_noop; 17062 noop_size = sizeof (thumb_noop); 17063 } 17064 else 17065 { 17066 if (target_big_endian) 17067 noop = arm_bigend_noop; 17068 else 17069 noop = arm_noop; 17070 noop_size = sizeof (arm_noop); 17071 } 17072 17073 if (bytes & (noop_size - 1)) 17074 { 17075 fix = bytes & (noop_size - 1); 17076 memset (p, 0, fix); 17077 p += fix; 17078 bytes -= fix; 17079 } 17080 17081 while (bytes >= noop_size) 17082 { 17083 memcpy (p, noop, noop_size); 17084 p += noop_size; 17085 bytes -= noop_size; 17086 fix += noop_size; 17087 } 17088 17089 fragP->fr_fix += fix; 17090 fragP->fr_var = noop_size; 17091} 17092 17093/* Called from md_do_align. Used to create an alignment 17094 frag in a code section. */ 17095 17096void 17097arm_frag_align_code (int n, int max) 17098{ 17099 char * p; 17100 17101 /* We assume that there will never be a requirement 17102 to support alignments greater than 32 bytes. */ 17103 if (max > MAX_MEM_FOR_RS_ALIGN_CODE) 17104 as_fatal (_("alignments greater than 32 bytes not supported in .text sections.")); 17105 17106 p = frag_var (rs_align_code, 17107 MAX_MEM_FOR_RS_ALIGN_CODE, 17108 1, 17109 (relax_substateT) max, 17110 (symbolS *) NULL, 17111 (offsetT) n, 17112 (char *) NULL); 17113 *p = 0; 17114} 17115 17116/* Perform target specific initialisation of a frag. */ 17117 17118void 17119arm_init_frag (fragS * fragP) 17120{ 17121 /* Record whether this frag is in an ARM or a THUMB area. */ 17122 fragP->tc_frag_data = thumb_mode; 17123} 17124 17125#ifdef OBJ_ELF 17126/* When we change sections we need to issue a new mapping symbol. */ 17127 17128void 17129arm_elf_change_section (void) 17130{ 17131 flagword flags; 17132 segment_info_type *seginfo; 17133 17134 /* Link an unlinked unwind index table section to the .text section. */ 17135 if (elf_section_type (now_seg) == SHT_ARM_EXIDX 17136 && elf_linked_to_section (now_seg) == NULL) 17137 elf_linked_to_section (now_seg) = text_section; 17138 17139 if (!SEG_NORMAL (now_seg)) 17140 return; 17141 17142 flags = bfd_get_section_flags (stdoutput, now_seg); 17143 17144 /* We can ignore sections that only contain debug info. */ 17145 if ((flags & SEC_ALLOC) == 0) 17146 return; 17147 17148 seginfo = seg_info (now_seg); 17149 mapstate = seginfo->tc_segment_info_data.mapstate; 17150 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency; 17151} 17152 17153int 17154arm_elf_section_type (const char * str, size_t len) 17155{ 17156 if (len == 5 && strncmp (str, "exidx", 5) == 0) 17157 return SHT_ARM_EXIDX; 17158 17159 return -1; 17160} 17161 17162/* Code to deal with unwinding tables. */ 17163 17164static void add_unwind_adjustsp (offsetT); 17165 17166/* Cenerate and deferred unwind frame offset. */ 17167 17168static void 17169flush_pending_unwind (void) 17170{ 17171 offsetT offset; 17172 17173 offset = unwind.pending_offset; 17174 unwind.pending_offset = 0; 17175 if (offset != 0) 17176 add_unwind_adjustsp (offset); 17177} 17178 17179/* Add an opcode to this list for this function. Two-byte opcodes should 17180 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse 17181 order. */ 17182 17183static void 17184add_unwind_opcode (valueT op, int length) 17185{ 17186 /* Add any deferred stack adjustment. */ 17187 if (unwind.pending_offset) 17188 flush_pending_unwind (); 17189 17190 unwind.sp_restored = 0; 17191 17192 if (unwind.opcode_count + length > unwind.opcode_alloc) 17193 { 17194 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE; 17195 if (unwind.opcodes) 17196 unwind.opcodes = xrealloc (unwind.opcodes, 17197 unwind.opcode_alloc); 17198 else 17199 unwind.opcodes = xmalloc (unwind.opcode_alloc); 17200 } 17201 while (length > 0) 17202 { 17203 length--; 17204 unwind.opcodes[unwind.opcode_count] = op & 0xff; 17205 op >>= 8; 17206 unwind.opcode_count++; 17207 } 17208} 17209 17210/* Add unwind opcodes to adjust the stack pointer. */ 17211 17212static void 17213add_unwind_adjustsp (offsetT offset) 17214{ 17215 valueT op; 17216 17217 if (offset > 0x200) 17218 { 17219 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */ 17220 char bytes[5]; 17221 int n; 17222 valueT o; 17223 17224 /* Long form: 0xb2, uleb128. */ 17225 /* This might not fit in a word so add the individual bytes, 17226 remembering the list is built in reverse order. */ 17227 o = (valueT) ((offset - 0x204) >> 2); 17228 if (o == 0) 17229 add_unwind_opcode (0, 1); 17230 17231 /* Calculate the uleb128 encoding of the offset. */ 17232 n = 0; 17233 while (o) 17234 { 17235 bytes[n] = o & 0x7f; 17236 o >>= 7; 17237 if (o) 17238 bytes[n] |= 0x80; 17239 n++; 17240 } 17241 /* Add the insn. */ 17242 for (; n; n--) 17243 add_unwind_opcode (bytes[n - 1], 1); 17244 add_unwind_opcode (0xb2, 1); 17245 } 17246 else if (offset > 0x100) 17247 { 17248 /* Two short opcodes. */ 17249 add_unwind_opcode (0x3f, 1); 17250 op = (offset - 0x104) >> 2; 17251 add_unwind_opcode (op, 1); 17252 } 17253 else if (offset > 0) 17254 { 17255 /* Short opcode. */ 17256 op = (offset - 4) >> 2; 17257 add_unwind_opcode (op, 1); 17258 } 17259 else if (offset < 0) 17260 { 17261 offset = -offset; 17262 while (offset > 0x100) 17263 { 17264 add_unwind_opcode (0x7f, 1); 17265 offset -= 0x100; 17266 } 17267 op = ((offset - 4) >> 2) | 0x40; 17268 add_unwind_opcode (op, 1); 17269 } 17270} 17271 17272/* Finish the list of unwind opcodes for this function. */ 17273static void 17274finish_unwind_opcodes (void) 17275{ 17276 valueT op; 17277 17278 if (unwind.fp_used) 17279 { 17280 /* Adjust sp as necessary. */ 17281 unwind.pending_offset += unwind.fp_offset - unwind.frame_size; 17282 flush_pending_unwind (); 17283 17284 /* After restoring sp from the frame pointer. */ 17285 op = 0x90 | unwind.fp_reg; 17286 add_unwind_opcode (op, 1); 17287 } 17288 else 17289 flush_pending_unwind (); 17290} 17291 17292 17293/* Start an exception table entry. If idx is nonzero this is an index table 17294 entry. */ 17295 17296static void 17297start_unwind_section (const segT text_seg, int idx) 17298{ 17299 const char * text_name; 17300 const char * prefix; 17301 const char * prefix_once; 17302 const char * group_name; 17303 size_t prefix_len; 17304 size_t text_len; 17305 char * sec_name; 17306 size_t sec_name_len; 17307 int type; 17308 int flags; 17309 int linkonce; 17310 17311 if (idx) 17312 { 17313 prefix = ELF_STRING_ARM_unwind; 17314 prefix_once = ELF_STRING_ARM_unwind_once; 17315 type = SHT_ARM_EXIDX; 17316 } 17317 else 17318 { 17319 prefix = ELF_STRING_ARM_unwind_info; 17320 prefix_once = ELF_STRING_ARM_unwind_info_once; 17321 type = SHT_PROGBITS; 17322 } 17323 17324 text_name = segment_name (text_seg); 17325 if (streq (text_name, ".text")) 17326 text_name = ""; 17327 17328 if (strncmp (text_name, ".gnu.linkonce.t.", 17329 strlen (".gnu.linkonce.t.")) == 0) 17330 { 17331 prefix = prefix_once; 17332 text_name += strlen (".gnu.linkonce.t."); 17333 } 17334 17335 prefix_len = strlen (prefix); 17336 text_len = strlen (text_name); 17337 sec_name_len = prefix_len + text_len; 17338 sec_name = xmalloc (sec_name_len + 1); 17339 memcpy (sec_name, prefix, prefix_len); 17340 memcpy (sec_name + prefix_len, text_name, text_len); 17341 sec_name[prefix_len + text_len] = '\0'; 17342 17343 flags = SHF_ALLOC; 17344 linkonce = 0; 17345 group_name = 0; 17346 17347 /* Handle COMDAT group. */ 17348 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0) 17349 { 17350 group_name = elf_group_name (text_seg); 17351 if (group_name == NULL) 17352 { 17353 as_bad ("Group section `%s' has no group signature", 17354 segment_name (text_seg)); 17355 ignore_rest_of_line (); 17356 return; 17357 } 17358 flags |= SHF_GROUP; 17359 linkonce = 1; 17360 } 17361 17362 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0); 17363 17364 /* Set the setion link for index tables. */ 17365 if (idx) 17366 elf_linked_to_section (now_seg) = text_seg; 17367} 17368 17369 17370/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional 17371 personality routine data. Returns zero, or the index table value for 17372 and inline entry. */ 17373 17374static valueT 17375create_unwind_entry (int have_data) 17376{ 17377 int size; 17378 addressT where; 17379 char *ptr; 17380 /* The current word of data. */ 17381 valueT data; 17382 /* The number of bytes left in this word. */ 17383 int n; 17384 17385 finish_unwind_opcodes (); 17386 17387 /* Remember the current text section. */ 17388 unwind.saved_seg = now_seg; 17389 unwind.saved_subseg = now_subseg; 17390 17391 start_unwind_section (now_seg, 0); 17392 17393 if (unwind.personality_routine == NULL) 17394 { 17395 if (unwind.personality_index == -2) 17396 { 17397 if (have_data) 17398 as_bad (_("handerdata in cantunwind frame")); 17399 return 1; /* EXIDX_CANTUNWIND. */ 17400 } 17401 17402 /* Use a default personality routine if none is specified. */ 17403 if (unwind.personality_index == -1) 17404 { 17405 if (unwind.opcode_count > 3) 17406 unwind.personality_index = 1; 17407 else 17408 unwind.personality_index = 0; 17409 } 17410 17411 /* Space for the personality routine entry. */ 17412 if (unwind.personality_index == 0) 17413 { 17414 if (unwind.opcode_count > 3) 17415 as_bad (_("too many unwind opcodes for personality routine 0")); 17416 17417 if (!have_data) 17418 { 17419 /* All the data is inline in the index table. */ 17420 data = 0x80; 17421 n = 3; 17422 while (unwind.opcode_count > 0) 17423 { 17424 unwind.opcode_count--; 17425 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17426 n--; 17427 } 17428 17429 /* Pad with "finish" opcodes. */ 17430 while (n--) 17431 data = (data << 8) | 0xb0; 17432 17433 return data; 17434 } 17435 size = 0; 17436 } 17437 else 17438 /* We get two opcodes "free" in the first word. */ 17439 size = unwind.opcode_count - 2; 17440 } 17441 else 17442 /* An extra byte is required for the opcode count. */ 17443 size = unwind.opcode_count + 1; 17444 17445 size = (size + 3) >> 2; 17446 if (size > 0xff) 17447 as_bad (_("too many unwind opcodes")); 17448 17449 frag_align (2, 0, 0); 17450 record_alignment (now_seg, 2); 17451 unwind.table_entry = expr_build_dot (); 17452 17453 /* Allocate the table entry. */ 17454 ptr = frag_more ((size << 2) + 4); 17455 memset(ptr, 0, (size << 2) + 4); 17456 where = frag_now_fix () - ((size << 2) + 4); 17457 17458 switch (unwind.personality_index) 17459 { 17460 case -1: 17461 /* ??? Should this be a PLT generating relocation? */ 17462 /* Custom personality routine. */ 17463 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1, 17464 BFD_RELOC_ARM_PREL31); 17465 17466 where += 4; 17467 ptr += 4; 17468 17469 /* Set the first byte to the number of additional words. */ 17470 data = size - 1; 17471 n = 3; 17472 break; 17473 17474 /* ABI defined personality routines. */ 17475 case 0: 17476 /* Three opcodes bytes are packed into the first word. */ 17477 data = 0x80; 17478 n = 3; 17479 break; 17480 17481 case 1: 17482 case 2: 17483 /* The size and first two opcode bytes go in the first word. */ 17484 data = ((0x80 + unwind.personality_index) << 8) | size; 17485 n = 2; 17486 break; 17487 17488 default: 17489 /* Should never happen. */ 17490 abort (); 17491 } 17492 17493 /* Pack the opcodes into words (MSB first), reversing the list at the same 17494 time. */ 17495 while (unwind.opcode_count > 0) 17496 { 17497 if (n == 0) 17498 { 17499 md_number_to_chars (ptr, data, 4); 17500 ptr += 4; 17501 n = 4; 17502 data = 0; 17503 } 17504 unwind.opcode_count--; 17505 n--; 17506 data = (data << 8) | unwind.opcodes[unwind.opcode_count]; 17507 } 17508 17509 /* Finish off the last word. */ 17510 if (n < 4) 17511 { 17512 /* Pad with "finish" opcodes. */ 17513 while (n--) 17514 data = (data << 8) | 0xb0; 17515 17516 md_number_to_chars (ptr, data, 4); 17517 } 17518 17519 if (!have_data) 17520 { 17521 /* Add an empty descriptor if there is no user-specified data. */ 17522 ptr = frag_more (4); 17523 md_number_to_chars (ptr, 0, 4); 17524 } 17525 17526 return 0; 17527} 17528 17529 17530/* Initialize the DWARF-2 unwind information for this procedure. */ 17531 17532void 17533tc_arm_frame_initial_instructions (void) 17534{ 17535 cfi_add_CFA_def_cfa (REG_SP, 0); 17536} 17537#endif /* OBJ_ELF */ 17538 17539/* Convert REGNAME to a DWARF-2 register number. */ 17540 17541int 17542tc_arm_regname_to_dw2regnum (char *regname) 17543{ 17544 int reg = arm_reg_parse (®name, REG_TYPE_RN); 17545 17546 if (reg == FAIL) 17547 return -1; 17548 17549 return reg; 17550} 17551 17552#ifdef TE_PE 17553void 17554tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 17555{ 17556 expressionS expr; 17557 17558 expr.X_op = O_secrel; 17559 expr.X_add_symbol = symbol; 17560 expr.X_add_number = 0; 17561 emit_expr (&expr, size); 17562} 17563#endif 17564 17565/* MD interface: Symbol and relocation handling. */ 17566 17567/* Return the address within the segment that a PC-relative fixup is 17568 relative to. For ARM, PC-relative fixups applied to instructions 17569 are generally relative to the location of the fixup plus 8 bytes. 17570 Thumb branches are offset by 4, and Thumb loads relative to PC 17571 require special handling. */ 17572 17573long 17574md_pcrel_from_section (fixS * fixP, segT seg) 17575{ 17576 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; 17577 17578 /* If this is pc-relative and we are going to emit a relocation 17579 then we just want to put out any pipeline compensation that the linker 17580 will need. Otherwise we want to use the calculated base. 17581 For WinCE we skip the bias for externals as well, since this 17582 is how the MS ARM-CE assembler behaves and we want to be compatible. */ 17583 if (fixP->fx_pcrel 17584 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) 17585 || (arm_force_relocation (fixP) 17586#ifdef TE_WINCE 17587 && !S_IS_EXTERNAL (fixP->fx_addsy) 17588#endif 17589 ))) 17590 base = 0; 17591 17592 switch (fixP->fx_r_type) 17593 { 17594 /* PC relative addressing on the Thumb is slightly odd as the 17595 bottom two bits of the PC are forced to zero for the 17596 calculation. This happens *after* application of the 17597 pipeline offset. However, Thumb adrl already adjusts for 17598 this, so we need not do it again. */ 17599 case BFD_RELOC_ARM_THUMB_ADD: 17600 return base & ~3; 17601 17602 case BFD_RELOC_ARM_THUMB_OFFSET: 17603 case BFD_RELOC_ARM_T32_OFFSET_IMM: 17604 case BFD_RELOC_ARM_T32_ADD_PC12: 17605 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 17606 return (base + 4) & ~3; 17607 17608 /* Thumb branches are simply offset by +4. */ 17609 case BFD_RELOC_THUMB_PCREL_BRANCH7: 17610 case BFD_RELOC_THUMB_PCREL_BRANCH9: 17611 case BFD_RELOC_THUMB_PCREL_BRANCH12: 17612 case BFD_RELOC_THUMB_PCREL_BRANCH20: 17613 case BFD_RELOC_THUMB_PCREL_BRANCH23: 17614 case BFD_RELOC_THUMB_PCREL_BRANCH25: 17615 case BFD_RELOC_THUMB_PCREL_BLX: 17616 return base + 4; 17617 17618 /* ARM mode branches are offset by +8. However, the Windows CE 17619 loader expects the relocation not to take this into account. */ 17620 case BFD_RELOC_ARM_PCREL_BRANCH: 17621 case BFD_RELOC_ARM_PCREL_CALL: 17622 case BFD_RELOC_ARM_PCREL_JUMP: 17623 case BFD_RELOC_ARM_PCREL_BLX: 17624 case BFD_RELOC_ARM_PLT32: 17625#ifdef TE_WINCE 17626 /* When handling fixups immediately, because we have already 17627 discovered the value of a symbol, or the address of the frag involved 17628 we must account for the offset by +8, as the OS loader will never see the reloc. 17629 see fixup_segment() in write.c 17630 The S_IS_EXTERNAL test handles the case of global symbols. 17631 Those need the calculated base, not just the pipe compensation the linker will need. */ 17632 if (fixP->fx_pcrel 17633 && fixP->fx_addsy != NULL 17634 && (S_GET_SEGMENT (fixP->fx_addsy) == seg) 17635 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP))) 17636 return base + 8; 17637 return base; 17638#else 17639 return base + 8; 17640#endif 17641 17642 /* ARM mode loads relative to PC are also offset by +8. Unlike 17643 branches, the Windows CE loader *does* expect the relocation 17644 to take this into account. */ 17645 case BFD_RELOC_ARM_OFFSET_IMM: 17646 case BFD_RELOC_ARM_OFFSET_IMM8: 17647 case BFD_RELOC_ARM_HWLITERAL: 17648 case BFD_RELOC_ARM_LITERAL: 17649 case BFD_RELOC_ARM_CP_OFF_IMM: 17650 return base + 8; 17651 17652 17653 /* Other PC-relative relocations are un-offset. */ 17654 default: 17655 return base; 17656 } 17657} 17658 17659/* Under ELF we need to default _GLOBAL_OFFSET_TABLE. 17660 Otherwise we have no need to default values of symbols. */ 17661 17662symbolS * 17663md_undefined_symbol (char * name ATTRIBUTE_UNUSED) 17664{ 17665#ifdef OBJ_ELF 17666 if (name[0] == '_' && name[1] == 'G' 17667 && streq (name, GLOBAL_OFFSET_TABLE_NAME)) 17668 { 17669 if (!GOT_symbol) 17670 { 17671 if (symbol_find (name)) 17672 as_bad ("GOT already in the symbol table"); 17673 17674 GOT_symbol = symbol_new (name, undefined_section, 17675 (valueT) 0, & zero_address_frag); 17676 } 17677 17678 return GOT_symbol; 17679 } 17680#endif 17681 17682 return 0; 17683} 17684 17685/* Subroutine of md_apply_fix. Check to see if an immediate can be 17686 computed as two separate immediate values, added together. We 17687 already know that this value cannot be computed by just one ARM 17688 instruction. */ 17689 17690static unsigned int 17691validate_immediate_twopart (unsigned int val, 17692 unsigned int * highpart) 17693{ 17694 unsigned int a; 17695 unsigned int i; 17696 17697 for (i = 0; i < 32; i += 2) 17698 if (((a = rotate_left (val, i)) & 0xff) != 0) 17699 { 17700 if (a & 0xff00) 17701 { 17702 if (a & ~ 0xffff) 17703 continue; 17704 * highpart = (a >> 8) | ((i + 24) << 7); 17705 } 17706 else if (a & 0xff0000) 17707 { 17708 if (a & 0xff000000) 17709 continue; 17710 * highpart = (a >> 16) | ((i + 16) << 7); 17711 } 17712 else 17713 { 17714 assert (a & 0xff000000); 17715 * highpart = (a >> 24) | ((i + 8) << 7); 17716 } 17717 17718 return (a & 0xff) | (i << 7); 17719 } 17720 17721 return FAIL; 17722} 17723 17724static int 17725validate_offset_imm (unsigned int val, int hwse) 17726{ 17727 if ((hwse && val > 255) || val > 4095) 17728 return FAIL; 17729 return val; 17730} 17731 17732/* Subroutine of md_apply_fix. Do those data_ops which can take a 17733 negative immediate constant by altering the instruction. A bit of 17734 a hack really. 17735 MOV <-> MVN 17736 AND <-> BIC 17737 ADC <-> SBC 17738 by inverting the second operand, and 17739 ADD <-> SUB 17740 CMP <-> CMN 17741 by negating the second operand. */ 17742 17743static int 17744negate_data_op (unsigned long * instruction, 17745 unsigned long value) 17746{ 17747 int op, new_inst; 17748 unsigned long negated, inverted; 17749 17750 negated = encode_arm_immediate (-value); 17751 inverted = encode_arm_immediate (~value); 17752 17753 op = (*instruction >> DATA_OP_SHIFT) & 0xf; 17754 switch (op) 17755 { 17756 /* First negates. */ 17757 case OPCODE_SUB: /* ADD <-> SUB */ 17758 new_inst = OPCODE_ADD; 17759 value = negated; 17760 break; 17761 17762 case OPCODE_ADD: 17763 new_inst = OPCODE_SUB; 17764 value = negated; 17765 break; 17766 17767 case OPCODE_CMP: /* CMP <-> CMN */ 17768 new_inst = OPCODE_CMN; 17769 value = negated; 17770 break; 17771 17772 case OPCODE_CMN: 17773 new_inst = OPCODE_CMP; 17774 value = negated; 17775 break; 17776 17777 /* Now Inverted ops. */ 17778 case OPCODE_MOV: /* MOV <-> MVN */ 17779 new_inst = OPCODE_MVN; 17780 value = inverted; 17781 break; 17782 17783 case OPCODE_MVN: 17784 new_inst = OPCODE_MOV; 17785 value = inverted; 17786 break; 17787 17788 case OPCODE_AND: /* AND <-> BIC */ 17789 new_inst = OPCODE_BIC; 17790 value = inverted; 17791 break; 17792 17793 case OPCODE_BIC: 17794 new_inst = OPCODE_AND; 17795 value = inverted; 17796 break; 17797 17798 case OPCODE_ADC: /* ADC <-> SBC */ 17799 new_inst = OPCODE_SBC; 17800 value = inverted; 17801 break; 17802 17803 case OPCODE_SBC: 17804 new_inst = OPCODE_ADC; 17805 value = inverted; 17806 break; 17807 17808 /* We cannot do anything. */ 17809 default: 17810 return FAIL; 17811 } 17812 17813 if (value == (unsigned) FAIL) 17814 return FAIL; 17815 17816 *instruction &= OPCODE_MASK; 17817 *instruction |= new_inst << DATA_OP_SHIFT; 17818 return value; 17819} 17820 17821/* Like negate_data_op, but for Thumb-2. */ 17822 17823static unsigned int 17824thumb32_negate_data_op (offsetT *instruction, unsigned int value) 17825{ 17826 int op, new_inst; 17827 int rd; 17828 unsigned int negated, inverted; 17829 17830 negated = encode_thumb32_immediate (-value); 17831 inverted = encode_thumb32_immediate (~value); 17832 17833 rd = (*instruction >> 8) & 0xf; 17834 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf; 17835 switch (op) 17836 { 17837 /* ADD <-> SUB. Includes CMP <-> CMN. */ 17838 case T2_OPCODE_SUB: 17839 new_inst = T2_OPCODE_ADD; 17840 value = negated; 17841 break; 17842 17843 case T2_OPCODE_ADD: 17844 new_inst = T2_OPCODE_SUB; 17845 value = negated; 17846 break; 17847 17848 /* ORR <-> ORN. Includes MOV <-> MVN. */ 17849 case T2_OPCODE_ORR: 17850 new_inst = T2_OPCODE_ORN; 17851 value = inverted; 17852 break; 17853 17854 case T2_OPCODE_ORN: 17855 new_inst = T2_OPCODE_ORR; 17856 value = inverted; 17857 break; 17858 17859 /* AND <-> BIC. TST has no inverted equivalent. */ 17860 case T2_OPCODE_AND: 17861 new_inst = T2_OPCODE_BIC; 17862 if (rd == 15) 17863 value = FAIL; 17864 else 17865 value = inverted; 17866 break; 17867 17868 case T2_OPCODE_BIC: 17869 new_inst = T2_OPCODE_AND; 17870 value = inverted; 17871 break; 17872 17873 /* ADC <-> SBC */ 17874 case T2_OPCODE_ADC: 17875 new_inst = T2_OPCODE_SBC; 17876 value = inverted; 17877 break; 17878 17879 case T2_OPCODE_SBC: 17880 new_inst = T2_OPCODE_ADC; 17881 value = inverted; 17882 break; 17883 17884 /* We cannot do anything. */ 17885 default: 17886 return FAIL; 17887 } 17888 17889 if (value == (unsigned int)FAIL) 17890 return FAIL; 17891 17892 *instruction &= T2_OPCODE_MASK; 17893 *instruction |= new_inst << T2_DATA_OP_SHIFT; 17894 return value; 17895} 17896 17897/* Read a 32-bit thumb instruction from buf. */ 17898static unsigned long 17899get_thumb32_insn (char * buf) 17900{ 17901 unsigned long insn; 17902 insn = md_chars_to_number (buf, THUMB_SIZE) << 16; 17903 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 17904 17905 return insn; 17906} 17907 17908 17909/* We usually want to set the low bit on the address of thumb function 17910 symbols. In particular .word foo - . should have the low bit set. 17911 Generic code tries to fold the difference of two symbols to 17912 a constant. Prevent this and force a relocation when the first symbols 17913 is a thumb function. */ 17914int 17915arm_optimize_expr (expressionS *l, operatorT op, expressionS *r) 17916{ 17917 if (op == O_subtract 17918 && l->X_op == O_symbol 17919 && r->X_op == O_symbol 17920 && THUMB_IS_FUNC (l->X_add_symbol)) 17921 { 17922 l->X_op = O_subtract; 17923 l->X_op_symbol = r->X_add_symbol; 17924 l->X_add_number -= r->X_add_number; 17925 return 1; 17926 } 17927 /* Process as normal. */ 17928 return 0; 17929} 17930 17931void 17932md_apply_fix (fixS * fixP, 17933 valueT * valP, 17934 segT seg) 17935{ 17936 offsetT value = * valP; 17937 offsetT newval; 17938 unsigned int newimm; 17939 unsigned long temp; 17940 int sign; 17941 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal; 17942 17943 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED); 17944 17945 /* Note whether this will delete the relocation. */ 17946 17947 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 17948 fixP->fx_done = 1; 17949 17950 /* On a 64-bit host, silently truncate 'value' to 32 bits for 17951 consistency with the behavior on 32-bit hosts. Remember value 17952 for emit_reloc. */ 17953 value &= 0xffffffff; 17954 value ^= 0x80000000; 17955 value -= 0x80000000; 17956 17957 *valP = value; 17958 fixP->fx_addnumber = value; 17959 17960 /* Same treatment for fixP->fx_offset. */ 17961 fixP->fx_offset &= 0xffffffff; 17962 fixP->fx_offset ^= 0x80000000; 17963 fixP->fx_offset -= 0x80000000; 17964 17965 switch (fixP->fx_r_type) 17966 { 17967 case BFD_RELOC_NONE: 17968 /* This will need to go in the object file. */ 17969 fixP->fx_done = 0; 17970 break; 17971 17972 case BFD_RELOC_ARM_IMMEDIATE: 17973 /* We claim that this fixup has been processed here, 17974 even if in fact we generate an error because we do 17975 not have a reloc for it, so tc_gen_reloc will reject it. */ 17976 fixP->fx_done = 1; 17977 17978 if (fixP->fx_addsy 17979 && ! S_IS_DEFINED (fixP->fx_addsy)) 17980 { 17981 as_bad_where (fixP->fx_file, fixP->fx_line, 17982 _("undefined symbol %s used as an immediate value"), 17983 S_GET_NAME (fixP->fx_addsy)); 17984 break; 17985 } 17986 17987 newimm = encode_arm_immediate (value); 17988 temp = md_chars_to_number (buf, INSN_SIZE); 17989 17990 /* If the instruction will fail, see if we can fix things up by 17991 changing the opcode. */ 17992 if (newimm == (unsigned int) FAIL 17993 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL) 17994 { 17995 as_bad_where (fixP->fx_file, fixP->fx_line, 17996 _("invalid constant (%lx) after fixup"), 17997 (unsigned long) value); 17998 break; 17999 } 18000 18001 newimm |= (temp & 0xfffff000); 18002 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 18003 break; 18004 18005 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 18006 { 18007 unsigned int highpart = 0; 18008 unsigned int newinsn = 0xe1a00000; /* nop. */ 18009 18010 newimm = encode_arm_immediate (value); 18011 temp = md_chars_to_number (buf, INSN_SIZE); 18012 18013 /* If the instruction will fail, see if we can fix things up by 18014 changing the opcode. */ 18015 if (newimm == (unsigned int) FAIL 18016 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL) 18017 { 18018 /* No ? OK - try using two ADD instructions to generate 18019 the value. */ 18020 newimm = validate_immediate_twopart (value, & highpart); 18021 18022 /* Yes - then make sure that the second instruction is 18023 also an add. */ 18024 if (newimm != (unsigned int) FAIL) 18025 newinsn = temp; 18026 /* Still No ? Try using a negated value. */ 18027 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL) 18028 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT; 18029 /* Otherwise - give up. */ 18030 else 18031 { 18032 as_bad_where (fixP->fx_file, fixP->fx_line, 18033 _("unable to compute ADRL instructions for PC offset of 0x%lx"), 18034 (long) value); 18035 break; 18036 } 18037 18038 /* Replace the first operand in the 2nd instruction (which 18039 is the PC) with the destination register. We have 18040 already added in the PC in the first instruction and we 18041 do not want to do it again. */ 18042 newinsn &= ~ 0xf0000; 18043 newinsn |= ((newinsn & 0x0f000) << 4); 18044 } 18045 18046 newimm |= (temp & 0xfffff000); 18047 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE); 18048 18049 highpart |= (newinsn & 0xfffff000); 18050 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE); 18051 } 18052 break; 18053 18054 case BFD_RELOC_ARM_OFFSET_IMM: 18055 if (!fixP->fx_done && seg->use_rela_p) 18056 value = 0; 18057 18058 case BFD_RELOC_ARM_LITERAL: 18059 sign = value >= 0; 18060 18061 if (value < 0) 18062 value = - value; 18063 18064 if (validate_offset_imm (value, 0) == FAIL) 18065 { 18066 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL) 18067 as_bad_where (fixP->fx_file, fixP->fx_line, 18068 _("invalid literal constant: pool needs to be closer")); 18069 else 18070 as_bad_where (fixP->fx_file, fixP->fx_line, 18071 _("bad immediate value for offset (%ld)"), 18072 (long) value); 18073 break; 18074 } 18075 18076 newval = md_chars_to_number (buf, INSN_SIZE); 18077 newval &= 0xff7ff000; 18078 newval |= value | (sign ? INDEX_UP : 0); 18079 md_number_to_chars (buf, newval, INSN_SIZE); 18080 break; 18081 18082 case BFD_RELOC_ARM_OFFSET_IMM8: 18083 case BFD_RELOC_ARM_HWLITERAL: 18084 sign = value >= 0; 18085 18086 if (value < 0) 18087 value = - value; 18088 18089 if (validate_offset_imm (value, 1) == FAIL) 18090 { 18091 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL) 18092 as_bad_where (fixP->fx_file, fixP->fx_line, 18093 _("invalid literal constant: pool needs to be closer")); 18094 else 18095 as_bad (_("bad immediate value for 8-bit offset (%ld)"), 18096 (long) value); 18097 break; 18098 } 18099 18100 newval = md_chars_to_number (buf, INSN_SIZE); 18101 newval &= 0xff7ff0f0; 18102 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0); 18103 md_number_to_chars (buf, newval, INSN_SIZE); 18104 break; 18105 18106 case BFD_RELOC_ARM_T32_OFFSET_U8: 18107 if (value < 0 || value > 1020 || value % 4 != 0) 18108 as_bad_where (fixP->fx_file, fixP->fx_line, 18109 _("bad immediate value for offset (%ld)"), (long) value); 18110 value /= 4; 18111 18112 newval = md_chars_to_number (buf+2, THUMB_SIZE); 18113 newval |= value; 18114 md_number_to_chars (buf+2, newval, THUMB_SIZE); 18115 break; 18116 18117 case BFD_RELOC_ARM_T32_OFFSET_IMM: 18118 /* This is a complicated relocation used for all varieties of Thumb32 18119 load/store instruction with immediate offset: 18120 18121 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit, 18122 *4, optional writeback(W) 18123 (doubleword load/store) 18124 18125 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel 18126 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit 18127 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction) 18128 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit 18129 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit 18130 18131 Uppercase letters indicate bits that are already encoded at 18132 this point. Lowercase letters are our problem. For the 18133 second block of instructions, the secondary opcode nybble 18134 (bits 8..11) is present, and bit 23 is zero, even if this is 18135 a PC-relative operation. */ 18136 newval = md_chars_to_number (buf, THUMB_SIZE); 18137 newval <<= 16; 18138 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE); 18139 18140 if ((newval & 0xf0000000) == 0xe0000000) 18141 { 18142 /* Doubleword load/store: 8-bit offset, scaled by 4. */ 18143 if (value >= 0) 18144 newval |= (1 << 23); 18145 else 18146 value = -value; 18147 if (value % 4 != 0) 18148 { 18149 as_bad_where (fixP->fx_file, fixP->fx_line, 18150 _("offset not a multiple of 4")); 18151 break; 18152 } 18153 value /= 4; 18154 if (value > 0xff) 18155 { 18156 as_bad_where (fixP->fx_file, fixP->fx_line, 18157 _("offset out of range")); 18158 break; 18159 } 18160 newval &= ~0xff; 18161 } 18162 else if ((newval & 0x000f0000) == 0x000f0000) 18163 { 18164 /* PC-relative, 12-bit offset. */ 18165 if (value >= 0) 18166 newval |= (1 << 23); 18167 else 18168 value = -value; 18169 if (value > 0xfff) 18170 { 18171 as_bad_where (fixP->fx_file, fixP->fx_line, 18172 _("offset out of range")); 18173 break; 18174 } 18175 newval &= ~0xfff; 18176 } 18177 else if ((newval & 0x00000100) == 0x00000100) 18178 { 18179 /* Writeback: 8-bit, +/- offset. */ 18180 if (value >= 0) 18181 newval |= (1 << 9); 18182 else 18183 value = -value; 18184 if (value > 0xff) 18185 { 18186 as_bad_where (fixP->fx_file, fixP->fx_line, 18187 _("offset out of range")); 18188 break; 18189 } 18190 newval &= ~0xff; 18191 } 18192 else if ((newval & 0x00000f00) == 0x00000e00) 18193 { 18194 /* T-instruction: positive 8-bit offset. */ 18195 if (value < 0 || value > 0xff) 18196 { 18197 as_bad_where (fixP->fx_file, fixP->fx_line, 18198 _("offset out of range")); 18199 break; 18200 } 18201 newval &= ~0xff; 18202 newval |= value; 18203 } 18204 else 18205 { 18206 /* Positive 12-bit or negative 8-bit offset. */ 18207 int limit; 18208 if (value >= 0) 18209 { 18210 newval |= (1 << 23); 18211 limit = 0xfff; 18212 } 18213 else 18214 { 18215 value = -value; 18216 limit = 0xff; 18217 } 18218 if (value > limit) 18219 { 18220 as_bad_where (fixP->fx_file, fixP->fx_line, 18221 _("offset out of range")); 18222 break; 18223 } 18224 newval &= ~limit; 18225 } 18226 18227 newval |= value; 18228 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE); 18229 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE); 18230 break; 18231 18232 case BFD_RELOC_ARM_SHIFT_IMM: 18233 newval = md_chars_to_number (buf, INSN_SIZE); 18234 if (((unsigned long) value) > 32 18235 || (value == 32 18236 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60))) 18237 { 18238 as_bad_where (fixP->fx_file, fixP->fx_line, 18239 _("shift expression is too large")); 18240 break; 18241 } 18242 18243 if (value == 0) 18244 /* Shifts of zero must be done as lsl. */ 18245 newval &= ~0x60; 18246 else if (value == 32) 18247 value = 0; 18248 newval &= 0xfffff07f; 18249 newval |= (value & 0x1f) << 7; 18250 md_number_to_chars (buf, newval, INSN_SIZE); 18251 break; 18252 18253 case BFD_RELOC_ARM_T32_IMMEDIATE: 18254 case BFD_RELOC_ARM_T32_ADD_IMM: 18255 case BFD_RELOC_ARM_T32_IMM12: 18256 case BFD_RELOC_ARM_T32_ADD_PC12: 18257 /* We claim that this fixup has been processed here, 18258 even if in fact we generate an error because we do 18259 not have a reloc for it, so tc_gen_reloc will reject it. */ 18260 fixP->fx_done = 1; 18261 18262 if (fixP->fx_addsy 18263 && ! S_IS_DEFINED (fixP->fx_addsy)) 18264 { 18265 as_bad_where (fixP->fx_file, fixP->fx_line, 18266 _("undefined symbol %s used as an immediate value"), 18267 S_GET_NAME (fixP->fx_addsy)); 18268 break; 18269 } 18270 18271 newval = md_chars_to_number (buf, THUMB_SIZE); 18272 newval <<= 16; 18273 newval |= md_chars_to_number (buf+2, THUMB_SIZE); 18274 18275 newimm = FAIL; 18276 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 18277 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18278 { 18279 newimm = encode_thumb32_immediate (value); 18280 if (newimm == (unsigned int) FAIL) 18281 newimm = thumb32_negate_data_op (&newval, value); 18282 } 18283 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE 18284 && newimm == (unsigned int) FAIL) 18285 { 18286 /* Turn add/sum into addw/subw. */ 18287 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM) 18288 newval = (newval & 0xfeffffff) | 0x02000000; 18289 18290 /* 12 bit immediate for addw/subw. */ 18291 if (value < 0) 18292 { 18293 value = -value; 18294 newval ^= 0x00a00000; 18295 } 18296 if (value > 0xfff) 18297 newimm = (unsigned int) FAIL; 18298 else 18299 newimm = value; 18300 } 18301 18302 if (newimm == (unsigned int)FAIL) 18303 { 18304 as_bad_where (fixP->fx_file, fixP->fx_line, 18305 _("invalid constant (%lx) after fixup"), 18306 (unsigned long) value); 18307 break; 18308 } 18309 18310 newval |= (newimm & 0x800) << 15; 18311 newval |= (newimm & 0x700) << 4; 18312 newval |= (newimm & 0x0ff); 18313 18314 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE); 18315 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE); 18316 break; 18317 18318 case BFD_RELOC_ARM_SMC: 18319 if (((unsigned long) value) > 0xffff) 18320 as_bad_where (fixP->fx_file, fixP->fx_line, 18321 _("invalid smc expression")); 18322 newval = md_chars_to_number (buf, INSN_SIZE); 18323 newval |= (value & 0xf) | ((value & 0xfff0) << 4); 18324 md_number_to_chars (buf, newval, INSN_SIZE); 18325 break; 18326 18327 case BFD_RELOC_ARM_SWI: 18328 if (fixP->tc_fix_data != 0) 18329 { 18330 if (((unsigned long) value) > 0xff) 18331 as_bad_where (fixP->fx_file, fixP->fx_line, 18332 _("invalid swi expression")); 18333 newval = md_chars_to_number (buf, THUMB_SIZE); 18334 newval |= value; 18335 md_number_to_chars (buf, newval, THUMB_SIZE); 18336 } 18337 else 18338 { 18339 if (((unsigned long) value) > 0x00ffffff) 18340 as_bad_where (fixP->fx_file, fixP->fx_line, 18341 _("invalid swi expression")); 18342 newval = md_chars_to_number (buf, INSN_SIZE); 18343 newval |= value; 18344 md_number_to_chars (buf, newval, INSN_SIZE); 18345 } 18346 break; 18347 18348 case BFD_RELOC_ARM_MULTI: 18349 if (((unsigned long) value) > 0xffff) 18350 as_bad_where (fixP->fx_file, fixP->fx_line, 18351 _("invalid expression in load/store multiple")); 18352 newval = value | md_chars_to_number (buf, INSN_SIZE); 18353 md_number_to_chars (buf, newval, INSN_SIZE); 18354 break; 18355 18356#ifdef OBJ_ELF 18357 case BFD_RELOC_ARM_PCREL_CALL: 18358 newval = md_chars_to_number (buf, INSN_SIZE); 18359 if ((newval & 0xf0000000) == 0xf0000000) 18360 temp = 1; 18361 else 18362 temp = 3; 18363 goto arm_branch_common; 18364 18365 case BFD_RELOC_ARM_PCREL_JUMP: 18366 case BFD_RELOC_ARM_PLT32: 18367#endif 18368 case BFD_RELOC_ARM_PCREL_BRANCH: 18369 temp = 3; 18370 goto arm_branch_common; 18371 18372 case BFD_RELOC_ARM_PCREL_BLX: 18373 temp = 1; 18374 arm_branch_common: 18375 /* We are going to store value (shifted right by two) in the 18376 instruction, in a 24 bit, signed field. Bits 26 through 32 either 18377 all clear or all set and bit 0 must be clear. For B/BL bit 1 must 18378 also be be clear. */ 18379 if (value & temp) 18380 as_bad_where (fixP->fx_file, fixP->fx_line, 18381 _("misaligned branch destination")); 18382 if ((value & (offsetT)0xfe000000) != (offsetT)0 18383 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) 18384 as_bad_where (fixP->fx_file, fixP->fx_line, 18385 _("branch out of range")); 18386 18387 if (fixP->fx_done || !seg->use_rela_p) 18388 { 18389 newval = md_chars_to_number (buf, INSN_SIZE); 18390 newval |= (value >> 2) & 0x00ffffff; 18391 /* Set the H bit on BLX instructions. */ 18392 if (temp == 1) 18393 { 18394 if (value & 2) 18395 newval |= 0x01000000; 18396 else 18397 newval &= ~0x01000000; 18398 } 18399 md_number_to_chars (buf, newval, INSN_SIZE); 18400 } 18401 break; 18402 18403 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */ 18404 /* CBZ can only branch forward. */ 18405 18406 /* Attempts to use CBZ to branch to the next instruction 18407 (which, strictly speaking, are prohibited) will be turned into 18408 no-ops. 18409 18410 FIXME: It may be better to remove the instruction completely and 18411 perform relaxation. */ 18412 if (value == -2) 18413 { 18414 newval = md_chars_to_number (buf, THUMB_SIZE); 18415 newval = 0xbf00; /* NOP encoding T1 */ 18416 md_number_to_chars (buf, newval, THUMB_SIZE); 18417 } 18418 else 18419 { 18420 if (value & ~0x7e) 18421 as_bad_where (fixP->fx_file, fixP->fx_line, 18422 _("branch out of range")); 18423 18424 if (fixP->fx_done || !seg->use_rela_p) 18425 { 18426 newval = md_chars_to_number (buf, THUMB_SIZE); 18427 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3); 18428 md_number_to_chars (buf, newval, THUMB_SIZE); 18429 } 18430 } 18431 break; 18432 18433 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ 18434 if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) 18435 as_bad_where (fixP->fx_file, fixP->fx_line, 18436 _("branch out of range")); 18437 18438 if (fixP->fx_done || !seg->use_rela_p) 18439 { 18440 newval = md_chars_to_number (buf, THUMB_SIZE); 18441 newval |= (value & 0x1ff) >> 1; 18442 md_number_to_chars (buf, newval, THUMB_SIZE); 18443 } 18444 break; 18445 18446 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ 18447 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) 18448 as_bad_where (fixP->fx_file, fixP->fx_line, 18449 _("branch out of range")); 18450 18451 if (fixP->fx_done || !seg->use_rela_p) 18452 { 18453 newval = md_chars_to_number (buf, THUMB_SIZE); 18454 newval |= (value & 0xfff) >> 1; 18455 md_number_to_chars (buf, newval, THUMB_SIZE); 18456 } 18457 break; 18458 18459 case BFD_RELOC_THUMB_PCREL_BRANCH20: 18460 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) 18461 as_bad_where (fixP->fx_file, fixP->fx_line, 18462 _("conditional branch out of range")); 18463 18464 if (fixP->fx_done || !seg->use_rela_p) 18465 { 18466 offsetT newval2; 18467 addressT S, J1, J2, lo, hi; 18468 18469 S = (value & 0x00100000) >> 20; 18470 J2 = (value & 0x00080000) >> 19; 18471 J1 = (value & 0x00040000) >> 18; 18472 hi = (value & 0x0003f000) >> 12; 18473 lo = (value & 0x00000ffe) >> 1; 18474 18475 newval = md_chars_to_number (buf, THUMB_SIZE); 18476 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18477 newval |= (S << 10) | hi; 18478 newval2 |= (J1 << 13) | (J2 << 11) | lo; 18479 md_number_to_chars (buf, newval, THUMB_SIZE); 18480 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18481 } 18482 break; 18483 18484 case BFD_RELOC_THUMB_PCREL_BLX: 18485 case BFD_RELOC_THUMB_PCREL_BRANCH23: 18486 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) 18487 as_bad_where (fixP->fx_file, fixP->fx_line, 18488 _("branch out of range")); 18489 18490 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) 18491 /* For a BLX instruction, make sure that the relocation is rounded up 18492 to a word boundary. This follows the semantics of the instruction 18493 which specifies that bit 1 of the target address will come from bit 18494 1 of the base address. */ 18495 value = (value + 1) & ~ 1; 18496 18497 if (fixP->fx_done || !seg->use_rela_p) 18498 { 18499 offsetT newval2; 18500 18501 newval = md_chars_to_number (buf, THUMB_SIZE); 18502 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18503 newval |= (value & 0x7fffff) >> 12; 18504 newval2 |= (value & 0xfff) >> 1; 18505 md_number_to_chars (buf, newval, THUMB_SIZE); 18506 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18507 } 18508 break; 18509 18510 case BFD_RELOC_THUMB_PCREL_BRANCH25: 18511 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) 18512 as_bad_where (fixP->fx_file, fixP->fx_line, 18513 _("branch out of range")); 18514 18515 if (fixP->fx_done || !seg->use_rela_p) 18516 { 18517 offsetT newval2; 18518 addressT S, I1, I2, lo, hi; 18519 18520 S = (value & 0x01000000) >> 24; 18521 I1 = (value & 0x00800000) >> 23; 18522 I2 = (value & 0x00400000) >> 22; 18523 hi = (value & 0x003ff000) >> 12; 18524 lo = (value & 0x00000ffe) >> 1; 18525 18526 I1 = !(I1 ^ S); 18527 I2 = !(I2 ^ S); 18528 18529 newval = md_chars_to_number (buf, THUMB_SIZE); 18530 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); 18531 newval |= (S << 10) | hi; 18532 newval2 |= (I1 << 13) | (I2 << 11) | lo; 18533 md_number_to_chars (buf, newval, THUMB_SIZE); 18534 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); 18535 } 18536 break; 18537 18538 case BFD_RELOC_8: 18539 if (fixP->fx_done || !seg->use_rela_p) 18540 md_number_to_chars (buf, value, 1); 18541 break; 18542 18543 case BFD_RELOC_16: 18544 if (fixP->fx_done || !seg->use_rela_p) 18545 md_number_to_chars (buf, value, 2); 18546 break; 18547 18548#ifdef OBJ_ELF 18549 case BFD_RELOC_ARM_TLS_GD32: 18550 case BFD_RELOC_ARM_TLS_LE32: 18551 case BFD_RELOC_ARM_TLS_IE32: 18552 case BFD_RELOC_ARM_TLS_LDM32: 18553 case BFD_RELOC_ARM_TLS_LDO32: 18554 S_SET_THREAD_LOCAL (fixP->fx_addsy); 18555 /* fall through */ 18556 18557 case BFD_RELOC_ARM_GOT32: 18558 case BFD_RELOC_ARM_GOTOFF: 18559 case BFD_RELOC_ARM_TARGET2: 18560 if (fixP->fx_done || !seg->use_rela_p) 18561 md_number_to_chars (buf, 0, 4); 18562 break; 18563#endif 18564 18565 case BFD_RELOC_RVA: 18566 case BFD_RELOC_32: 18567 case BFD_RELOC_ARM_TARGET1: 18568 case BFD_RELOC_ARM_ROSEGREL32: 18569 case BFD_RELOC_ARM_SBREL32: 18570 case BFD_RELOC_32_PCREL: 18571#ifdef TE_PE 18572 case BFD_RELOC_32_SECREL: 18573#endif 18574 if (fixP->fx_done || !seg->use_rela_p) 18575#ifdef TE_WINCE 18576 /* For WinCE we only do this for pcrel fixups. */ 18577 if (fixP->fx_done || fixP->fx_pcrel) 18578#endif 18579 md_number_to_chars (buf, value, 4); 18580 break; 18581 18582#ifdef OBJ_ELF 18583 case BFD_RELOC_ARM_PREL31: 18584 if (fixP->fx_done || !seg->use_rela_p) 18585 { 18586 newval = md_chars_to_number (buf, 4) & 0x80000000; 18587 if ((value ^ (value >> 1)) & 0x40000000) 18588 { 18589 as_bad_where (fixP->fx_file, fixP->fx_line, 18590 _("rel31 relocation overflow")); 18591 } 18592 newval |= value & 0x7fffffff; 18593 md_number_to_chars (buf, newval, 4); 18594 } 18595 break; 18596#endif 18597 18598 case BFD_RELOC_ARM_CP_OFF_IMM: 18599 case BFD_RELOC_ARM_T32_CP_OFF_IMM: 18600 if (value < -1023 || value > 1023 || (value & 3)) 18601 as_bad_where (fixP->fx_file, fixP->fx_line, 18602 _("co-processor offset out of range")); 18603 cp_off_common: 18604 sign = value >= 0; 18605 if (value < 0) 18606 value = -value; 18607 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18608 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18609 newval = md_chars_to_number (buf, INSN_SIZE); 18610 else 18611 newval = get_thumb32_insn (buf); 18612 newval &= 0xff7fff00; 18613 newval |= (value >> 2) | (sign ? INDEX_UP : 0); 18614 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM 18615 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2) 18616 md_number_to_chars (buf, newval, INSN_SIZE); 18617 else 18618 put_thumb32_insn (buf, newval); 18619 break; 18620 18621 case BFD_RELOC_ARM_CP_OFF_IMM_S2: 18622 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2: 18623 if (value < -255 || value > 255) 18624 as_bad_where (fixP->fx_file, fixP->fx_line, 18625 _("co-processor offset out of range")); 18626 value *= 4; 18627 goto cp_off_common; 18628 18629 case BFD_RELOC_ARM_THUMB_OFFSET: 18630 newval = md_chars_to_number (buf, THUMB_SIZE); 18631 /* Exactly what ranges, and where the offset is inserted depends 18632 on the type of instruction, we can establish this from the 18633 top 4 bits. */ 18634 switch (newval >> 12) 18635 { 18636 case 4: /* PC load. */ 18637 /* Thumb PC loads are somewhat odd, bit 1 of the PC is 18638 forced to zero for these loads; md_pcrel_from has already 18639 compensated for this. */ 18640 if (value & 3) 18641 as_bad_where (fixP->fx_file, fixP->fx_line, 18642 _("invalid offset, target not word aligned (0x%08lX)"), 18643 (((unsigned long) fixP->fx_frag->fr_address 18644 + (unsigned long) fixP->fx_where) & ~3) 18645 + (unsigned long) value); 18646 18647 if (value & ~0x3fc) 18648 as_bad_where (fixP->fx_file, fixP->fx_line, 18649 _("invalid offset, value too big (0x%08lX)"), 18650 (long) value); 18651 18652 newval |= value >> 2; 18653 break; 18654 18655 case 9: /* SP load/store. */ 18656 if (value & ~0x3fc) 18657 as_bad_where (fixP->fx_file, fixP->fx_line, 18658 _("invalid offset, value too big (0x%08lX)"), 18659 (long) value); 18660 newval |= value >> 2; 18661 break; 18662 18663 case 6: /* Word load/store. */ 18664 if (value & ~0x7c) 18665 as_bad_where (fixP->fx_file, fixP->fx_line, 18666 _("invalid offset, value too big (0x%08lX)"), 18667 (long) value); 18668 newval |= value << 4; /* 6 - 2. */ 18669 break; 18670 18671 case 7: /* Byte load/store. */ 18672 if (value & ~0x1f) 18673 as_bad_where (fixP->fx_file, fixP->fx_line, 18674 _("invalid offset, value too big (0x%08lX)"), 18675 (long) value); 18676 newval |= value << 6; 18677 break; 18678 18679 case 8: /* Halfword load/store. */ 18680 if (value & ~0x3e) 18681 as_bad_where (fixP->fx_file, fixP->fx_line, 18682 _("invalid offset, value too big (0x%08lX)"), 18683 (long) value); 18684 newval |= value << 5; /* 6 - 1. */ 18685 break; 18686 18687 default: 18688 as_bad_where (fixP->fx_file, fixP->fx_line, 18689 "Unable to process relocation for thumb opcode: %lx", 18690 (unsigned long) newval); 18691 break; 18692 } 18693 md_number_to_chars (buf, newval, THUMB_SIZE); 18694 break; 18695 18696 case BFD_RELOC_ARM_THUMB_ADD: 18697 /* This is a complicated relocation, since we use it for all of 18698 the following immediate relocations: 18699 18700 3bit ADD/SUB 18701 8bit ADD/SUB 18702 9bit ADD/SUB SP word-aligned 18703 10bit ADD PC/SP word-aligned 18704 18705 The type of instruction being processed is encoded in the 18706 instruction field: 18707 18708 0x8000 SUB 18709 0x00F0 Rd 18710 0x000F Rs 18711 */ 18712 newval = md_chars_to_number (buf, THUMB_SIZE); 18713 { 18714 int rd = (newval >> 4) & 0xf; 18715 int rs = newval & 0xf; 18716 int subtract = !!(newval & 0x8000); 18717 18718 /* Check for HI regs, only very restricted cases allowed: 18719 Adjusting SP, and using PC or SP to get an address. */ 18720 if ((rd > 7 && (rd != REG_SP || rs != REG_SP)) 18721 || (rs > 7 && rs != REG_SP && rs != REG_PC)) 18722 as_bad_where (fixP->fx_file, fixP->fx_line, 18723 _("invalid Hi register with immediate")); 18724 18725 /* If value is negative, choose the opposite instruction. */ 18726 if (value < 0) 18727 { 18728 value = -value; 18729 subtract = !subtract; 18730 if (value < 0) 18731 as_bad_where (fixP->fx_file, fixP->fx_line, 18732 _("immediate value out of range")); 18733 } 18734 18735 if (rd == REG_SP) 18736 { 18737 if (value & ~0x1fc) 18738 as_bad_where (fixP->fx_file, fixP->fx_line, 18739 _("invalid immediate for stack address calculation")); 18740 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST; 18741 newval |= value >> 2; 18742 } 18743 else if (rs == REG_PC || rs == REG_SP) 18744 { 18745 if (subtract || value & ~0x3fc) 18746 as_bad_where (fixP->fx_file, fixP->fx_line, 18747 _("invalid immediate for address calculation (value = 0x%08lX)"), 18748 (unsigned long) value); 18749 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP); 18750 newval |= rd << 8; 18751 newval |= value >> 2; 18752 } 18753 else if (rs == rd) 18754 { 18755 if (value & ~0xff) 18756 as_bad_where (fixP->fx_file, fixP->fx_line, 18757 _("immediate value out of range")); 18758 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8; 18759 newval |= (rd << 8) | value; 18760 } 18761 else 18762 { 18763 if (value & ~0x7) 18764 as_bad_where (fixP->fx_file, fixP->fx_line, 18765 _("immediate value out of range")); 18766 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3; 18767 newval |= rd | (rs << 3) | (value << 6); 18768 } 18769 } 18770 md_number_to_chars (buf, newval, THUMB_SIZE); 18771 break; 18772 18773 case BFD_RELOC_ARM_THUMB_IMM: 18774 newval = md_chars_to_number (buf, THUMB_SIZE); 18775 if (value < 0 || value > 255) 18776 as_bad_where (fixP->fx_file, fixP->fx_line, 18777 _("invalid immediate: %ld is too large"), 18778 (long) value); 18779 newval |= value; 18780 md_number_to_chars (buf, newval, THUMB_SIZE); 18781 break; 18782 18783 case BFD_RELOC_ARM_THUMB_SHIFT: 18784 /* 5bit shift value (0..32). LSL cannot take 32. */ 18785 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f; 18786 temp = newval & 0xf800; 18787 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I)) 18788 as_bad_where (fixP->fx_file, fixP->fx_line, 18789 _("invalid shift value: %ld"), (long) value); 18790 /* Shifts of zero must be encoded as LSL. */ 18791 if (value == 0) 18792 newval = (newval & 0x003f) | T_OPCODE_LSL_I; 18793 /* Shifts of 32 are encoded as zero. */ 18794 else if (value == 32) 18795 value = 0; 18796 newval |= value << 6; 18797 md_number_to_chars (buf, newval, THUMB_SIZE); 18798 break; 18799 18800 case BFD_RELOC_VTABLE_INHERIT: 18801 case BFD_RELOC_VTABLE_ENTRY: 18802 fixP->fx_done = 0; 18803 return; 18804 18805 case BFD_RELOC_ARM_MOVW: 18806 case BFD_RELOC_ARM_MOVT: 18807 case BFD_RELOC_ARM_THUMB_MOVW: 18808 case BFD_RELOC_ARM_THUMB_MOVT: 18809 if (fixP->fx_done || !seg->use_rela_p) 18810 { 18811 /* REL format relocations are limited to a 16-bit addend. */ 18812 if (!fixP->fx_done) 18813 { 18814 if (value < -0x1000 || value > 0xffff) 18815 as_bad_where (fixP->fx_file, fixP->fx_line, 18816 _("offset too big")); 18817 } 18818 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT 18819 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18820 { 18821 value >>= 16; 18822 } 18823 18824 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 18825 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 18826 { 18827 newval = get_thumb32_insn (buf); 18828 newval &= 0xfbf08f00; 18829 newval |= (value & 0xf000) << 4; 18830 newval |= (value & 0x0800) << 15; 18831 newval |= (value & 0x0700) << 4; 18832 newval |= (value & 0x00ff); 18833 put_thumb32_insn (buf, newval); 18834 } 18835 else 18836 { 18837 newval = md_chars_to_number (buf, 4); 18838 newval &= 0xfff0f000; 18839 newval |= value & 0x0fff; 18840 newval |= (value & 0xf000) << 4; 18841 md_number_to_chars (buf, newval, 4); 18842 } 18843 } 18844 return; 18845 18846 case BFD_RELOC_ARM_ALU_PC_G0_NC: 18847 case BFD_RELOC_ARM_ALU_PC_G0: 18848 case BFD_RELOC_ARM_ALU_PC_G1_NC: 18849 case BFD_RELOC_ARM_ALU_PC_G1: 18850 case BFD_RELOC_ARM_ALU_PC_G2: 18851 case BFD_RELOC_ARM_ALU_SB_G0_NC: 18852 case BFD_RELOC_ARM_ALU_SB_G0: 18853 case BFD_RELOC_ARM_ALU_SB_G1_NC: 18854 case BFD_RELOC_ARM_ALU_SB_G1: 18855 case BFD_RELOC_ARM_ALU_SB_G2: 18856 assert (!fixP->fx_done); 18857 if (!seg->use_rela_p) 18858 { 18859 bfd_vma insn; 18860 bfd_vma encoded_addend; 18861 bfd_vma addend_abs = abs (value); 18862 18863 /* Check that the absolute value of the addend can be 18864 expressed as an 8-bit constant plus a rotation. */ 18865 encoded_addend = encode_arm_immediate (addend_abs); 18866 if (encoded_addend == (unsigned int) FAIL) 18867 as_bad_where (fixP->fx_file, fixP->fx_line, 18868 _("the offset 0x%08lX is not representable"), 18869 (unsigned long) addend_abs); 18870 18871 /* Extract the instruction. */ 18872 insn = md_chars_to_number (buf, INSN_SIZE); 18873 18874 /* If the addend is positive, use an ADD instruction. 18875 Otherwise use a SUB. Take care not to destroy the S bit. */ 18876 insn &= 0xff1fffff; 18877 if (value < 0) 18878 insn |= 1 << 22; 18879 else 18880 insn |= 1 << 23; 18881 18882 /* Place the encoded addend into the first 12 bits of the 18883 instruction. */ 18884 insn &= 0xfffff000; 18885 insn |= encoded_addend; 18886 18887 /* Update the instruction. */ 18888 md_number_to_chars (buf, insn, INSN_SIZE); 18889 } 18890 break; 18891 18892 case BFD_RELOC_ARM_LDR_PC_G0: 18893 case BFD_RELOC_ARM_LDR_PC_G1: 18894 case BFD_RELOC_ARM_LDR_PC_G2: 18895 case BFD_RELOC_ARM_LDR_SB_G0: 18896 case BFD_RELOC_ARM_LDR_SB_G1: 18897 case BFD_RELOC_ARM_LDR_SB_G2: 18898 assert (!fixP->fx_done); 18899 if (!seg->use_rela_p) 18900 { 18901 bfd_vma insn; 18902 bfd_vma addend_abs = abs (value); 18903 18904 /* Check that the absolute value of the addend can be 18905 encoded in 12 bits. */ 18906 if (addend_abs >= 0x1000) 18907 as_bad_where (fixP->fx_file, fixP->fx_line, 18908 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"), 18909 (unsigned long) addend_abs); 18910 18911 /* Extract the instruction. */ 18912 insn = md_chars_to_number (buf, INSN_SIZE); 18913 18914 /* If the addend is negative, clear bit 23 of the instruction. 18915 Otherwise set it. */ 18916 if (value < 0) 18917 insn &= ~(1 << 23); 18918 else 18919 insn |= 1 << 23; 18920 18921 /* Place the absolute value of the addend into the first 12 bits 18922 of the instruction. */ 18923 insn &= 0xfffff000; 18924 insn |= addend_abs; 18925 18926 /* Update the instruction. */ 18927 md_number_to_chars (buf, insn, INSN_SIZE); 18928 } 18929 break; 18930 18931 case BFD_RELOC_ARM_LDRS_PC_G0: 18932 case BFD_RELOC_ARM_LDRS_PC_G1: 18933 case BFD_RELOC_ARM_LDRS_PC_G2: 18934 case BFD_RELOC_ARM_LDRS_SB_G0: 18935 case BFD_RELOC_ARM_LDRS_SB_G1: 18936 case BFD_RELOC_ARM_LDRS_SB_G2: 18937 assert (!fixP->fx_done); 18938 if (!seg->use_rela_p) 18939 { 18940 bfd_vma insn; 18941 bfd_vma addend_abs = abs (value); 18942 18943 /* Check that the absolute value of the addend can be 18944 encoded in 8 bits. */ 18945 if (addend_abs >= 0x100) 18946 as_bad_where (fixP->fx_file, fixP->fx_line, 18947 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"), 18948 (unsigned long) addend_abs); 18949 18950 /* Extract the instruction. */ 18951 insn = md_chars_to_number (buf, INSN_SIZE); 18952 18953 /* If the addend is negative, clear bit 23 of the instruction. 18954 Otherwise set it. */ 18955 if (value < 0) 18956 insn &= ~(1 << 23); 18957 else 18958 insn |= 1 << 23; 18959 18960 /* Place the first four bits of the absolute value of the addend 18961 into the first 4 bits of the instruction, and the remaining 18962 four into bits 8 .. 11. */ 18963 insn &= 0xfffff0f0; 18964 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4); 18965 18966 /* Update the instruction. */ 18967 md_number_to_chars (buf, insn, INSN_SIZE); 18968 } 18969 break; 18970 18971 case BFD_RELOC_ARM_LDC_PC_G0: 18972 case BFD_RELOC_ARM_LDC_PC_G1: 18973 case BFD_RELOC_ARM_LDC_PC_G2: 18974 case BFD_RELOC_ARM_LDC_SB_G0: 18975 case BFD_RELOC_ARM_LDC_SB_G1: 18976 case BFD_RELOC_ARM_LDC_SB_G2: 18977 assert (!fixP->fx_done); 18978 if (!seg->use_rela_p) 18979 { 18980 bfd_vma insn; 18981 bfd_vma addend_abs = abs (value); 18982 18983 /* Check that the absolute value of the addend is a multiple of 18984 four and, when divided by four, fits in 8 bits. */ 18985 if (addend_abs & 0x3) 18986 as_bad_where (fixP->fx_file, fixP->fx_line, 18987 _("bad offset 0x%08lX (must be word-aligned)"), 18988 (unsigned long) addend_abs); 18989 18990 if ((addend_abs >> 2) > 0xff) 18991 as_bad_where (fixP->fx_file, fixP->fx_line, 18992 _("bad offset 0x%08lX (must be an 8-bit number of words)"), 18993 (unsigned long) addend_abs); 18994 18995 /* Extract the instruction. */ 18996 insn = md_chars_to_number (buf, INSN_SIZE); 18997 18998 /* If the addend is negative, clear bit 23 of the instruction. 18999 Otherwise set it. */ 19000 if (value < 0) 19001 insn &= ~(1 << 23); 19002 else 19003 insn |= 1 << 23; 19004 19005 /* Place the addend (divided by four) into the first eight 19006 bits of the instruction. */ 19007 insn &= 0xfffffff0; 19008 insn |= addend_abs >> 2; 19009 19010 /* Update the instruction. */ 19011 md_number_to_chars (buf, insn, INSN_SIZE); 19012 } 19013 break; 19014 19015 case BFD_RELOC_UNUSED: 19016 default: 19017 as_bad_where (fixP->fx_file, fixP->fx_line, 19018 _("bad relocation fixup type (%d)"), fixP->fx_r_type); 19019 } 19020} 19021 19022/* Translate internal representation of relocation info to BFD target 19023 format. */ 19024 19025arelent * 19026tc_gen_reloc (asection *section, fixS *fixp) 19027{ 19028 arelent * reloc; 19029 bfd_reloc_code_real_type code; 19030 19031 reloc = xmalloc (sizeof (arelent)); 19032 19033 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 19034 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 19035 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 19036 19037 if (fixp->fx_pcrel) 19038 { 19039 if (section->use_rela_p) 19040 fixp->fx_offset -= md_pcrel_from_section (fixp, section); 19041 else 19042 fixp->fx_offset = reloc->address; 19043 } 19044 reloc->addend = fixp->fx_offset; 19045 19046 switch (fixp->fx_r_type) 19047 { 19048 case BFD_RELOC_8: 19049 if (fixp->fx_pcrel) 19050 { 19051 code = BFD_RELOC_8_PCREL; 19052 break; 19053 } 19054 19055 case BFD_RELOC_16: 19056 if (fixp->fx_pcrel) 19057 { 19058 code = BFD_RELOC_16_PCREL; 19059 break; 19060 } 19061 19062 case BFD_RELOC_32: 19063 if (fixp->fx_pcrel) 19064 { 19065 code = BFD_RELOC_32_PCREL; 19066 break; 19067 } 19068 19069 case BFD_RELOC_ARM_MOVW: 19070 if (fixp->fx_pcrel) 19071 { 19072 code = BFD_RELOC_ARM_MOVW_PCREL; 19073 break; 19074 } 19075 19076 case BFD_RELOC_ARM_MOVT: 19077 if (fixp->fx_pcrel) 19078 { 19079 code = BFD_RELOC_ARM_MOVT_PCREL; 19080 break; 19081 } 19082 19083 case BFD_RELOC_ARM_THUMB_MOVW: 19084 if (fixp->fx_pcrel) 19085 { 19086 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL; 19087 break; 19088 } 19089 19090 case BFD_RELOC_ARM_THUMB_MOVT: 19091 if (fixp->fx_pcrel) 19092 { 19093 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL; 19094 break; 19095 } 19096 19097 case BFD_RELOC_NONE: 19098 case BFD_RELOC_ARM_PCREL_BRANCH: 19099 case BFD_RELOC_ARM_PCREL_BLX: 19100 case BFD_RELOC_RVA: 19101 case BFD_RELOC_THUMB_PCREL_BRANCH7: 19102 case BFD_RELOC_THUMB_PCREL_BRANCH9: 19103 case BFD_RELOC_THUMB_PCREL_BRANCH12: 19104 case BFD_RELOC_THUMB_PCREL_BRANCH20: 19105 case BFD_RELOC_THUMB_PCREL_BRANCH23: 19106 case BFD_RELOC_THUMB_PCREL_BRANCH25: 19107 case BFD_RELOC_THUMB_PCREL_BLX: 19108 case BFD_RELOC_VTABLE_ENTRY: 19109 case BFD_RELOC_VTABLE_INHERIT: 19110#ifdef TE_PE 19111 case BFD_RELOC_32_SECREL: 19112#endif 19113 code = fixp->fx_r_type; 19114 break; 19115 19116 case BFD_RELOC_ARM_LITERAL: 19117 case BFD_RELOC_ARM_HWLITERAL: 19118 /* If this is called then the a literal has 19119 been referenced across a section boundary. */ 19120 as_bad_where (fixp->fx_file, fixp->fx_line, 19121 _("literal referenced across section boundary")); 19122 return NULL; 19123 19124#ifdef OBJ_ELF 19125 case BFD_RELOC_ARM_GOT32: 19126 case BFD_RELOC_ARM_GOTOFF: 19127 case BFD_RELOC_ARM_PLT32: 19128 case BFD_RELOC_ARM_TARGET1: 19129 case BFD_RELOC_ARM_ROSEGREL32: 19130 case BFD_RELOC_ARM_SBREL32: 19131 case BFD_RELOC_ARM_PREL31: 19132 case BFD_RELOC_ARM_TARGET2: 19133 case BFD_RELOC_ARM_TLS_LE32: 19134 case BFD_RELOC_ARM_TLS_LDO32: 19135 case BFD_RELOC_ARM_PCREL_CALL: 19136 case BFD_RELOC_ARM_PCREL_JUMP: 19137 case BFD_RELOC_ARM_ALU_PC_G0_NC: 19138 case BFD_RELOC_ARM_ALU_PC_G0: 19139 case BFD_RELOC_ARM_ALU_PC_G1_NC: 19140 case BFD_RELOC_ARM_ALU_PC_G1: 19141 case BFD_RELOC_ARM_ALU_PC_G2: 19142 case BFD_RELOC_ARM_LDR_PC_G0: 19143 case BFD_RELOC_ARM_LDR_PC_G1: 19144 case BFD_RELOC_ARM_LDR_PC_G2: 19145 case BFD_RELOC_ARM_LDRS_PC_G0: 19146 case BFD_RELOC_ARM_LDRS_PC_G1: 19147 case BFD_RELOC_ARM_LDRS_PC_G2: 19148 case BFD_RELOC_ARM_LDC_PC_G0: 19149 case BFD_RELOC_ARM_LDC_PC_G1: 19150 case BFD_RELOC_ARM_LDC_PC_G2: 19151 case BFD_RELOC_ARM_ALU_SB_G0_NC: 19152 case BFD_RELOC_ARM_ALU_SB_G0: 19153 case BFD_RELOC_ARM_ALU_SB_G1_NC: 19154 case BFD_RELOC_ARM_ALU_SB_G1: 19155 case BFD_RELOC_ARM_ALU_SB_G2: 19156 case BFD_RELOC_ARM_LDR_SB_G0: 19157 case BFD_RELOC_ARM_LDR_SB_G1: 19158 case BFD_RELOC_ARM_LDR_SB_G2: 19159 case BFD_RELOC_ARM_LDRS_SB_G0: 19160 case BFD_RELOC_ARM_LDRS_SB_G1: 19161 case BFD_RELOC_ARM_LDRS_SB_G2: 19162 case BFD_RELOC_ARM_LDC_SB_G0: 19163 case BFD_RELOC_ARM_LDC_SB_G1: 19164 case BFD_RELOC_ARM_LDC_SB_G2: 19165 code = fixp->fx_r_type; 19166 break; 19167 19168 case BFD_RELOC_ARM_TLS_GD32: 19169 case BFD_RELOC_ARM_TLS_IE32: 19170 case BFD_RELOC_ARM_TLS_LDM32: 19171 /* BFD will include the symbol's address in the addend. 19172 But we don't want that, so subtract it out again here. */ 19173 if (!S_IS_COMMON (fixp->fx_addsy)) 19174 reloc->addend -= (*reloc->sym_ptr_ptr)->value; 19175 code = fixp->fx_r_type; 19176 break; 19177#endif 19178 19179 case BFD_RELOC_ARM_IMMEDIATE: 19180 as_bad_where (fixp->fx_file, fixp->fx_line, 19181 _("internal relocation (type: IMMEDIATE) not fixed up")); 19182 return NULL; 19183 19184 case BFD_RELOC_ARM_ADRL_IMMEDIATE: 19185 as_bad_where (fixp->fx_file, fixp->fx_line, 19186 _("ADRL used for a symbol not defined in the same file")); 19187 return NULL; 19188 19189 case BFD_RELOC_ARM_OFFSET_IMM: 19190 if (section->use_rela_p) 19191 { 19192 code = fixp->fx_r_type; 19193 break; 19194 } 19195 19196 if (fixp->fx_addsy != NULL 19197 && !S_IS_DEFINED (fixp->fx_addsy) 19198 && S_IS_LOCAL (fixp->fx_addsy)) 19199 { 19200 as_bad_where (fixp->fx_file, fixp->fx_line, 19201 _("undefined local label `%s'"), 19202 S_GET_NAME (fixp->fx_addsy)); 19203 return NULL; 19204 } 19205 19206 as_bad_where (fixp->fx_file, fixp->fx_line, 19207 _("internal_relocation (type: OFFSET_IMM) not fixed up")); 19208 return NULL; 19209 19210 default: 19211 { 19212 char * type; 19213 19214 switch (fixp->fx_r_type) 19215 { 19216 case BFD_RELOC_NONE: type = "NONE"; break; 19217 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break; 19218 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break; 19219 case BFD_RELOC_ARM_SMC: type = "SMC"; break; 19220 case BFD_RELOC_ARM_SWI: type = "SWI"; break; 19221 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break; 19222 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break; 19223 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break; 19224 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break; 19225 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break; 19226 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break; 19227 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break; 19228 default: type = _("<unknown>"); break; 19229 } 19230 as_bad_where (fixp->fx_file, fixp->fx_line, 19231 _("cannot represent %s relocation in this object file format"), 19232 type); 19233 return NULL; 19234 } 19235 } 19236 19237#ifdef OBJ_ELF 19238 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32) 19239 && GOT_symbol 19240 && fixp->fx_addsy == GOT_symbol) 19241 { 19242 code = BFD_RELOC_ARM_GOTPC; 19243 reloc->addend = fixp->fx_offset = reloc->address; 19244 } 19245#endif 19246 19247 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 19248 19249 if (reloc->howto == NULL) 19250 { 19251 as_bad_where (fixp->fx_file, fixp->fx_line, 19252 _("cannot represent %s relocation in this object file format"), 19253 bfd_get_reloc_code_name (code)); 19254 return NULL; 19255 } 19256 19257 /* HACK: Since arm ELF uses Rel instead of Rela, encode the 19258 vtable entry to be used in the relocation's section offset. */ 19259 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19260 reloc->address = fixp->fx_offset; 19261 19262 return reloc; 19263} 19264 19265/* This fix_new is called by cons via TC_CONS_FIX_NEW. */ 19266 19267void 19268cons_fix_new_arm (fragS * frag, 19269 int where, 19270 int size, 19271 expressionS * exp) 19272{ 19273 bfd_reloc_code_real_type type; 19274 int pcrel = 0; 19275 19276 /* Pick a reloc. 19277 FIXME: @@ Should look at CPU word size. */ 19278 switch (size) 19279 { 19280 case 1: 19281 type = BFD_RELOC_8; 19282 break; 19283 case 2: 19284 type = BFD_RELOC_16; 19285 break; 19286 case 4: 19287 default: 19288 type = BFD_RELOC_32; 19289 break; 19290 case 8: 19291 type = BFD_RELOC_64; 19292 break; 19293 } 19294 19295#ifdef TE_PE 19296 if (exp->X_op == O_secrel) 19297 { 19298 exp->X_op = O_symbol; 19299 type = BFD_RELOC_32_SECREL; 19300 } 19301#endif 19302 19303 fix_new_exp (frag, where, (int) size, exp, pcrel, type); 19304} 19305 19306#if defined OBJ_COFF || defined OBJ_ELF 19307void 19308arm_validate_fix (fixS * fixP) 19309{ 19310 /* If the destination of the branch is a defined symbol which does not have 19311 the THUMB_FUNC attribute, then we must be calling a function which has 19312 the (interfacearm) attribute. We look for the Thumb entry point to that 19313 function and change the branch to refer to that function instead. */ 19314 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23 19315 && fixP->fx_addsy != NULL 19316 && S_IS_DEFINED (fixP->fx_addsy) 19317 && ! THUMB_IS_FUNC (fixP->fx_addsy)) 19318 { 19319 fixP->fx_addsy = find_real_start (fixP->fx_addsy); 19320 } 19321} 19322#endif 19323 19324int 19325arm_force_relocation (struct fix * fixp) 19326{ 19327#if defined (OBJ_COFF) && defined (TE_PE) 19328 if (fixp->fx_r_type == BFD_RELOC_RVA) 19329 return 1; 19330#endif 19331 19332 /* Resolve these relocations even if the symbol is extern or weak. */ 19333 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE 19334 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM 19335 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE 19336 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM 19337 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE 19338 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12 19339 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12) 19340 return 0; 19341 19342 /* Always leave these relocations for the linker. */ 19343 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19344 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19345 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19346 return 1; 19347 19348 /* Always generate relocations against function symbols. */ 19349 if (fixp->fx_r_type == BFD_RELOC_32 19350 && fixp->fx_addsy 19351 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)) 19352 return 1; 19353 19354 return generic_force_reloc (fixp); 19355} 19356 19357#if defined (OBJ_ELF) || defined (OBJ_COFF) 19358/* Relocations against function names must be left unadjusted, 19359 so that the linker can use this information to generate interworking 19360 stubs. The MIPS version of this function 19361 also prevents relocations that are mips-16 specific, but I do not 19362 know why it does this. 19363 19364 FIXME: 19365 There is one other problem that ought to be addressed here, but 19366 which currently is not: Taking the address of a label (rather 19367 than a function) and then later jumping to that address. Such 19368 addresses also ought to have their bottom bit set (assuming that 19369 they reside in Thumb code), but at the moment they will not. */ 19370 19371bfd_boolean 19372arm_fix_adjustable (fixS * fixP) 19373{ 19374 if (fixP->fx_addsy == NULL) 19375 return 1; 19376 19377 /* Preserve relocations against symbols with function type. */ 19378 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION) 19379 return 0; 19380 19381 if (THUMB_IS_FUNC (fixP->fx_addsy) 19382 && fixP->fx_subsy == NULL) 19383 return 0; 19384 19385 /* We need the symbol name for the VTABLE entries. */ 19386 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 19387 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 19388 return 0; 19389 19390 /* Don't allow symbols to be discarded on GOT related relocs. */ 19391 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32 19392 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32 19393 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF 19394 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32 19395 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32 19396 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32 19397 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32 19398 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32 19399 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2) 19400 return 0; 19401 19402 /* Similarly for group relocations. */ 19403 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC 19404 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2) 19405 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0) 19406 return 0; 19407 19408 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW 19409 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT 19410 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW 19411 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT) 19412 return 0; 19413 19414 return 1; 19415} 19416#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */ 19417 19418#ifdef OBJ_ELF 19419 19420const char * 19421elf32_arm_target_format (void) 19422{ 19423#ifdef TE_SYMBIAN 19424 return (target_big_endian 19425 ? "elf32-bigarm-symbian" 19426 : "elf32-littlearm-symbian"); 19427#elif defined (TE_VXWORKS) 19428 return (target_big_endian 19429 ? "elf32-bigarm-vxworks" 19430 : "elf32-littlearm-vxworks"); 19431#else 19432 if (target_big_endian) 19433 return "elf32-bigarm"; 19434 else 19435 return "elf32-littlearm"; 19436#endif 19437} 19438 19439void 19440armelf_frob_symbol (symbolS * symp, 19441 int * puntp) 19442{ 19443 elf_frob_symbol (symp, puntp); 19444} 19445#endif 19446 19447/* MD interface: Finalization. */ 19448 19449/* A good place to do this, although this was probably not intended 19450 for this kind of use. We need to dump the literal pool before 19451 references are made to a null symbol pointer. */ 19452 19453void 19454arm_cleanup (void) 19455{ 19456 literal_pool * pool; 19457 19458 for (pool = list_of_pools; pool; pool = pool->next) 19459 { 19460 /* Put it at the end of the relevent section. */ 19461 subseg_set (pool->section, pool->sub_section); 19462#ifdef OBJ_ELF 19463 arm_elf_change_section (); 19464#endif 19465 s_ltorg (0); 19466 } 19467} 19468 19469/* Adjust the symbol table. This marks Thumb symbols as distinct from 19470 ARM ones. */ 19471 19472void 19473arm_adjust_symtab (void) 19474{ 19475#ifdef OBJ_COFF 19476 symbolS * sym; 19477 19478 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19479 { 19480 if (ARM_IS_THUMB (sym)) 19481 { 19482 if (THUMB_IS_FUNC (sym)) 19483 { 19484 /* Mark the symbol as a Thumb function. */ 19485 if ( S_GET_STORAGE_CLASS (sym) == C_STAT 19486 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */ 19487 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC); 19488 19489 else if (S_GET_STORAGE_CLASS (sym) == C_EXT) 19490 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC); 19491 else 19492 as_bad (_("%s: unexpected function type: %d"), 19493 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym)); 19494 } 19495 else switch (S_GET_STORAGE_CLASS (sym)) 19496 { 19497 case C_EXT: 19498 S_SET_STORAGE_CLASS (sym, C_THUMBEXT); 19499 break; 19500 case C_STAT: 19501 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT); 19502 break; 19503 case C_LABEL: 19504 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL); 19505 break; 19506 default: 19507 /* Do nothing. */ 19508 break; 19509 } 19510 } 19511 19512 if (ARM_IS_INTERWORK (sym)) 19513 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF; 19514 } 19515#endif 19516#ifdef OBJ_ELF 19517 symbolS * sym; 19518 char bind; 19519 19520 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 19521 { 19522 if (ARM_IS_THUMB (sym)) 19523 { 19524 elf_symbol_type * elf_sym; 19525 19526 elf_sym = elf_symbol (symbol_get_bfdsym (sym)); 19527 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info); 19528 19529 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name, 19530 BFD_ARM_SPECIAL_SYM_TYPE_ANY)) 19531 { 19532 /* If it's a .thumb_func, declare it as so, 19533 otherwise tag label as .code 16. */ 19534 if (THUMB_IS_FUNC (sym)) 19535 elf_sym->internal_elf_sym.st_info = 19536 ELF_ST_INFO (bind, STT_ARM_TFUNC); 19537 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 19538 elf_sym->internal_elf_sym.st_info = 19539 ELF_ST_INFO (bind, STT_ARM_16BIT); 19540 } 19541 } 19542 } 19543#endif 19544} 19545 19546/* MD interface: Initialization. */ 19547 19548static void 19549set_constant_flonums (void) 19550{ 19551 int i; 19552 19553 for (i = 0; i < NUM_FLOAT_VALS; i++) 19554 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL) 19555 abort (); 19556} 19557 19558/* Auto-select Thumb mode if it's the only available instruction set for the 19559 given architecture. */ 19560 19561static void 19562autoselect_thumb_from_cpu_variant (void) 19563{ 19564 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)) 19565 opcode_select (16); 19566} 19567 19568void 19569md_begin (void) 19570{ 19571 unsigned mach; 19572 unsigned int i; 19573 19574 if ( (arm_ops_hsh = hash_new ()) == NULL 19575 || (arm_cond_hsh = hash_new ()) == NULL 19576 || (arm_shift_hsh = hash_new ()) == NULL 19577 || (arm_psr_hsh = hash_new ()) == NULL 19578 || (arm_v7m_psr_hsh = hash_new ()) == NULL 19579 || (arm_reg_hsh = hash_new ()) == NULL 19580 || (arm_reloc_hsh = hash_new ()) == NULL 19581 || (arm_barrier_opt_hsh = hash_new ()) == NULL) 19582 as_fatal (_("virtual memory exhausted")); 19583 19584 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++) 19585 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i)); 19586 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++) 19587 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i)); 19588 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++) 19589 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i)); 19590 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++) 19591 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i)); 19592 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++) 19593 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i)); 19594 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++) 19595 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i)); 19596 for (i = 0; 19597 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt); 19598 i++) 19599 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template, 19600 (PTR) (barrier_opt_names + i)); 19601#ifdef OBJ_ELF 19602 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++) 19603 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i)); 19604#endif 19605 19606 set_constant_flonums (); 19607 19608 /* Set the cpu variant based on the command-line options. We prefer 19609 -mcpu= over -march= if both are set (as for GCC); and we prefer 19610 -mfpu= over any other way of setting the floating point unit. 19611 Use of legacy options with new options are faulted. */ 19612 if (legacy_cpu) 19613 { 19614 if (mcpu_cpu_opt || march_cpu_opt) 19615 as_bad (_("use of old and new-style options to set CPU type")); 19616 19617 mcpu_cpu_opt = legacy_cpu; 19618 } 19619 else if (!mcpu_cpu_opt) 19620 mcpu_cpu_opt = march_cpu_opt; 19621 19622 if (legacy_fpu) 19623 { 19624 if (mfpu_opt) 19625 as_bad (_("use of old and new-style options to set FPU type")); 19626 19627 mfpu_opt = legacy_fpu; 19628 } 19629 else if (!mfpu_opt) 19630 { 19631#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS)) 19632 /* Some environments specify a default FPU. If they don't, infer it 19633 from the processor. */ 19634 if (mcpu_fpu_opt) 19635 mfpu_opt = mcpu_fpu_opt; 19636 else 19637 mfpu_opt = march_fpu_opt; 19638#else 19639 mfpu_opt = &fpu_default; 19640#endif 19641 } 19642 19643 if (!mfpu_opt) 19644 { 19645 if (mcpu_cpu_opt != NULL) 19646 mfpu_opt = &fpu_default; 19647 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5)) 19648 mfpu_opt = &fpu_arch_vfp_v2; 19649 else 19650 mfpu_opt = &fpu_arch_fpa; 19651 } 19652 19653#ifdef CPU_DEFAULT 19654 if (!mcpu_cpu_opt) 19655 { 19656 mcpu_cpu_opt = &cpu_default; 19657 selected_cpu = cpu_default; 19658 } 19659#else 19660 if (mcpu_cpu_opt) 19661 selected_cpu = *mcpu_cpu_opt; 19662 else 19663 mcpu_cpu_opt = &arm_arch_any; 19664#endif 19665 19666 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 19667 19668 autoselect_thumb_from_cpu_variant (); 19669 19670 arm_arch_used = thumb_arch_used = arm_arch_none; 19671 19672#if defined OBJ_COFF || defined OBJ_ELF 19673 { 19674 unsigned int flags = 0; 19675 19676#if defined OBJ_ELF 19677 flags = meabi_flags; 19678 19679 switch (meabi_flags) 19680 { 19681 case EF_ARM_EABI_UNKNOWN: 19682#endif 19683 /* Set the flags in the private structure. */ 19684 if (uses_apcs_26) flags |= F_APCS26; 19685 if (support_interwork) flags |= F_INTERWORK; 19686 if (uses_apcs_float) flags |= F_APCS_FLOAT; 19687 if (pic_code) flags |= F_PIC; 19688 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard)) 19689 flags |= F_SOFT_FLOAT; 19690 19691 switch (mfloat_abi_opt) 19692 { 19693 case ARM_FLOAT_ABI_SOFT: 19694 case ARM_FLOAT_ABI_SOFTFP: 19695 flags |= F_SOFT_FLOAT; 19696 break; 19697 19698 case ARM_FLOAT_ABI_HARD: 19699 if (flags & F_SOFT_FLOAT) 19700 as_bad (_("hard-float conflicts with specified fpu")); 19701 break; 19702 } 19703 19704 /* Using pure-endian doubles (even if soft-float). */ 19705 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure)) 19706 flags |= F_VFP_FLOAT; 19707 19708#if defined OBJ_ELF 19709 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick)) 19710 flags |= EF_ARM_MAVERICK_FLOAT; 19711 break; 19712 19713 case EF_ARM_EABI_VER4: 19714 case EF_ARM_EABI_VER5: 19715 /* No additional flags to set. */ 19716 break; 19717 19718 default: 19719 abort (); 19720 } 19721#endif 19722 bfd_set_private_flags (stdoutput, flags); 19723 19724 /* We have run out flags in the COFF header to encode the 19725 status of ATPCS support, so instead we create a dummy, 19726 empty, debug section called .arm.atpcs. */ 19727 if (atpcs) 19728 { 19729 asection * sec; 19730 19731 sec = bfd_make_section (stdoutput, ".arm.atpcs"); 19732 19733 if (sec != NULL) 19734 { 19735 bfd_set_section_flags 19736 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */); 19737 bfd_set_section_size (stdoutput, sec, 0); 19738 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0); 19739 } 19740 } 19741 } 19742#endif 19743 19744 /* Record the CPU type as well. */ 19745 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)) 19746 mach = bfd_mach_arm_iWMMXt2; 19747 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt)) 19748 mach = bfd_mach_arm_iWMMXt; 19749 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale)) 19750 mach = bfd_mach_arm_XScale; 19751 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick)) 19752 mach = bfd_mach_arm_ep9312; 19753 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e)) 19754 mach = bfd_mach_arm_5TE; 19755 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5)) 19756 { 19757 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19758 mach = bfd_mach_arm_5T; 19759 else 19760 mach = bfd_mach_arm_5; 19761 } 19762 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4)) 19763 { 19764 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t)) 19765 mach = bfd_mach_arm_4T; 19766 else 19767 mach = bfd_mach_arm_4; 19768 } 19769 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m)) 19770 mach = bfd_mach_arm_3M; 19771 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3)) 19772 mach = bfd_mach_arm_3; 19773 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s)) 19774 mach = bfd_mach_arm_2a; 19775 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2)) 19776 mach = bfd_mach_arm_2; 19777 else 19778 mach = bfd_mach_arm_unknown; 19779 19780 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach); 19781} 19782 19783/* Command line processing. */ 19784 19785/* md_parse_option 19786 Invocation line includes a switch not recognized by the base assembler. 19787 See if it's a processor-specific option. 19788 19789 This routine is somewhat complicated by the need for backwards 19790 compatibility (since older releases of gcc can't be changed). 19791 The new options try to make the interface as compatible as 19792 possible with GCC. 19793 19794 New options (supported) are: 19795 19796 -mcpu=<cpu name> Assemble for selected processor 19797 -march=<architecture name> Assemble for selected architecture 19798 -mfpu=<fpu architecture> Assemble for selected FPU. 19799 -EB/-mbig-endian Big-endian 19800 -EL/-mlittle-endian Little-endian 19801 -k Generate PIC code 19802 -mthumb Start in Thumb mode 19803 -mthumb-interwork Code supports ARM/Thumb interworking 19804 19805 For now we will also provide support for: 19806 19807 -mapcs-32 32-bit Program counter 19808 -mapcs-26 26-bit Program counter 19809 -macps-float Floats passed in FP registers 19810 -mapcs-reentrant Reentrant code 19811 -matpcs 19812 (sometime these will probably be replaced with -mapcs=<list of options> 19813 and -matpcs=<list of options>) 19814 19815 The remaining options are only supported for back-wards compatibility. 19816 Cpu variants, the arm part is optional: 19817 -m[arm]1 Currently not supported. 19818 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor 19819 -m[arm]3 Arm 3 processor 19820 -m[arm]6[xx], Arm 6 processors 19821 -m[arm]7[xx][t][[d]m] Arm 7 processors 19822 -m[arm]8[10] Arm 8 processors 19823 -m[arm]9[20][tdmi] Arm 9 processors 19824 -mstrongarm[110[0]] StrongARM processors 19825 -mxscale XScale processors 19826 -m[arm]v[2345[t[e]]] Arm architectures 19827 -mall All (except the ARM1) 19828 FP variants: 19829 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions 19830 -mfpe-old (No float load/store multiples) 19831 -mvfpxd VFP Single precision 19832 -mvfp All VFP 19833 -mno-fpu Disable all floating point instructions 19834 19835 The following CPU names are recognized: 19836 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620, 19837 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, 19838 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c, 19839 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9, 19840 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e, 19841 arm10t arm10e, arm1020t, arm1020e, arm10200e, 19842 strongarm, strongarm110, strongarm1100, strongarm1110, xscale. 19843 19844 */ 19845 19846const char * md_shortopts = "m:k"; 19847 19848#ifdef ARM_BI_ENDIAN 19849#define OPTION_EB (OPTION_MD_BASE + 0) 19850#define OPTION_EL (OPTION_MD_BASE + 1) 19851#else 19852#if TARGET_BYTES_BIG_ENDIAN 19853#define OPTION_EB (OPTION_MD_BASE + 0) 19854#else 19855#define OPTION_EL (OPTION_MD_BASE + 1) 19856#endif 19857#endif 19858 19859struct option md_longopts[] = 19860{ 19861#ifdef OPTION_EB 19862 {"EB", no_argument, NULL, OPTION_EB}, 19863#endif 19864#ifdef OPTION_EL 19865 {"EL", no_argument, NULL, OPTION_EL}, 19866#endif 19867 {NULL, no_argument, NULL, 0} 19868}; 19869 19870size_t md_longopts_size = sizeof (md_longopts); 19871 19872struct arm_option_table 19873{ 19874 char *option; /* Option name to match. */ 19875 char *help; /* Help information. */ 19876 int *var; /* Variable to change. */ 19877 int value; /* What to change it to. */ 19878 char *deprecated; /* If non-null, print this message. */ 19879}; 19880 19881struct arm_option_table arm_opts[] = 19882{ 19883 {"k", N_("generate PIC code"), &pic_code, 1, NULL}, 19884 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL}, 19885 {"mthumb-interwork", N_("support ARM/Thumb interworking"), 19886 &support_interwork, 1, NULL}, 19887 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL}, 19888 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL}, 19889 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float, 19890 1, NULL}, 19891 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL}, 19892 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL}, 19893 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL}, 19894 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0, 19895 NULL}, 19896 19897 /* These are recognized by the assembler, but have no affect on code. */ 19898 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL}, 19899 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL}, 19900 {NULL, NULL, NULL, 0, NULL} 19901}; 19902 19903struct arm_legacy_option_table 19904{ 19905 char *option; /* Option name to match. */ 19906 const arm_feature_set **var; /* Variable to change. */ 19907 const arm_feature_set value; /* What to change it to. */ 19908 char *deprecated; /* If non-null, print this message. */ 19909}; 19910 19911const struct arm_legacy_option_table arm_legacy_opts[] = 19912{ 19913 /* DON'T add any new processors to this list -- we want the whole list 19914 to go away... Add them to the processors table instead. */ 19915 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19916 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")}, 19917 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19918 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")}, 19919 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19920 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")}, 19921 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19922 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")}, 19923 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19924 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")}, 19925 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19926 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")}, 19927 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19928 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")}, 19929 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19930 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")}, 19931 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19932 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")}, 19933 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19934 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")}, 19935 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19936 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")}, 19937 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19938 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")}, 19939 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19940 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")}, 19941 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19942 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")}, 19943 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19944 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")}, 19945 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19946 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")}, 19947 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19948 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")}, 19949 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19950 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")}, 19951 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19952 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")}, 19953 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19954 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")}, 19955 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19956 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")}, 19957 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19958 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")}, 19959 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19960 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")}, 19961 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19962 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19963 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19964 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")}, 19965 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19966 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")}, 19967 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19968 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")}, 19969 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19970 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")}, 19971 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19972 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")}, 19973 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 19974 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")}, 19975 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 19976 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")}, 19977 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 19978 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")}, 19979 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 19980 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")}, 19981 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 19982 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")}, 19983 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")}, 19984 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4, 19985 N_("use -mcpu=strongarm110")}, 19986 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4, 19987 N_("use -mcpu=strongarm1100")}, 19988 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4, 19989 N_("use -mcpu=strongarm1110")}, 19990 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")}, 19991 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")}, 19992 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")}, 19993 19994 /* Architecture variants -- don't add any more to this list either. */ 19995 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 19996 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")}, 19997 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 19998 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")}, 19999 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 20000 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")}, 20001 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 20002 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")}, 20003 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 20004 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")}, 20005 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 20006 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")}, 20007 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 20008 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")}, 20009 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 20010 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")}, 20011 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 20012 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")}, 20013 20014 /* Floating point variants -- don't add any more to this list either. */ 20015 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")}, 20016 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")}, 20017 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")}, 20018 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE, 20019 N_("use either -mfpu=softfpa or -mfpu=softvfp")}, 20020 20021 {NULL, NULL, ARM_ARCH_NONE, NULL} 20022}; 20023 20024struct arm_cpu_option_table 20025{ 20026 char *name; 20027 const arm_feature_set value; 20028 /* For some CPUs we assume an FPU unless the user explicitly sets 20029 -mfpu=... */ 20030 const arm_feature_set default_fpu; 20031 /* The canonical name of the CPU, or NULL to use NAME converted to upper 20032 case. */ 20033 const char *canonical_name; 20034}; 20035 20036/* This list should, at a minimum, contain all the cpu names 20037 recognized by GCC. */ 20038static const struct arm_cpu_option_table arm_cpus[] = 20039{ 20040 {"all", ARM_ANY, FPU_ARCH_FPA, NULL}, 20041 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL}, 20042 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL}, 20043 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 20044 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL}, 20045 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20046 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20047 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20048 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20049 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20050 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20051 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20052 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20053 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20054 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20055 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL}, 20056 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20057 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20058 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20059 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20060 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20061 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20062 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20063 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20064 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20065 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20066 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20067 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL}, 20068 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20069 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20070 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20071 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20072 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20073 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20074 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20075 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20076 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20077 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL}, 20078 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20079 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"}, 20080 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20081 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20082 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20083 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL}, 20084 /* For V5 or later processors we default to using VFP; but the user 20085 should really set the FPU type explicitly. */ 20086 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20087 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20088 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 20089 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"}, 20090 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 20091 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20092 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"}, 20093 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20094 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL}, 20095 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"}, 20096 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20097 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20098 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20099 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20100 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20101 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"}, 20102 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL}, 20103 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20104 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL}, 20105 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"}, 20106 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL}, 20107 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"}, 20108 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL}, 20109 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"}, 20110 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL}, 20111 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL}, 20112 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL}, 20113 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL}, 20114 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL}, 20115 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL}, 20116 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL}, 20117 {"cortex-a8", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 20118 | FPU_NEON_EXT_V1), 20119 NULL}, 20120 {"cortex-a9", ARM_ARCH_V7A, ARM_FEATURE(0, FPU_VFP_V3 20121 | FPU_NEON_EXT_V1), 20122 NULL}, 20123 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL}, 20124 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL}, 20125 /* ??? XSCALE is really an architecture. */ 20126 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20127 /* ??? iwmmxt is not a processor. */ 20128 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL}, 20129 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL}, 20130 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL}, 20131 /* Maverick */ 20132 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"}, 20133 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL} 20134}; 20135 20136struct arm_arch_option_table 20137{ 20138 char *name; 20139 const arm_feature_set value; 20140 const arm_feature_set default_fpu; 20141}; 20142 20143/* This list should, at a minimum, contain all the architecture names 20144 recognized by GCC. */ 20145static const struct arm_arch_option_table arm_archs[] = 20146{ 20147 {"all", ARM_ANY, FPU_ARCH_FPA}, 20148 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA}, 20149 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA}, 20150 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20151 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA}, 20152 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA}, 20153 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA}, 20154 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA}, 20155 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA}, 20156 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA}, 20157 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA}, 20158 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP}, 20159 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP}, 20160 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP}, 20161 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP}, 20162 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP}, 20163 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP}, 20164 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP}, 20165 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP}, 20166 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP}, 20167 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP}, 20168 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP}, 20169 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP}, 20170 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP}, 20171 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP}, 20172 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP}, 20173 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP}, 20174 /* The official spelling of the ARMv7 profile variants is the dashed form. 20175 Accept the non-dashed form for compatibility with old toolchains. */ 20176 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20177 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20178 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20179 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP}, 20180 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP}, 20181 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP}, 20182 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP}, 20183 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP}, 20184 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP}, 20185 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE} 20186}; 20187 20188/* ISA extensions in the co-processor space. */ 20189struct arm_option_cpu_value_table 20190{ 20191 char *name; 20192 const arm_feature_set value; 20193}; 20194 20195static const struct arm_option_cpu_value_table arm_extensions[] = 20196{ 20197 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)}, 20198 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)}, 20199 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)}, 20200 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)}, 20201 {"sec", ARM_FEATURE (ARM_EXT_V6Z, 0)}, 20202 {NULL, ARM_ARCH_NONE} 20203}; 20204 20205/* This list should, at a minimum, contain all the fpu names 20206 recognized by GCC. */ 20207static const struct arm_option_cpu_value_table arm_fpus[] = 20208{ 20209 {"softfpa", FPU_NONE}, 20210 {"fpe", FPU_ARCH_FPE}, 20211 {"fpe2", FPU_ARCH_FPE}, 20212 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */ 20213 {"fpa", FPU_ARCH_FPA}, 20214 {"fpa10", FPU_ARCH_FPA}, 20215 {"fpa11", FPU_ARCH_FPA}, 20216 {"arm7500fe", FPU_ARCH_FPA}, 20217 {"softvfp", FPU_ARCH_VFP}, 20218 {"softvfp+vfp", FPU_ARCH_VFP_V2}, 20219 {"vfp", FPU_ARCH_VFP_V2}, 20220 {"vfpv2", FPU_ARCH_VFP_V2}, 20221 {"vfp9", FPU_ARCH_VFP_V2}, 20222 {"vfp3", FPU_ARCH_VFP_V3}, 20223 {"vfpv3", FPU_ARCH_VFP_V3}, 20224 {"vfp10", FPU_ARCH_VFP_V2}, 20225 {"vfp10-r0", FPU_ARCH_VFP_V1}, 20226 {"vfpxd", FPU_ARCH_VFP_V1xD}, 20227 {"arm1020t", FPU_ARCH_VFP_V1}, 20228 {"arm1020e", FPU_ARCH_VFP_V2}, 20229 {"arm1136jfs", FPU_ARCH_VFP_V2}, 20230 {"arm1136jf-s", FPU_ARCH_VFP_V2}, 20231 {"maverick", FPU_ARCH_MAVERICK}, 20232 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, 20233 {NULL, ARM_ARCH_NONE} 20234}; 20235 20236struct arm_option_value_table 20237{ 20238 char *name; 20239 long value; 20240}; 20241 20242static const struct arm_option_value_table arm_float_abis[] = 20243{ 20244 {"hard", ARM_FLOAT_ABI_HARD}, 20245 {"softfp", ARM_FLOAT_ABI_SOFTFP}, 20246 {"soft", ARM_FLOAT_ABI_SOFT}, 20247 {NULL, 0} 20248}; 20249 20250#ifdef OBJ_ELF 20251/* We only know how to output GNU and ver 4/5 (AAELF) formats. */ 20252static const struct arm_option_value_table arm_eabis[] = 20253{ 20254 {"gnu", EF_ARM_EABI_UNKNOWN}, 20255 {"4", EF_ARM_EABI_VER4}, 20256 {"5", EF_ARM_EABI_VER5}, 20257 {NULL, 0} 20258}; 20259#endif 20260 20261struct arm_long_option_table 20262{ 20263 char * option; /* Substring to match. */ 20264 char * help; /* Help information. */ 20265 int (* func) (char * subopt); /* Function to decode sub-option. */ 20266 char * deprecated; /* If non-null, print this message. */ 20267}; 20268 20269static int 20270arm_parse_extension (char * str, const arm_feature_set **opt_p) 20271{ 20272 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set)); 20273 20274 /* Copy the feature set, so that we can modify it. */ 20275 *ext_set = **opt_p; 20276 *opt_p = ext_set; 20277 20278 while (str != NULL && *str != 0) 20279 { 20280 const struct arm_option_cpu_value_table * opt; 20281 char * ext; 20282 int optlen; 20283 20284 if (*str != '+') 20285 { 20286 as_bad (_("invalid architectural extension")); 20287 return 0; 20288 } 20289 20290 str++; 20291 ext = strchr (str, '+'); 20292 20293 if (ext != NULL) 20294 optlen = ext - str; 20295 else 20296 optlen = strlen (str); 20297 20298 if (optlen == 0) 20299 { 20300 as_bad (_("missing architectural extension")); 20301 return 0; 20302 } 20303 20304 for (opt = arm_extensions; opt->name != NULL; opt++) 20305 if (strncmp (opt->name, str, optlen) == 0) 20306 { 20307 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value); 20308 break; 20309 } 20310 20311 if (opt->name == NULL) 20312 { 20313 as_bad (_("unknown architectural extnsion `%s'"), str); 20314 return 0; 20315 } 20316 20317 str = ext; 20318 }; 20319 20320 return 1; 20321} 20322 20323static int 20324arm_parse_cpu (char * str) 20325{ 20326 const struct arm_cpu_option_table * opt; 20327 char * ext = strchr (str, '+'); 20328 int optlen; 20329 20330 if (ext != NULL) 20331 optlen = ext - str; 20332 else 20333 optlen = strlen (str); 20334 20335 if (optlen == 0) 20336 { 20337 as_bad (_("missing cpu name `%s'"), str); 20338 return 0; 20339 } 20340 20341 for (opt = arm_cpus; opt->name != NULL; opt++) 20342 if (strncmp (opt->name, str, optlen) == 0) 20343 { 20344 mcpu_cpu_opt = &opt->value; 20345 mcpu_fpu_opt = &opt->default_fpu; 20346 if (opt->canonical_name) 20347 strcpy(selected_cpu_name, opt->canonical_name); 20348 else 20349 { 20350 int i; 20351 for (i = 0; i < optlen; i++) 20352 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20353 selected_cpu_name[i] = 0; 20354 } 20355 20356 if (ext != NULL) 20357 return arm_parse_extension (ext, &mcpu_cpu_opt); 20358 20359 return 1; 20360 } 20361 20362 as_bad (_("unknown cpu `%s'"), str); 20363 return 0; 20364} 20365 20366static int 20367arm_parse_arch (char * str) 20368{ 20369 const struct arm_arch_option_table *opt; 20370 char *ext = strchr (str, '+'); 20371 int optlen; 20372 20373 if (ext != NULL) 20374 optlen = ext - str; 20375 else 20376 optlen = strlen (str); 20377 20378 if (optlen == 0) 20379 { 20380 as_bad (_("missing architecture name `%s'"), str); 20381 return 0; 20382 } 20383 20384 for (opt = arm_archs; opt->name != NULL; opt++) 20385 if (strncmp (opt->name, str, optlen) == 0) 20386 { 20387 march_cpu_opt = &opt->value; 20388 march_fpu_opt = &opt->default_fpu; 20389 strcpy(selected_cpu_name, opt->name); 20390 20391 if (ext != NULL) 20392 return arm_parse_extension (ext, &march_cpu_opt); 20393 20394 return 1; 20395 } 20396 20397 as_bad (_("unknown architecture `%s'\n"), str); 20398 return 0; 20399} 20400 20401static int 20402arm_parse_fpu (char * str) 20403{ 20404 const struct arm_option_cpu_value_table * opt; 20405 20406 for (opt = arm_fpus; opt->name != NULL; opt++) 20407 if (streq (opt->name, str)) 20408 { 20409 mfpu_opt = &opt->value; 20410 return 1; 20411 } 20412 20413 as_bad (_("unknown floating point format `%s'\n"), str); 20414 return 0; 20415} 20416 20417static int 20418arm_parse_float_abi (char * str) 20419{ 20420 const struct arm_option_value_table * opt; 20421 20422 for (opt = arm_float_abis; opt->name != NULL; opt++) 20423 if (streq (opt->name, str)) 20424 { 20425 mfloat_abi_opt = opt->value; 20426 return 1; 20427 } 20428 20429 as_bad (_("unknown floating point abi `%s'\n"), str); 20430 return 0; 20431} 20432 20433#ifdef OBJ_ELF 20434static int 20435arm_parse_eabi (char * str) 20436{ 20437 const struct arm_option_value_table *opt; 20438 20439 for (opt = arm_eabis; opt->name != NULL; opt++) 20440 if (streq (opt->name, str)) 20441 { 20442 meabi_flags = opt->value; 20443 return 1; 20444 } 20445 as_bad (_("unknown EABI `%s'\n"), str); 20446 return 0; 20447} 20448#endif 20449 20450struct arm_long_option_table arm_long_opts[] = 20451{ 20452 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"), 20453 arm_parse_cpu, NULL}, 20454 {"march=", N_("<arch name>\t assemble for architecture <arch name>"), 20455 arm_parse_arch, NULL}, 20456 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"), 20457 arm_parse_fpu, NULL}, 20458 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"), 20459 arm_parse_float_abi, NULL}, 20460#ifdef OBJ_ELF 20461 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"), 20462 arm_parse_eabi, NULL}, 20463#endif 20464 {NULL, NULL, 0, NULL} 20465}; 20466 20467int 20468md_parse_option (int c, char * arg) 20469{ 20470 struct arm_option_table *opt; 20471 const struct arm_legacy_option_table *fopt; 20472 struct arm_long_option_table *lopt; 20473 20474 switch (c) 20475 { 20476#ifdef OPTION_EB 20477 case OPTION_EB: 20478 target_big_endian = 1; 20479 break; 20480#endif 20481 20482#ifdef OPTION_EL 20483 case OPTION_EL: 20484 target_big_endian = 0; 20485 break; 20486#endif 20487 20488 case 'a': 20489 /* Listing option. Just ignore these, we don't support additional 20490 ones. */ 20491 return 0; 20492 20493 default: 20494 for (opt = arm_opts; opt->option != NULL; opt++) 20495 { 20496 if (c == opt->option[0] 20497 && ((arg == NULL && opt->option[1] == 0) 20498 || streq (arg, opt->option + 1))) 20499 { 20500#if WARN_DEPRECATED 20501 /* If the option is deprecated, tell the user. */ 20502 if (opt->deprecated != NULL) 20503 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20504 arg ? arg : "", _(opt->deprecated)); 20505#endif 20506 20507 if (opt->var != NULL) 20508 *opt->var = opt->value; 20509 20510 return 1; 20511 } 20512 } 20513 20514 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++) 20515 { 20516 if (c == fopt->option[0] 20517 && ((arg == NULL && fopt->option[1] == 0) 20518 || streq (arg, fopt->option + 1))) 20519 { 20520#if WARN_DEPRECATED 20521 /* If the option is deprecated, tell the user. */ 20522 if (fopt->deprecated != NULL) 20523 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, 20524 arg ? arg : "", _(fopt->deprecated)); 20525#endif 20526 20527 if (fopt->var != NULL) 20528 *fopt->var = &fopt->value; 20529 20530 return 1; 20531 } 20532 } 20533 20534 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20535 { 20536 /* These options are expected to have an argument. */ 20537 if (c == lopt->option[0] 20538 && arg != NULL 20539 && strncmp (arg, lopt->option + 1, 20540 strlen (lopt->option + 1)) == 0) 20541 { 20542#if WARN_DEPRECATED 20543 /* If the option is deprecated, tell the user. */ 20544 if (lopt->deprecated != NULL) 20545 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg, 20546 _(lopt->deprecated)); 20547#endif 20548 20549 /* Call the sup-option parser. */ 20550 return lopt->func (arg + strlen (lopt->option) - 1); 20551 } 20552 } 20553 20554 return 0; 20555 } 20556 20557 return 1; 20558} 20559 20560void 20561md_show_usage (FILE * fp) 20562{ 20563 struct arm_option_table *opt; 20564 struct arm_long_option_table *lopt; 20565 20566 fprintf (fp, _(" ARM-specific assembler options:\n")); 20567 20568 for (opt = arm_opts; opt->option != NULL; opt++) 20569 if (opt->help != NULL) 20570 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help)); 20571 20572 for (lopt = arm_long_opts; lopt->option != NULL; lopt++) 20573 if (lopt->help != NULL) 20574 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help)); 20575 20576#ifdef OPTION_EB 20577 fprintf (fp, _("\ 20578 -EB assemble code for a big-endian cpu\n")); 20579#endif 20580 20581#ifdef OPTION_EL 20582 fprintf (fp, _("\ 20583 -EL assemble code for a little-endian cpu\n")); 20584#endif 20585} 20586 20587 20588#ifdef OBJ_ELF 20589typedef struct 20590{ 20591 int val; 20592 arm_feature_set flags; 20593} cpu_arch_ver_table; 20594 20595/* Mapping from CPU features to EABI CPU arch values. Table must be sorted 20596 least features first. */ 20597static const cpu_arch_ver_table cpu_arch_ver[] = 20598{ 20599 {1, ARM_ARCH_V4}, 20600 {2, ARM_ARCH_V4T}, 20601 {3, ARM_ARCH_V5}, 20602 {4, ARM_ARCH_V5TE}, 20603 {5, ARM_ARCH_V5TEJ}, 20604 {6, ARM_ARCH_V6}, 20605 {7, ARM_ARCH_V6Z}, 20606 {8, ARM_ARCH_V6K}, 20607 {9, ARM_ARCH_V6T2}, 20608 {10, ARM_ARCH_V7A}, 20609 {10, ARM_ARCH_V7R}, 20610 {10, ARM_ARCH_V7M}, 20611 {0, ARM_ARCH_NONE} 20612}; 20613 20614/* Set the public EABI object attributes. */ 20615static void 20616aeabi_set_public_attributes (void) 20617{ 20618 int arch; 20619 arm_feature_set flags; 20620 arm_feature_set tmp; 20621 const cpu_arch_ver_table *p; 20622 20623 /* Choose the architecture based on the capabilities of the requested cpu 20624 (if any) and/or the instructions actually used. */ 20625 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used); 20626 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt); 20627 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu); 20628 /*Allow the user to override the reported architecture. */ 20629 if (object_arch) 20630 { 20631 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any); 20632 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch); 20633 } 20634 20635 tmp = flags; 20636 arch = 0; 20637 for (p = cpu_arch_ver; p->val; p++) 20638 { 20639 if (ARM_CPU_HAS_FEATURE (tmp, p->flags)) 20640 { 20641 arch = p->val; 20642 ARM_CLEAR_FEATURE (tmp, tmp, p->flags); 20643 } 20644 } 20645 20646 /* Tag_CPU_name. */ 20647 if (selected_cpu_name[0]) 20648 { 20649 char *p; 20650 20651 p = selected_cpu_name; 20652 if (strncmp(p, "armv", 4) == 0) 20653 { 20654 int i; 20655 20656 p += 4; 20657 for (i = 0; p[i]; i++) 20658 p[i] = TOUPPER (p[i]); 20659 } 20660 bfd_elf_add_proc_attr_string (stdoutput, 5, p); 20661 } 20662 /* Tag_CPU_arch. */ 20663 bfd_elf_add_proc_attr_int (stdoutput, 6, arch); 20664 /* Tag_CPU_arch_profile. */ 20665 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)) 20666 bfd_elf_add_proc_attr_int (stdoutput, 7, 'A'); 20667 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r)) 20668 bfd_elf_add_proc_attr_int (stdoutput, 7, 'R'); 20669 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)) 20670 bfd_elf_add_proc_attr_int (stdoutput, 7, 'M'); 20671 /* Tag_ARM_ISA_use. */ 20672 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full)) 20673 bfd_elf_add_proc_attr_int (stdoutput, 8, 1); 20674 /* Tag_THUMB_ISA_use. */ 20675 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full)) 20676 bfd_elf_add_proc_attr_int (stdoutput, 9, 20677 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1); 20678 /* Tag_VFP_arch. */ 20679 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3) 20680 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3)) 20681 bfd_elf_add_proc_attr_int (stdoutput, 10, 3); 20682 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2) 20683 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2)) 20684 bfd_elf_add_proc_attr_int (stdoutput, 10, 2); 20685 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1) 20686 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1) 20687 || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd) 20688 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd)) 20689 bfd_elf_add_proc_attr_int (stdoutput, 10, 1); 20690 /* Tag_WMMX_arch. */ 20691 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt) 20692 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt)) 20693 bfd_elf_add_proc_attr_int (stdoutput, 11, 1); 20694 /* Tag_NEON_arch. */ 20695 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1) 20696 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1)) 20697 bfd_elf_add_proc_attr_int (stdoutput, 12, 1); 20698} 20699 20700/* Add the default contents for the .ARM.attributes section. */ 20701void 20702arm_md_end (void) 20703{ 20704 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4) 20705 return; 20706 20707 aeabi_set_public_attributes (); 20708} 20709#endif /* OBJ_ELF */ 20710 20711 20712/* Parse a .cpu directive. */ 20713 20714static void 20715s_arm_cpu (int ignored ATTRIBUTE_UNUSED) 20716{ 20717 const struct arm_cpu_option_table *opt; 20718 char *name; 20719 char saved_char; 20720 20721 name = input_line_pointer; 20722 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20723 input_line_pointer++; 20724 saved_char = *input_line_pointer; 20725 *input_line_pointer = 0; 20726 20727 /* Skip the first "all" entry. */ 20728 for (opt = arm_cpus + 1; opt->name != NULL; opt++) 20729 if (streq (opt->name, name)) 20730 { 20731 mcpu_cpu_opt = &opt->value; 20732 selected_cpu = opt->value; 20733 if (opt->canonical_name) 20734 strcpy(selected_cpu_name, opt->canonical_name); 20735 else 20736 { 20737 int i; 20738 for (i = 0; opt->name[i]; i++) 20739 selected_cpu_name[i] = TOUPPER (opt->name[i]); 20740 selected_cpu_name[i] = 0; 20741 } 20742 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20743 *input_line_pointer = saved_char; 20744 demand_empty_rest_of_line (); 20745 return; 20746 } 20747 as_bad (_("unknown cpu `%s'"), name); 20748 *input_line_pointer = saved_char; 20749 ignore_rest_of_line (); 20750} 20751 20752 20753/* Parse a .arch directive. */ 20754 20755static void 20756s_arm_arch (int ignored ATTRIBUTE_UNUSED) 20757{ 20758 const struct arm_arch_option_table *opt; 20759 char saved_char; 20760 char *name; 20761 20762 name = input_line_pointer; 20763 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20764 input_line_pointer++; 20765 saved_char = *input_line_pointer; 20766 *input_line_pointer = 0; 20767 20768 /* Skip the first "all" entry. */ 20769 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20770 if (streq (opt->name, name)) 20771 { 20772 mcpu_cpu_opt = &opt->value; 20773 selected_cpu = opt->value; 20774 strcpy(selected_cpu_name, opt->name); 20775 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20776 *input_line_pointer = saved_char; 20777 demand_empty_rest_of_line (); 20778 return; 20779 } 20780 20781 as_bad (_("unknown architecture `%s'\n"), name); 20782 *input_line_pointer = saved_char; 20783 ignore_rest_of_line (); 20784} 20785 20786/* Parse a .arch_extension directive. */ 20787 20788static void 20789s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED) 20790{ 20791 const struct arm_option_cpu_value_table *opt; 20792 char saved_char; 20793 char *name; 20794 20795 name = input_line_pointer; 20796 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20797 input_line_pointer++; 20798 saved_char = *input_line_pointer; 20799 *input_line_pointer = 0; 20800 20801 for (opt = arm_extensions; opt->name != NULL; opt++) 20802 if (streq (opt->name, name)) 20803 { 20804 ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, opt->value); 20805 *input_line_pointer = saved_char; 20806 demand_empty_rest_of_line (); 20807 return; 20808 } 20809 20810 as_bad (_("unknown architecture `%s'\n"), name); 20811 *input_line_pointer = saved_char; 20812 ignore_rest_of_line (); 20813} 20814 20815/* Parse a .object_arch directive. */ 20816 20817static void 20818s_arm_object_arch (int ignored ATTRIBUTE_UNUSED) 20819{ 20820 const struct arm_arch_option_table *opt; 20821 char saved_char; 20822 char *name; 20823 20824 name = input_line_pointer; 20825 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20826 input_line_pointer++; 20827 saved_char = *input_line_pointer; 20828 *input_line_pointer = 0; 20829 20830 /* Skip the first "all" entry. */ 20831 for (opt = arm_archs + 1; opt->name != NULL; opt++) 20832 if (streq (opt->name, name)) 20833 { 20834 object_arch = &opt->value; 20835 *input_line_pointer = saved_char; 20836 demand_empty_rest_of_line (); 20837 return; 20838 } 20839 20840 as_bad (_("unknown architecture `%s'\n"), name); 20841 *input_line_pointer = saved_char; 20842 ignore_rest_of_line (); 20843} 20844 20845 20846/* Parse a .fpu directive. */ 20847 20848static void 20849s_arm_fpu (int ignored ATTRIBUTE_UNUSED) 20850{ 20851 const struct arm_option_cpu_value_table *opt; 20852 char saved_char; 20853 char *name; 20854 20855 name = input_line_pointer; 20856 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 20857 input_line_pointer++; 20858 saved_char = *input_line_pointer; 20859 *input_line_pointer = 0; 20860 20861 for (opt = arm_fpus; opt->name != NULL; opt++) 20862 if (streq (opt->name, name)) 20863 { 20864 mfpu_opt = &opt->value; 20865 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt); 20866 *input_line_pointer = saved_char; 20867 demand_empty_rest_of_line (); 20868 return; 20869 } 20870 20871 as_bad (_("unknown floating point format `%s'\n"), name); 20872 *input_line_pointer = saved_char; 20873 ignore_rest_of_line (); 20874} 20875 20876/* Copy symbol information. */ 20877void 20878arm_copy_symbol_attributes (symbolS *dest, symbolS *src) 20879{ 20880 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src); 20881} 20882