1/* 2 * Copyright (c) 2007 Apple Inc. All rights reserved. 3 * 4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ 5 * 6 * This file contains Original Code and/or Modifications of Original Code 7 * as defined in and that are subject to the Apple Public Source License 8 * Version 2.0 (the 'License'). You may not use this file except in 9 * compliance with the License. The rights granted to you under the License 10 * may not be used to create, or enable the creation or redistribution of, 11 * unlawful or unlicensed copies of an Apple operating system, or to 12 * circumvent, violate, or enable the circumvention or violation of, any 13 * terms of an Apple operating system software license agreement. 14 * 15 * Please obtain a copy of the License at 16 * http://www.opensource.apple.com/apsl/ and read it before using this file. 17 * 18 * The Original Code and all software distributed under the License are 19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER 20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, 21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. 23 * Please see the License for the specific language governing rights and 24 * limitations under the License. 25 * 26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ 27 */ 28#ifdef KERNEL_PRIVATE 29#ifndef _I386_MACHINE_CHECK_H_ 30#define _I386_MACHINE_CHECK_H_ 31 32#include <stdint.h> 33 34#include <i386/cpu_data.h> 35 36/* 37 * This header defines the machine check architecture for Pentium4 and Xeon. 38 */ 39 40/* 41 * Macro BITS(n,m) returns the number of bits between bit(n) and bit(m), 42 * where (n>m). Macro BIT1(n) is cosmetic and returns 1. 43 */ 44#define BITS(n,m) ((n)-(m)+1) 45#define BIT1(n) (1) 46 47/* 48 * IA32 SDM 14.3.1 Machine-Check Global Control MSRs: 49 */ 50#define IA32_MCG_CAP (0x179) 51typedef union { 52 struct { 53 uint64_t count :BITS(7,0); 54 uint64_t mcg_ctl_p :BIT1(8); 55 uint64_t mcg_ext_p :BIT1(9); 56 uint64_t mcg_ext_corr_err_p :BIT1(10); 57 uint64_t mcg_tes_p :BIT1(11); 58 uint64_t mcg_ecms :BIT1(12); 59 uint64_t mcg_reserved2 :BITS(15,13); 60 uint64_t mcg_ext_cnt :BITS(23,16); 61 uint64_t mcg_ser_p :BIT1(24); 62 } bits; 63 uint64_t u64; 64} ia32_mcg_cap_t; 65 66#define IA32_MCG_STATUS (0x17A) 67typedef union { 68 struct { 69 uint64_t ripv :BIT1(0); 70 uint64_t eipv :BIT1(1); 71 uint64_t mcip :BIT1(2); 72 } bits; 73 uint64_t u64; 74} ia32_mcg_status_t; 75 76#define IA32_MCG_CTL (0x17B) 77typedef uint64_t ia32_mcg_ctl_t; 78#define IA32_MCG_CTL_ENABLE (0xFFFFFFFFFFFFFFFFULL) 79#define IA32_MCG_CTL_DISABLE (0x0ULL) 80 81 82/* 83 * IA32 SDM 14.3.2 Error-Reporting Register Banks: 84 */ 85#define IA32_MCi_CTL(i) (0x400 + 4*(i)) 86#define IA32_MCi_STATUS(i) (0x401 + 4*(i)) 87#define IA32_MCi_ADDR(i) (0x402 + 4*(i)) 88#define IA32_MCi_MISC(i) (0x403 + 4*(i)) 89 90#define IA32_MC0_CTL IA32_MCi_CTL(0) 91#define IA32_MC0_STATUS IA32_MCi_STATUS(0) 92#define IA32_MC0_ADDR IA32_MCi_ADDR(0) 93#define IA32_MC0_MISC IA32_MCi_MISC(0) 94 95#define IA32_MC1_CTL IA32_MCi_CTL(1) 96#define IA32_MC1_STATUS IA32_MCi_STATUS(1) 97#define IA32_MC1_ADDR IA32_MCi_ADDR(1) 98#define IA32_MC1_MISC IA32_MCi_MISC(1) 99 100#define IA32_MC2_CTL IA32_MCi_CTL(2) 101#define IA32_MC2_STATUS IA32_MCi_STATUS(2) 102#define IA32_MC2_ADDR IA32_MCi_ADDR(2) 103#define IA32_MC2_MISC IA32_MCi_MISC(2) 104 105#define IA32_MC3_CTL IA32_MCi_CTL(3) 106#define IA32_MC3_STATUS IA32_MCi_STATUS(3) 107#define IA32_MC3_ADDR IA32_MCi_ADDR(3) 108#define IA32_MC3_MISC IA32_MCi_MISC(3) 109 110#define IA32_MC4_CTL IA32_MCi_CTL(4) 111#define IA32_MC4_STATUS IA32_MCi_STATUS(4) 112#define IA32_MC4_ADDR IA32_MCi_ADDR(4) 113#define IA32_MC4_MISC IA32_MCi_MISC(4) 114 115typedef uint64_t ia32_mci_ctl_t; 116#define IA32_MCi_CTL_EE(j) (0x1ULL << (j)) 117#define IA32_MCi_CTL_ENABLE_ALL (0xFFFFFFFFFFFFFFFFULL) 118 119typedef union { 120 struct { 121 uint64_t mca_error :BITS(15,0); 122 uint64_t model_specific_error :BITS(31,16); 123 uint64_t other_information :BITS(56,32); 124 uint64_t pcc :BIT1(57); 125 uint64_t addrv :BIT1(58); 126 uint64_t miscv :BIT1(59); 127 uint64_t en :BIT1(60); 128 uint64_t uc :BIT1(61); 129 uint64_t over :BIT1(62); 130 uint64_t val :BIT1(63); 131 } bits; 132 struct { /* Variant if threshold-based error status present: */ 133 uint64_t mca_error :BITS(15,0); 134 uint64_t model_specific_error :BITS(31,16); 135 uint64_t other_information :BITS(52,32); 136 uint64_t threshold :BITS(54,53); 137 uint64_t ar :BIT1(55); 138 uint64_t s :BIT1(56); 139 uint64_t pcc :BIT1(57); 140 uint64_t addrv :BIT1(58); 141 uint64_t miscv :BIT1(59); 142 uint64_t en :BIT1(60); 143 uint64_t uc :BIT1(61); 144 uint64_t over :BIT1(62); 145 uint64_t val :BIT1(63); 146 } bits_tes_p; 147 struct ia32_mc8_specific { 148 uint64_t channel_number :BITS(3,0); 149 uint64_t memory_operation :BITS(6,4); 150 uint64_t unused :BITS(15,7); 151 uint64_t read_ecc :BIT1(16); 152 uint64_t ecc_on_a_scrub :BIT1(17); 153 uint64_t write_parity :BIT1(18); 154 uint64_t redundant_memory :BIT1(19); 155 uint64_t sparing :BIT1(20); 156 uint64_t access_out_of_range :BIT1(21); 157 uint64_t rtid_out_of_range :BIT1(22); 158 uint64_t address_parity :BIT1(23); 159 uint64_t byte_enable_parity :BIT1(24); 160 uint64_t reserved :BITS(37,25); 161 uint64_t cor_err_cnt :BITS(52,38); 162 } bits_mc8; 163 uint64_t u64; 164} ia32_mci_status_t; 165 166/* Values for threshold_status if mcg_tes_p == 1 and uc == 0 */ 167#define THRESHOLD_STATUS_NO_TRACKING 0 168#define THRESHOLD_STATUS_GREEN 1 169#define THRESHOLD_STATUS_YELLOW 2 170#define THRESHOLD_STATUS_RESERVED 3 171 172/* MC8 memory operations encoding: */ 173#define MC8_MMM_GENERIC 0 174#define MC8_MMM_READ 1 175#define MC8_MMM_WRITE 2 176#define MC8_MMM_ADDRESS_COMMAND 3 177#define MC8_MMM_RESERVED 4 178typedef union { 179 struct { 180 uint64_t rtid :BITS(7,0); 181 uint64_t reserved1 :BITS(15,8); 182 uint64_t dimm :BITS(17,16); 183 uint64_t channel :BITS(19,18); 184 uint64_t reserved2 :BITS(31,20); 185 uint64_t syndrome :BITS(63,32); 186 } bits; 187 uint64_t u64; 188} ia32_mc8_misc_t; 189 190typedef uint64_t ia32_mci_addr_t; 191typedef uint64_t ia32_mci_misc_t; 192 193#define IA32_MCG_EAX (0x180) 194#define IA32_MCG_EBX (0x181) 195#define IA32_MCG_ECX (0x182) 196#define IA32_MCG_EDX (0x183) 197#define IA32_MCG_ESI (0x184) 198#define IA32_MCG_EDI (0x185) 199#define IA32_MCG_EBP (0x186) 200#define IA32_MCG_ESP (0x187) 201#define IA32_MCG_EFLAGS (0x188) 202#define IA32_MCG_EIP (0x189) 203#define IA32_MCG_MISC (0x18A) 204 205#define IA32_MCG_RAX (0x180) 206#define IA32_MCG_RBX (0x181) 207#define IA32_MCG_RCX (0x182) 208#define IA32_MCG_RDX (0x183) 209#define IA32_MCG_RSI (0x184) 210#define IA32_MCG_RDI (0x185) 211#define IA32_MCG_RBP (0x186) 212#define IA32_MCG_RSP (0x187) 213#define IA32_MCG_RFLAGS (0x188) 214#define IA32_MCG_RIP (0x189) 215#define IA32_MCG_MISC (0x18A) 216#define IA32_MCG_RESERVED1 (0x18B) 217#define IA32_MCG_RESERVED2 (0x18C) 218#define IA32_MCG_RESERVED3 (0x18D) 219#define IA32_MCG_RESERVED4 (0x18E) 220#define IA32_MCG_RESERVED5 (0x18F) 221#define IA32_MCG_R8 (0x190) 222#define IA32_MCG_R9 (0x191) 223#define IA32_MCG_R10 (0x192) 224#define IA32_MCG_R11 (0x193) 225#define IA32_MCG_R12 (0x194) 226#define IA32_MCG_R13 (0x195) 227#define IA32_MCG_R14 (0x196) 228#define IA32_MCG_R15 (0x197) 229 230extern void mca_cpu_alloc(cpu_data_t *cdp); 231extern void mca_cpu_init(void); 232extern void mca_dump(void); 233extern void mca_check_save(void); 234extern boolean_t mca_is_cmci_present(void); 235 236#endif /* _I386_MACHINE_CHECK_H_ */ 237#endif /* KERNEL_PRIVATE */ 238