1/* 2 * Register and bit definitions for the Realtek RTL 8139C Single Chip 3 * Fast Ethernet Controller with integrated PHY. 4 * Reference: 5 * Realtek 3.3V Single Chip Fast EThernet Controller 6 * with Power Management RTL8139C(L), Rev 1.4 7 * Realtek Semiconductor Corporation, Hsinchu, Taiwan, 2002/01/10. 8 */ 9#ifndef _RTL8139_H_ 10#define _RTL8139_H_ 11 12#define _DD_MAKEMASK1(n) (1 << (n)) 13#define _DD_MAKEMASK(v,n) ((((1)<<(v))-1) << (n)) 14#define _DD_MAKEVALUE(v,n) ((v) << (n)) 15#define _DD_GETVALUE(v,n,m) (((v) & (m)) >> (n)) 16 17/* Register definitions generally use Realtek nomenclature. Registers 18 are 4 bytes and R/W except as indicated. */ 19 20#define K_PCI_VENDOR_REALTEK 0x10EC 21#define K_PCI_ID_RTL8139 0x8139 22 23 24/* PCI Configuration Register offsets (8139 specific, Section 8) */ 25 26#define CAP_PM 0x50 /* Power Management */ 27#define CAP_VPD 0x60 /* Vital Product Data */ 28 29 30/* RTL8139 Operation Register offsets (Section 6) */ 31 32#define R_IDR0 0x0000 /* 1 byte, R/W */ 33#define R_IDR1 0x0001 34#define R_IDR2 0x0002 35#define R_IDR3 0x0003 36#define R_IDR4 0x0004 37#define R_IDR5 0x0005 38#define R_IDR(i) (R_IDR0 + (i)) 39 40#define R_MAR0 0x0008 /* 1 byte, R/W */ 41#define R_MAR1 0x0009 42#define R_MAR2 0x000A 43#define R_MAR3 0x000B 44#define R_MAR4 0x000C 45#define R_MAR5 0x000D 46#define R_MAR6 0x000E 47#define R_MAR7 0x000F 48#define R_MAR(i) (R_MAR0 + (i)) 49 50#define N_TSD 4 /* tx_descr(n) = (TSDn, TSADn) */ 51 52#define R_TSD0 0x0010 53#define R_TSD1 0x0014 54#define R_TSD2 0x0018 55#define R_TSD3 0x001C 56#define R_TSD(i) (R_TSD0 + 4*(i)) 57 58#define R_TSAD0 0x0020 59#define R_TSAD1 0x0024 60#define R_TSAD2 0x0028 61#define R_TSAD3 0x002C 62#define R_TSAD(i) (R_TSAD0 + 4*(i)) 63 64#define R_RBSTART 0x0030 65#define R_ERBCR 0x0034 /* 2 bytes, R */ 66#define R_ERSR 0x0036 /* 1 byte, R */ 67#define R_CR 0x0037 /* 1 byte, R/W */ 68#define R_CAPR 0x0038 /* 2 bytes, R/W */ 69#define R_CBR 0x003A /* 2 bytes, R */ 70 71#define R_IMR 0x003C /* 2 bytes, R/W */ 72#define R_ISR 0x003E /* 2 bytes, R/W */ 73 74#define R_TCR 0x0040 75#define R_RCR 0x0044 76#define R_TCTR 0x0048 77#define R_MPC 0x004C 78 79#define R_9346CR 0x0050 /* 1 byte, R/W */ 80#define R_CONFIG0 0x0051 /* 1 byte, R/W */ 81#define R_CONFIG1 0x0052 /* 1 byte, R/W */ 82#define R_TIMERINT 0x0054 83#define R_MSR 0x0058 /* 1 byte, R/W */ 84#define R_CONFIG3 0x0059 /* 1 byte, R/W */ 85#define R_CONFIG4 0x005A /* 1 byte, R/W */ 86 87#define R_MULINT 0x005C /* 2 bytes, R/W */ 88#define R_REVID 0x005E /* 1 byte, R */ 89 90#define R_TSDS 0x0060 /* 2 bytes, R */ 91 92/* MII Control Registers (all 2 bytes) */ 93#define R_BMCR 0x0062 94#define R_BMSR 0x0064 95#define R_ANAR 0x0066 96#define R_ANLPAR 0x0068 97#define R_ANER 0x006A 98#define R_DIS 0x006C 99#define R_FCSC 0x006E 100#define R_NWAYTR 0x0070 101#define R_REC 0x0072 102#define R_CSCR 0x0074 103 104#define R_PHY1_PARM 0x0078 105#define R_TW_PARM 0x007C 106#define R_PHY2_PARM 0x0080 /* 1 byte, R/W */ 107 108/* Wake-On-LAN Registers at 0x0084-0x00D3 (not supported) */ 109 110#define R_FLASH 0x00D4 111#define R_CONFIG5 0x00D8 /* 1 byte, R/W */ 112 113/* CardBus Registers at 0x00F0-0x00FC (not supported) */ 114 115 116/* 0x0010-0x001C TSDn: Transmit Status Registers (6.2) */ 117 118#define S_TS_SIZE 0 119#define M_TS_SIZE _DD_MAKEMASK(13,S_TS_SIZE) 120#define V_TS_SIZE(x) _DD_MAKEVALUE(x,S_TS_SIZE) 121#define G_TS_SIZE(x) _DD_GETVALUE(x,S_TS_SIZE,M_TS_SIZE) 122 123#define M_TS_OWN _DD_MAKEMASK1(13) 124#define M_TS_TUN _DD_MAKEMASK1(14) 125#define M_TS_TOK _DD_MAKEMASK1(15) 126 127#define S_TS_ERTXTH 16 128#define M_TS_ERTXTH _DD_MAKEMASK(6,S_TS_ERTXTH) 129#define V_TS_ERTXTH(x) _DD_MAKEVALUE(x,S_TS_ERTXTH) 130#define G_TS_ERTXTH(x) _DD_GETVALUE(x,S_TS_ERTXTH,M_TS_ERTXTH) 131#define ENCODE_TXTH(n) (((n)>>5)-1) 132#define DECODE_TXTH(v) (((v)+1)<<5) 133 134#define S_TS_NCC 24 135#define M_TS_NCC _DD_MAKEMASK(4,S_TS_NCC) 136#define V_TS_NCC(x) _DD_MAKEVALUE(x,S_TS_NCC) 137#define G_TS_NCC(x) _DD_GETVALUE(x,S_TS_NCC,M_TS_NCC) 138 139#define M_TS_CDH _DD_MAKEMASK1(28) 140#define M_TS_OWC _DD_MAKEMASK1(29) 141#define M_TS_TABT _DD_MAKEMASK1(30) 142#define M_TS_CRS _DD_MAKEMASK1(31) 143 144 145/* 0x0036 ERSR: Early Rx Status Register (6.3) */ 146 147#define M_ERSR_EROK _DD_MAKEMASK1(0) 148#define M_ERSR_EROVW _DD_MAKEMASK1(1) 149#define M_ERSR_ERBAD _DD_MAKEMASK1(2) 150#define M_ERSR_ERGOOD _DD_MAKEMASK1(3) 151 152 153/* 0x0037 CR: Command Register (6.4) */ 154 155#define M_CR_BUFE _DD_MAKEMASK1(0) 156#define M_CR_TE _DD_MAKEMASK1(2) 157#define M_CR_RE _DD_MAKEMASK1(3) 158#define M_CR_RST _DD_MAKEMASK1(4) 159 160 161/* 0x003C IMR: Interrupt Mask Register (6.5) */ 162/* 0x003E ISR: Interrupt Status Register (6.6) */ 163 164#define M_INT_ROK _DD_MAKEMASK1(0) 165#define M_INT_RER _DD_MAKEMASK1(1) 166#define M_INT_TOK _DD_MAKEMASK1(2) 167#define M_INT_TER _DD_MAKEMASK1(3) 168#define M_INT_RXOVW _DD_MAKEMASK1(4) 169#define M_INT_PUN_LINKCHG _DD_MAKEMASK1(5) 170#define M_INT_FOVW _DD_MAKEMASK1(6) 171#define M_INT_LENCHG _DD_MAKEMASK1(13) 172#define M_INT_TIMEOUT _DD_MAKEMASK1(14) 173#define M_INT_SERR _DD_MAKEMASK1(15) 174 175 176/* 0x0040 TCR: Transmit Configuration Register (6.7) */ 177 178#define M_TCR_CLRABT _DD_MAKEMASK1(0) 179 180#define S_TCR_TXRR 4 181#define M_TCR_TXRR _DD_MAKEMASK(4,S_TCR_TXRR) 182#define V_TCR_TXRR(x) _DD_MAKEVALUE(x,S_TCR_TXRR) 183#define G_TCR_TXRR(x) _DD_GETVALUE(x,S_TCR_TXRR,M_TCR_TXRR) 184 185#define S_TCR_MXDMA 8 186#define M_TCR_MXDMA _DD_MAKEMASK(3,S_TCR_MXDMA) 187#define V_TCR_MXDMA(x) _DD_MAKEVALUE(x,S_TCR_MXDMA) 188#define G_TCR_MXDMA(x) _DD_GETVALUE(x,S_TCR_MXDMA,M_TCR_MXDMA) 189 190#define M_TCR_CRC _DD_MAKEMASK1(16) 191 192#define S_TCR_LBK 17 193#define M_TCR_LBK _DD_MAKEMASK(2,S_TCR_LBK) 194#define V_TCR_LBK(x) _DD_MAKEVALUE(x,S_TCR_LBK) 195#define G_TCR_LBK(x) _DD_GETVALUE(x,S_TCR_LBK,M_TCR_LBK) 196#define K_LBK_OFF 0x0 197#define K_LBK_ON 0x3 198 199#define M_TCR_8139G _DD_MAKEMASK1(23) 200 201#define S_TCR_IFG 24 202#define M_TCR_IFG _DD_MAKEMASK(2,S_TCR_IFG) 203#define V_TCR_IFG(x) _DD_MAKEVALUE(x,S_TCR_IFG) 204#define G_TCR_IFG(x) _DD_GETVALUE(x,S_TCR_IFG,M_TCR_IFG) 205#define K_802_3_IFG 0x3 206 207#define S_TCR_HWVERID 26 208#define M_TCR_HWVERID _DD_MAKEMASK(5,S_TCR_HWVERID) 209#define V_TCR_HWVERID(x) _DD_MAKEVALUE(x,S_TCR_HWVERID) 210#define G_TCR_HWVERID(x) _DD_GETVALUE(x,S_TCR_HWVERID,M_TCR_HWVERID) 211#define K_VER_8139 0x18 212#define K_VER_8139A 0x1C 213#define K_VER_8139B 0x1E 214#define K_VER_8130 0x1F 215#define K_VER_8139C 0x1D 216 217 218/* 0x0044 RCR: Receive Configuration Register (6.8) */ 219 220#define M_RCR_AAP _DD_MAKEMASK1(0) 221#define M_RCR_APM _DD_MAKEMASK1(1) 222#define M_RCR_AM _DD_MAKEMASK1(2) 223#define M_RCR_AB _DD_MAKEMASK1(3) 224#define M_RCR_AR _DD_MAKEMASK1(4) 225#define M_RCR_AER _DD_MAKEMASK1(5) 226#define M_RCR_9356SEL _DD_MAKEMASK1(6) 227#define M_RCR_WRAP _DD_MAKEMASK1(7) 228 229#define S_RCR_MXDMA 8 230#define M_RCR_MXDMA _DD_MAKEMASK(3,S_RCR_MXDMA) 231#define V_RCR_MXDMA(x) _DD_MAKEVALUE(x,S_RCR_MXDMA) 232#define G_RCR_MXDMA(x) _DD_GETVALUE(x,S_RCR_MXDMA,M_RCR_MXDMA) 233 234#define S_RCR_RBLEN 11 235#define M_RCR_RBLEN _DD_MAKEMASK(2,S_RCR_RBLEN) 236#define V_RCR_RBLEN(x) _DD_MAKEVALUE(x,S_RCR_RBLEN) 237#define G_RCR_RBLEN(x) _DD_GETVALUE(x,S_RCR_RBLEN,M_RCR_RBLEN) 238#define K_RBLEN_8K 0x0 239#define K_RBLEN_16K 0x1 240#define K_RBLEN_32K 0x2 241#define K_RBLEN_64K 0x3 242 243#define S_RCR_RXFTH 13 244#define M_RCR_RXFTH _DD_MAKEMASK(3,S_RCR_RXFTH) 245#define V_RCR_RXFTH(x) _DD_MAKEVALUE(x,S_RCR_RXFTH) 246#define G_RCR_RXFTH(x) _DD_GETVALUE(x,S_RCR_RXFTH,M_RCR_RXFTH) 247#define K_RXFTH_16 0x0 248#define K_RXFTH_32 0x1 249#define K_RXFTH_64 0x2 250#define K_RXFTH_128 0x3 251#define K_RXFTH_256 0x4 252#define K_RXFTH_512 0x5 253#define K_RXFTH_1024 0x6 254#define K_RXFTH_SF 0x7 255 256#define M_RCR_RER8 _DD_MAKEMASK1(16) 257#define M_RCR_MULERINT _DD_MAKEMASK1(17) 258 259#define S_RCR_ERTH 24 260#define M_RCR_ERTH _DD_MAKEMASK(4,S_RCR_ERTH) 261#define V_RCR_ERTH(x) _DD_MAKEVALUE(x,S_RCR_ERTH) 262#define G_RCR_ERTH(x) _DD_GETVALUE(x,S_RCR_ERTH,M_RCR_ERTH) 263#define K_ERTH_NONE 0 264 265 266/* Maximum DMA encodings for TCR_MXDMA and RCR_MXDMA */ 267 268#define K_MXDMA_16 0x0 269#define K_MXDMA_32 0x1 270#define K_MXDMA_64 0x2 271#define K_MXDMA_128 0x3 272#define K_MXDMA_256 0x4 273#define K_MXDMA_512 0x5 274#define K_MXDMA_1024 0x6 275#define K_MXDMA_2048 0x7 /* TCR_MXDMA */ 276#define K_MXDMA_UNLIMITED 0x7 /* RCR_MXDMA */ 277 278 279/* 0x0050 9346CR: 93C46 Command Register (6.9) */ 280 281#define M_EECR_EEDO _DD_MAKEMASK1(0) 282#define M_EECR_EEDI _DD_MAKEMASK1(1) 283#define M_EECR_EESK _DD_MAKEMASK1(2) 284#define M_EECR_EECS _DD_MAKEMASK1(3) 285 286#define S_EECR_EEM 6 287#define M_EECR_EEM _DD_MAKEMASK(2,S_EECR_EEM) 288#define V_EECR_EEM(x) _DD_MAKEVALUE(x,S_EECR_EEM) 289#define G_EECR_EEM(x) _DD_GETVALUE(x,S_EECR_EEM,M_EECR_EEM) 290#define K_EEM_NORMAL 0x0 291#define K_EEM_AUTOLOAD 0x1 292#define K_EEM_PROGRAM 0x2 293#define K_EEM_CONFIG 0x3 294 295 296/* 0x0051 CONFIG0: Configuration Register 0 (6.10) */ 297 298#define S_CFG0_BS 0 299#define M_CFG0_BS _DD_MAKEMASK(3,S_CFG0_BS) 300#define V_CFG0_BS(x) _DD_MAKEVALUE(x,S_CFG0_BS) 301#define G_CFG0_BS(x) _DD_GETVALUE(x,S_CFG0_BS,M_CFG0_BS) 302#define K_BS_NONE 0x0 303 304#define S_CFG0_PL 3 305#define M_CFG0_PL _DD_MAKEMASK(2,S_CFG0_PL) 306#define V_CFG0_PL(x) _DD_MAKEVALUE(x,S_CFG0_PL) 307#define G_CFG0_PL(x) _DD_GETVALUE(x,S_CFG0_PL,M_CFG0_PL) 308 309#define M_CFG0_T10 _DD_MAKEMASK1(5) 310#define M_CFG0_PCS _DD_MAKEMASK1(6) 311#define M_CFG0_SCR _DD_MAKEMASK1(7) 312 313 314/* 0x0052 CONFIG1: Configuration Register 1 (6.11) */ 315 316#define M_CFG1_PMEN _DD_MAKEMASK1(0) 317#define M_CFG1_VDP _DD_MAKEMASK1(1) 318#define M_CFG1_IOMAP _DD_MAKEMASK1(2) 319#define M_CFG1_MEMMAP _DD_MAKEMASK1(3) 320#define M_CFG1_LWACT _DD_MAKEMASK1(4) 321#define M_CFG1_DVRLOAD _DD_MAKEMASK1(5) 322 323#define S_CFG1_LEDS 6 324#define M_CFG1_LEDS _DD_MAKEMASK(2,S_CFG1_LEDS) 325#define V_CFG1_LEDS(x) _DD_MAKEVALUE(x,S_CFG1_LEDS) 326#define G_CFG1_LEDS(x) _DD_GETVALUE(x,S_CFG1_LEDS,M_CFG1_LEDS) 327 328 329/* 0x0058 MSR: Media Status Register (6.12) */ 330 331#define M_MSR_RXPF _DD_MAKEMASK1(0) 332#define M_MSR_TXPF _DD_MAKEMASK1(1) 333#define M_MSR_LINKB _DD_MAKEMASK1(2) 334#define M_MSR_SPEED_10 _DD_MAKEMASK1(3) 335#define M_MSR_AUX_STATUS _DD_MAKEMASK1(4) 336#define M_MSR_RXFCE _DD_MAKEMASK1(6) 337#define M_MSR_TXFCE _DD_MAKEMASK1(7) 338 339 340/* 0x0059 CONFIG3: Configuration Register 3 (6.13) */ 341 342#define M_CFG3_FBTB_EN _DD_MAKEMASK1(0) 343#define M_CFG3_FUNCREG_EN _DD_MAKEMASK1(1) 344#define M_CFG3_CLKRUN_EN _DD_MAKEMASK1(2) 345#define M_CFG3_CARDB_EN _DD_MAKEMASK1(3) 346#define M_CFG3_LINKUP _DD_MAKEMASK1(4) 347#define M_CFG3_MAGIC _DD_MAKEMASK1(5) 348#define M_CFG3_PARM_EN _DD_MAKEMASK1(6) 349#define M_CFG3_GNTSEL _DD_MAKEMASK1(7) 350 351 352/* 0x005A CONFIG4: Configuration Register 4 (6.14) */ 353 354#define M_CFG4_PBWAKEUP _DD_MAKEMASK1(0) 355#define M_CFG4_LWPTN _DD_MAKEMASK1(2) 356#define M_CFG4_LWPME _DD_MAKEMASK1(4) 357#define M_CFG4_LONGWF _DD_MAKEMASK1(5) 358#define M_CFG4_ANAOFF _DD_MAKEMASK1(6) 359#define M_CFG4_RXFIFOAUTOCLR _DD_MAKEMASK1(7) 360 361 362/* 0x005C MULINT: Multiple Interrupt Select Register (6.15) */ 363 364#define S_MULINT_MISR 0 365#define M_MULINT_MISR _DD_MAKEMASK(12,S_MULINT_MISR) 366#define V_MULINT_MISR(x) _DD_MAKEVALUE(x,S_MULINT_MISR) 367#define G_MULINT_MISR(x) _DD_GETVALUE(x,S_MULINT_MISR,M_MULINT_MISR) 368 369 370/* 0x0060 TSDS (TSAD): Transmit Status of All Descriptors Register (6.17) */ 371 372#define M_TSDS_OWN(i) _DD_MAKEMASK1(0+(i)) 373#define M_TSDS_TABT(i) _DD_MAKEMASK1(4+(i)) 374#define M_TSDS_TUN(i) _DD_MAKEMASK1(8+(i)) 375#define M_TSDS_TOK(i) _DD_MAKEMASK1(12+(i)) 376 377 378/* 0x0070 NWAYTR: NWay Test Register (6.25) */ 379 380#define M_NWAYTR_FLAGLSC _DD_MAKEMASK1(0) 381#define M_NWAYTR_FLAGPDF _DD_MAKEMASK1(1) 382#define M_NWAYTR_FLAGABD _DD_MAKEMASK1(2) 383#define M_NWAYTR_ENNWLE _DD_MAKEMASK1(3) 384#define M_NWAYTR_NWLPBK _DD_MAKEMASK1(7) 385 386 387/* 0x0074 CSCR: CS Configuration Register (6.27) */ 388 389#define M_CSCR_PASS_SCR _DD_MAKEMASK1(0) 390#define M_CSCR_CONN_STATUS_EN _DD_MAKEMASK1(2) 391#define M_CSCR_CON_STATUS _DD_MAKEMASK1(3) 392#define M_CSCR_F_CONNECT _DD_MAKEMASK1(5) 393#define M_CSCR_F_LINK_100 _DD_MAKEMASK1(6) 394#define M_CSCR_JBEN _DD_MAKEMASK1(7) 395#define M_CSCR_HEART_BEAT _DD_MAKEMASK1(8) 396#define M_CSCR_LD _DD_MAKEMASK1(9) 397#define M_CSCR_TESTFUN _DD_MAKEMASK1(15) 398 399 400/* 0x00D4 FLASH: Flash Memory Read/Write Register */ 401 402#define S_FLASH_MA 0 403#define M_FLASH_MA _DD_MAKEMASK(16,S_FLASH_MA) 404#define V_FLASH_MA(x) _DD_MAKEVALUE(x,S_FLASH_MA) 405#define G_FLASH_MA(x) _DD_GETVALUE(x,S_FLASH_MA,M_FLASH_MA) 406 407#define M_FLASH_SWRWEN _DD_MAKEMASK1(17) 408#define M_FLASH_WEB _DD_MAKEMASK1(18) 409#define M_FLASH_OEB _DD_MAKEMASK1(19) 410#define M_FLASH_ROMCSB _DD_MAKEMASK1(20) 411 412#define S_FLASH_MD 24 413#define M_FLASH_MD _DD_MAKEMASK(8,S_FLASH_MD) 414#define V_FLASH_MD(x) _DD_MAKEVALUE(x,S_FLASH_MD) 415#define G_FLASH_MD(x) _DD_GETVALUE(x,S_FLASH_MD,M_FLASH_MD) 416 417 418/* 0x00D8 CONFIG5: Configuration Register 5 */ 419 420#define M_CFG5_PME_STS _DD_MAKEMASK1(0) 421#define M_CFG5_LANWAKE _DD_MAKEMASK1(1) 422#define M_CFG5_LDPS _DD_MAKEMASK1(2) 423#define M_CFG5_FIFOADDRPTR _DD_MAKEMASK1(3) 424#define M_CFG5_UWF _DD_MAKEMASK1(4) 425#define M_CFG5_MWF _DD_MAKEMASK1(5) 426#define M_CFG5_BWF _DD_MAKEMASK1(6) 427 428 429/* The 8139 does not use a descriptor ring. There is a contiguous 430 ring buffer for received packets, and each packet is preceded by a 431 (little endian) status word with the following format. */ 432 433#define M_RS_ROK _DD_MAKEMASK1(0) 434#define M_RS_FAE _DD_MAKEMASK1(1) 435#define M_RS_CRC _DD_MAKEMASK1(2) 436#define M_RS_LONG _DD_MAKEMASK1(3) 437#define M_RS_RUNT _DD_MAKEMASK1(4) 438#define M_RS_ISE _DD_MAKEMASK1(5) 439#define M_RS_BAR _DD_MAKEMASK1(13) 440#define M_RS_PAM _DD_MAKEMASK1(14) 441#define M_RS_MAR _DD_MAKEMASK1(15) 442#define S_RS_LEN 16 443#define M_RS_LEN _DD_MAKEMASK(16,S_RS_LEN) 444#define V_RS_LEN(x) _DD_MAKEVALUE(x,S_RS_LEN) 445#define G_RS_LEN(x) _DD_GETVALUE(x,S_RS_LEN,M_RS_LEN) 446 447#endif /* _RTL8139_H_ */ 448