1/* 2 * Register and bit definitions for the DEC/Intel 21143 Ethernet controller, 3 * part of the Tulip family of 10 and 10/100 controllers. 4 * Reference: 5 * 21143 PCI/CardBus 10/100 Mb/s Ethernet LAN Controller, 6 * Hardware Reference Manual, Revision 1.0. 7 * Document No. 278074-001 8 * Intel Corp., October 1998 9 * Includes extensions/alternatives for the DEC 21040, 21041 and 21140(A) 10 * Ethernet controllers. 11 */ 12#ifndef _DC21143_H_ 13#define _DC21143_H_ 14 15#define _DD_MAKEMASK1(n) (1 << (n)) 16#define _DD_MAKEMASK(v,n) ((((1)<<(v))-1) << (n)) 17#define _DD_MAKEVALUE(v,n) ((v) << (n)) 18#define _DD_GETVALUE(v,n,m) (((v) & (m)) >> (n)) 19 20 21/* ********************************************************************* 22 * PCI Configuration Register offsets (Tulip nomenclature) 23 ********************************************************************* */ 24 25#define R_CFG_CFID PCI_ID_REG 26#define K_PCI_VENDOR_DEC 0x1011 27#define K_PCI_ID_DC21040 0x0002 28#define K_PCI_ID_DC21041 0x0014 29#define K_PCI_ID_DC21140 0x0009 30#define K_PCI_ID_DC21143 0x0019 31 32#define R_CFG_CFRV PCI_CLASS_REG 33 34#define R_CFG_CBIO PCI_MAPREG(0) 35#define R_CFG_CBMA PCI_MAPREG(1) 36 37#define R_CFG_CFIT PCI_BPARAM_INTERRUPT_REG 38 39/* Tulip extensions */ 40#define R_CFG_CFDD 0x40 41 42#define M_CFDD_SLEEP __DD_MAKEMASK1(31) 43#define M_CFDD_SNOOZE __DD_MAKEMASK1(30) 44 45#define R_CFG_CPMS 0xE0 46 47 48/* ********************************************************************* 49 * CSRs: offsets 50 ********************************************************************* */ 51 52#define R_CSR_BUSMODE 0x00 53#define R_CSR_TXPOLL 0x08 54#define R_CSR_RXPOLL 0x10 55#define R_CSR_RXRING 0x18 56#define R_CSR_TXRING 0x20 57#define R_CSR_STATUS 0x28 58#define R_CSR_OPMODE 0x30 59#define R_CSR_INTMASK 0x38 60#define R_CSR_MISSEDFRAME 0x40 61#define R_CSR_ROM_MII 0x48 62#define R_CSR_BOOTROM_ADDR 0x50 63#define R_CSR_GENTIMER 0x58 64 65/* The following registers are specific to the 21040 */ 66 67#define R_CSR_FDUPLEX 0x58 68 69/* The following registers are specific to the 21040/21041 and 21142/21143 */ 70 71#define R_CSR_SIASTATUS 0x60 72#define R_CSR_SIAMODE0 0x68 73#define R_CSR_SIAMODE1 0x70 74#define R_CSR_SIAMODE2 0x78 75 76/* The following registers are specific to the 21140/21140A */ 77 78#define R_CSR_GENPORT 0x60 79#define R_CSR_WATCHDOG_TIMER 0x78 80 81 82/* CSR0: Bus Mode register */ 83 84#define M_CSR0_SWRESET _DD_MAKEMASK1(0) 85#define M_CSR0_BUSARB _DD_MAKEMASK1(1) 86 87#define S_CSR0_SKIPLEN 2 88#define M_CSR0_SKIPLEN _DD_MAKEMASK(5,S_CSR0_SKIPLEN) 89#define V_CSR0_SKIPLEN(x) _DD_MAKEVALUE(x,S_CSR0_SKIPLEN) 90#define G_CSR0_SKIPLEN(x) _DD_GETVALUE(x,S_CSR0_SKIPLEN,M_CSR0_SKIPLEN) 91 92#define M_CSR0_BIGENDIAN _DD_MAKEMASK1(7) 93 94#define S_CSR0_BURSTLEN 8 95#define M_CSR0_BURSTLEN _DD_MAKEMASK(6,S_CSR0_BURSTLEN) 96#define V_CSR0_BURSTLEN(x) _DD_MAKEVALUE(x,S_CSR0_BURSTLEN) 97#define G_CSR0_BURSTLEN(x) _DD_GETVALUE(x,S_CSR0_BURSTLEN,M_CSR0_BURSTLEN) 98 99#define S_CSR0_CACHEALIGN 14 100#define M_CSR0_CACHEALIGN _DD_MAKEMASK(2,S_CSR0_CACHEALIGN) 101#define V_CSR0_CACHEALIGN(x) _DD_MAKEVALUE(x,S_CSR0_CACHEALIGN) 102#define G_CSR0_CACHEALIGN(x) _DD_GETVALUE(x,S_CSR0_CACHEALIGN,M_CSR0_CACHEALIGN) 103 104#define S_CSR0_TXAUTOPOLL 17 105#define M_CSR0_TXAUTOPOLL _DD_MAKEMASK(3,S_CSR0_AUTOPOLL) 106#define V_CSR0_TXAUTOPOLL(x) _DD_MAKEVALUE(x,S_CSR0_TXAUTOPOLL) 107#define G_CSR0_TXAUTOPOLL(x) _DD_GETVALUE(x,S_CSR0_TXAUTOPOLL,M_CSR0_TXAUTOPOLL) 108 109#define M_CSR0_DESCBYTEORDER _DD_MAKEMASK1(20) /* not 21040 */ 110#define M_CSR0_READMULTENAB _DD_MAKEMASK1(21) /* not 2104{0,1} */ 111#define M_CSR0_READLINEENAB _DD_MAKEMASK1(23) /* not 2104{0,1} */ 112#define M_CSR0_WRITEINVALENAB _DD_MAKEMASK1(24) /* not 2104{0,1} */ 113 114#define K_CSR0_TAPDISABLED 0x00 115#define K_CSR0_TAP200US 0x01 116#define K_CSR0_TAP800US 0x02 117#define K_CSR0_TAP1600US 0x03 118 119#define K_CSR0_ALIGNNONE 0 120#define K_CSR0_ALIGN32 1 121#define K_CSR0_ALIGN64 2 122#define K_CSR0_ALIGN128 3 123 124#define K_CSR0_BURST32 32 125#define K_CSR0_BURST16 16 126#define K_CSR0_BURST8 8 127#define K_CSR0_BURST4 4 128#define K_CSR0_BURST2 2 129#define K_CSR0_BURST1 1 130#define K_CSR0_BURSTANY 0 131 132 133#define M_CSR3_RXDSCRADDR 0xFFFFFFFC 134#define M_CSR4_TXDSCRADDR 0xFFFFFFFC 135 136 137/* CSR5: Status register */ 138 139#define M_CSR5_TXINT _DD_MAKEMASK1(0) 140#define M_CSR5_TXSTOP _DD_MAKEMASK1(1) 141#define M_CSR5_TXBUFUNAVAIL _DD_MAKEMASK1(2) 142#define M_CSR5_TXJABTIMEOUT _DD_MAKEMASK1(3) 143#define M_CSR5_LINKPASS _DD_MAKEMASK1(4) /* not 21040 */ 144#define M_CSR5_TXUNDERFLOW _DD_MAKEMASK1(5) 145#define M_CSR5_RXINT _DD_MAKEMASK1(6) 146#define M_CSR5_RXBUFUNAVAIL _DD_MAKEMASK1(7) 147#define M_CSR5_RXSTOPPED _DD_MAKEMASK1(8) 148#define M_CSR5_RXWDOGTIMEOUT _DD_MAKEMASK1(9) 149#define M_CSR5_AUITPPIN _DD_MAKEMASK1(10) /* 21040 only */ 150#define M_CSR5_TXEARLYINT _DD_MAKEMASK1(10) /* not 2104{0,1} */ 151#define M_CSR5_FDSHORTFRAME _DD_MAKEMASK1(11) /* 21040 only */ 152#define M_CSR5_GPTIMEREXPIRE _DD_MAKEMASK1(11) /* not 21040 */ 153#define M_CSR5_LINKFAIL _DD_MAKEMASK1(12) 154#define M_CSR5_FATALBUSERROR _DD_MAKEMASK1(13) 155#define M_CSR5_RXEARLYINT _DD_MAKEMASK1(14) /* not 21040 */ 156#define M_CSR5_ABNORMALINT _DD_MAKEMASK1(15) 157#define M_CSR5_NORMALINT _DD_MAKEMASK1(16) 158 159#define S_CSR5_RXPROCSTATE 17 160#define M_CSR5_RXPROCSTATE _DD_MAKEMASK(3,S_CSR5_RXPROCSTATE) 161#define V_CSR5_RXPROCSTATE(x) _DD_MAKEVALUE(x,S_CSR5_RXPROCSTATE) 162#define G_CSR5_RXPROCSTATE(x) _DD_GETVALUE(x,S_CSR5_RXPROCSTATE,M_CSR5_RXPROCSTATE) 163 164#define K_CSR5_RXSTOPPED 0x00 /* RESET or STOP command */ 165#define K_CSR5_RXFETCH 0x01 /* fetching rx desc */ 166#define K_CSR5_RXCHECK 0x02 /* checking end of rx pkt */ 167#define K_CSR5_RXWAIT 0x03 /* waiting for rx pkt */ 168#define K_CSR5_RXSUSPEND 0x04 /* unavailable rx buffer */ 169#define K_CSR5_RXCLOSE 0x05 /* closing rx desc */ 170#define K_CSR5_RXFLUSH 0x06 /* flushing rx frame */ 171#define K_CSR5_RXQUEUE 0x07 /* reading rx frame from FIFO */ 172 173#define S_CSR5_TXPROCSTATE 20 174#define M_CSR5_TXPROCSTATE _DD_MAKEMASK(3,S_CSR5_TXPROCSTATE) 175#define V_CSR5_TXPROCSTATE(x) _DD_MAKEVALUE(x,S_CSR5_TXPROCSTATE) 176#define G_CSR5_TXPROCSTATE(x) _DD_GETVALUE(x,S_CSR5_TXPROCSTATE,M_CSR5_TXPROCSTATE) 177 178#define K_CSR5_TXSTOPPED 0x00 /* RESET or STOP command */ 179#define K_CSR5_TXFETCH 0x01 /* fetching tx desc */ 180#define K_CSR5_TXWAIT 0x02 /* waiting for end of tx */ 181#define K_CSR5_TXREAD 0x03 /* reading buffer into FIFO */ 182#define K_CSR5_TXSETUP 0x05 /* setup packet */ 183#define K_CSR5_TXSUSPEND 0x06 /* tx underflow or no tx desc */ 184#define K_CSR5_TXCLOSE 0x07 /* closing tx desc */ 185 186#define S_CSR5_ERRORBITS 23 187#define M_CSR5_ERRORBITS _DD_MAKEMASK(3,S_CSR5_ERRORBITS) 188#define V_CSR5_ERRORBITS(x) _DD_MAKEVALUE(x,S_CSR5_ERRORBITS) 189#define G_CSR5_ERRORBITS(x) _DD_GETVALUE(x,S_CSR5_ERRORBITS,M_CSR5_ERRORBITS) 190 191#define K_CSR5_FBE_PARITY 0x00 192#define K_CSR5_FBE_MABORT 0x01 193#define K_CSR5_FBE_TABORT 0x02 194 195#define M_CSR5_GPPORTINT _DD_MAKEMASK1(26) /* not 2104{0,1} */ 196#define M_CSR5_LINKCHANGED _DD_MAKEMASK1(27) /* not 2104{0,1} */ 197 198 199/* CSR6: Operating Mode register */ 200 201#define M_CSR6_RXHASHFILT _DD_MAKEMASK1(0) 202#define M_CSR6_RXSTART _DD_MAKEMASK1(1) 203#define M_CSR6_HASHONLY _DD_MAKEMASK1(2) 204#define M_CSR6_PASSBADFRAMES _DD_MAKEMASK1(3) 205#define M_CSR6_INVERSEFILT _DD_MAKEMASK1(4) 206#define M_CSR6_STOPBACKOFF _DD_MAKEMASK1(5) 207#define M_CSR6_PROMISCUOUS _DD_MAKEMASK1(6) 208#define M_CSR6_PASSALLMULTI _DD_MAKEMASK1(7) 209#define M_CSR6_FULLDUPLEX _DD_MAKEMASK1(9) 210 211#define M_CSR6_INTLOOPBACK _DD_MAKEMASK1(10) 212#define M_CSR6_EXTLOOPBACK _DD_MAKEMASK1(11) 213 214#define S_CSR6_OPMODE 10 215#define M_CSR6_OPMODE _DD_MAKEMASK(2,S_CSR6_OPMODE) 216#define V_CSR6_OPMODE(x) _DD_MAKEVALUE(x,S_CSR6_OPMODE) 217#define G_CSR6_OPMODE(x) _DD_GETVALUE(x,S_CSR6_OPMODE,M_CSR6_OPMODE) 218 219#define M_CSR6_FORCECOLL _DD_MAKEMASK1(12) 220#define M_CSR6_TXSTART _DD_MAKEMASK1(13) 221 222#define S_CSR6_THRESHCONTROL 14 223#define M_CSR6_THRESHCONTROL _DD_MAKEMASK(2,S_CSR6_THRESHCONTROL) 224#define V_CSR6_THRESHCONTROL(x) _DD_MAKEVALUE(x,S_CSR6_THRESHCONTROL) 225#define G_CSR6_THRESHCONTROL(x) _DD_GETVALUE(x,S_CSR6_THRESHCONTROL,M_CSR6_THRESHCONTROL) 226 227#define M_CSR6_BACKPRESSURE _DD_MAKEMASK1(16) /* 21040 only */ 228#define M_CSR6_CAPTUREEFFECT _DD_MAKEMASK1(17) 229 230#define M_CSR6_PORTSEL _DD_MAKEMASK1(18) /* not 2104{0,1} */ 231#define M_CSR6_HBDISABLE _DD_MAKEMASK1(19) /* not 2104{0,1} */ 232#define M_CSR6_STOREFWD _DD_MAKEMASK1(21) /* not 2104{0,1} */ 233#define M_CSR6_TXTHRESH _DD_MAKEMASK1(22) /* not 2104{0,1} */ 234#define M_CSR6_PCSFUNC _DD_MAKEMASK1(23) /* not 2104{0,1} */ 235#define M_CSR6_SCRAMMODE _DD_MAKEMASK1(24) /* not 2104{0,1} */ 236#define M_CSR6_MBO _DD_MAKEMASK1(25) /* not 2104{0,1} */ 237#define M_CSR6_RXALL _DD_MAKEMASK1(30) /* not 2104{0,1} */ 238 239#define M_CSR6_SPECCAP _DD_MAKEMASK1(31) /* not 21040 */ 240 241#define K_CSR6_TXTHRES_128_72 0x00 242#define K_CSR6_TXTHRES_256_96 0x01 243#define K_CSR6_TXTHRES_512_128 0x02 244#define K_CSR6_TXTHRES_1024_160 0x03 245 246 247#define M_CSR6_SPEED_10 (M_CSR6_TXTHRESH) 248 249#define M_CSR6_SPEED_100 (M_CSR6_HBDISABLE | \ 250 M_CSR6_SCRAMMODE | \ 251 M_CSR6_PCSFUNC | \ 252 M_CSR6_PORTSEL) 253 254#define M_CSR6_SPEED_10_MII (M_CSR6_TXTHRESH | \ 255 M_CSR6_PORTSEL) 256 257#define M_CSR6_SPEED_100_MII (M_CSR6_HBDISABLE | \ 258 M_CSR6_PORTSEL) 259 260 261/* CSR7: Interrupt mask register */ 262 263#define M_CSR7_TXINT _DD_MAKEMASK1(0) 264#define M_CSR7_TXSTOP _DD_MAKEMASK1(1) 265#define M_CSR7_TXBUFUNAVAIL _DD_MAKEMASK1(2) 266#define M_CSR7_TXJABTIMEOUT _DD_MAKEMASK1(3) 267#define M_CSR7_LINKPASS _DD_MAKEMASK1(4) /* not 21040 */ 268#define M_CSR7_TXUNDERFLOW _DD_MAKEMASK1(5) 269#define M_CSR7_RXINT _DD_MAKEMASK1(6) 270#define M_CSR7_RXBUFUNAVAIL _DD_MAKEMASK1(7) 271#define M_CSR7_RXSTOPPED _DD_MAKEMASK1(8) 272#define M_CSR7_RXWDOGTIMEOUT _DD_MAKEMASK1(9) 273#define M_CSR7_AUITPSW _DD_MAKEMASK1(10) /* 21040 only */ 274#define M_CSR7_TXEARLY _DD_MAKEMASK1(10) /* not 2104{0,1} */ 275#define M_CSR7_FD _DD_MAKEMASK1(11) /* 21040 only */ 276#define M_CSR7_GPTIMER _DD_MAKEMASK1(11) /* not 21040 */ 277#define M_CSR7_LINKFAIL _DD_MAKEMASK1(12) 278#define M_CSR7_FATALBUSERROR _DD_MAKEMASK1(13) 279#define M_CSR7_RXEARLY _DD_MAKEMASK1(14) /* not 21040 */ 280#define M_CSR7_ABNORMALINT _DD_MAKEMASK1(15) 281#define M_CSR7_NORMALINT _DD_MAKEMASK1(16) 282#define M_CSR7_GPPORT _DD_MAKEMASK1(26) /* not 2104{0,1} */ 283#define M_CSR7_LINKCHANGED _DD_MAKEMASK1(27) /* not 2104{0,1} */ 284 285 286/* CSR8: Missed Frame register */ 287 288#define M_CSR8_RXOVER_WRAP _DD_MAKEMASK1(28) /* not 2104{0,1} */ 289#define S_CSR8_RXOVER 17 290#define M_CSR8_RXOVER _DD_MAKEMASK(11,S_CSR8_RXOVER) /* not 2104{0,1} */ 291#define V_CSR8_RXOVER(x) _DD_MAKEVALUE(x,S_CSR8_RXOVER) 292#define G_CSR8_RXOVER(x) _DD_GETVALUE(x,S_CSR8_RXOVER,M_CSR8_RXOVER) 293 294#define M_CSR8_MISSEDWRAP _DD_MAKEMASK1(16) 295#define S_CSR8_MISSED 0 296#define M_CSR8_MISSED _DD_MAKEMASK(16,S_CSR8_MISSED) 297#define V_CSR8_MISSED(x) _DD_MAKEVALUE(x,S_CSR8_MISSED) 298#define G_CSR8_MISSED(x) _DD_GETVALUE(x,S_CSR8_MISSED,M_CSR8_MISSED) 299 300 301/* CSR9: ROM and MII register */ 302 303#define S_CSR9_ROMDATA 0 304#define M_CSR9_ROMDATA _DD_MAKEMASK(8,S_CSR9_ROMDATA) 305#define V_CSR9_ROMDATA(x) _DD_MAKEVALUE(x,S_CSR9_ROMDATA) 306#define G_CSR9_ROMDATA(x) _DD_GETVALUE(x,S_CSR9_ROMDATA,M_CSR9_ROMDATA) 307 308#define M_CSR9_SROMCHIPSEL _DD_MAKEMASK1(0) /* not 21040 */ 309#define M_CSR9_SROMCLOCK _DD_MAKEMASK1(1) /* not 21040 */ 310#define M_CSR9_SROMDATAIN _DD_MAKEMASK1(2) /* not 21040 */ 311#define M_CSR9_SROMDATAOUT _DD_MAKEMASK1(3) /* not 21040 */ 312 313#define M_CSR9_REGSELECT _DD_MAKEMASK1(10) /* not 21040 */ 314#define M_CSR9_SERROMSEL _DD_MAKEMASK1(11) /* not 21040 */ 315#define M_CSR9_ROMSEL _DD_MAKEMASK1(12) /* not 21040 */ 316#define M_CSR9_ROMWRITE _DD_MAKEMASK1(13) /* not 21040 */ 317#define M_CSR9_ROMREAD _DD_MAKEMASK1(14) /* not 21040 */ 318#define M_CSR9_MODESEL _DD_MAKEMASK1(15) /* 21041 only */ 319#define M_CSR9_MDC _DD_MAKEMASK1(16) /* not 2104{0,1} */ 320#define M_CSR9_MDO _DD_MAKEMASK1(17) /* not 2104{0,1} */ 321#define M_CSR9_MIIMODE _DD_MAKEMASK1(18) /* not 2104{0,1} */ 322#define M_CSR9_MDI _DD_MAKEMASK1(19) /* not 2104{0,1} */ 323 324#define M_CSR9_DATANOTVALID _DD_MAKEMASK1(31) /* 21040 only */ 325 326#define M_CSR10_BOOTROMADDR _DD_MAKEMASK(18,0) /* not 21040 */ 327 328 329/* CSR11 General Purpose Timer register */ 330 331#define S_CSR11_GPTIMER 0 /* not 21040 */ 332#define M_CSR11_GPTIMER _DD_MAKEMASK(16,S_CSR11_GPTIMER) 333#define V_CSR11_GPTIMER(x) _DD_MAKEVALUE(x,S_CSR11_GPTIMER) 334#define G_CSR11_GPTIMER(x) _DD_GETVALUE(x,S_CSR11_GPTIMER,M_CSR11_GPTIMER) 335 336 337#define M_CSR11_GPTIMERCONT _DD_MAKEMASK1(16) /* not 21040 */ 338 339#define S_CSR11_FDAUTOCONF 0 /* 21040 only */ 340#define M_CSR11_FDAUTOCONF _DD_MAKEMASK(16,S_CSR11_FDAUTOCONF) 341#define V_CSR11_FDAUTOCONF(x) _DD_MAKEVALUE(x,S_CSR11_FDAUTOCONF) 342#define G_CSR11_FRAUTOCONF(x) _DD_GETVALUE(x,S_CSR11_FDAUTOCONF,M_CSR11_AUTOCONF) 343 344 345/* CSR12: SIA Status register (21143) */ 346 347#define M_CSR12_MIIRPA _DD_MAKEMASK1(0) 348#define M_CSR12_100MBLINK _DD_MAKEMASK1(1) 349#define M_CSR12_10MBLINK _DD_MAKEMASK1(2) 350#define M_CSR12_AUTOPOLSTATE _DD_MAKEMASK1(3) 351 352#define M_CSR12_RXAUIACT _DD_MAKEMASK1(8) 353#define M_CSR12_RX10BASETACT _DD_MAKEMASK1(9) 354#define M_CSR12_NLPDETECT _DD_MAKEMASK1(10) 355#define M_CSR12_TXREMFAULT _DD_MAKEMASK1(11) 356 357#define S_CSR12_AUTONEGARBIT 12 358#define M_CSR12_AUTONEGARBIT _DD_MAKEMASK(3,S_CSR12_AUTONEGARBIT) 359#define V_CSR12_AUTONEGARBIT(x) _DD_MAKEVALUE(x,S_CSR12_AUTONEGARBIT) 360#define G_CSR12_AUTONEGARBIT(x) _DD_GETVALUE(x,S_CSR12_AUTONEGARBIT,M_CSR12_AUTONEGARBIT) 361 362#define M_CSR12_LINKPARTNEG _DD_MAKEMASK1(15) 363 364#define S_CSR12_LINKPARTCODE 16 365#define M_CSR12_LINKPARTCODE _DD_MAKEMASK(16,S_CSR12_LINKPARTCODE) 366#define V_CSR12_LINKPARTCODE(x) _DD_MAKEVALUE(x,S_CSR12_LINKPARTCODE) 367#define G_CSR12_LINKPARTCODE(x) _DD_GETVALUE(x,S_CSR12_LINKPARTCODE,M_CSR12_LINKPARTCODE) 368 369 370/* CSR12: SIA Status register (21041, also 31:12, 3:3 as for 21143) */ 371 372#define M_CSR12_NETCONNERR _DD_MAKEMASK1(1) 373#define M_CSR12_LINKFAIL _DD_MAKEMASK1(2) 374#define M_CSR12_SELPORTACT _DD_MAKEMASK1(8) 375#define M_CSR12_NONSELPORTACT _DD_MAKEMASK1(9) 376#define M_CSR12_AUTONEGRESTART _DD_MAKEMASK1(10) 377#define M_CSR12_UNSTABLENLP _DD_MAKEMASK1(11) 378 379 380/* CSR12: General Purpose Port register (21140) */ 381 382#define S_CSR12_DATA 0 383#define M_CSR12_DATA _DD_MAKEMASK(8,S_CSR12_DATA) 384#define V_CSR12_DATA _DD_MAKEVALUE(x,S_CSR12_DATA,M_CSR12_DATA) 385#define G_CSR12_DATA(x) _DD_GETVALUE(x,S_CSR12_DATA,M_CSR12_DATA) 386 387#define M_CSR12_CONTROL _DD_MAKEMASK1(8) 388 389 390/* CSR13: SIA Mode 0 register (21143 and 21041) */ 391 392#define M_CSR13_CONN_NOT_RESET _DD_MAKEMASK1(0) 393#define M_CSR13_CONN_CSR_AUTO _DD_MAKEMAKS1(2) /* 21041 only */ 394#define M_CSR13_CONN_AUI_10BT _DD_MAKEMASK1(3) 395 396 397/* CSR14: SIA Mode 1 register (21143 and 21041) */ 398 399#define M_CSR14_ENCODER _DD_MAKEMASK1(0) 400#define M_CSR14_LOOPBACK _DD_MAKEMASK1(1) 401#define M_CSR14_DRIVER _DD_MAKEMASK1(2) 402#define M_CSR14_LINKPULSE _DD_MAKEMASK1(3) 403 404#define S_CSR14_COMPENSATE 4 405#define M_CSR14_COMPENSATE _DD_MAKEMASK(2,S_CSR14_COMPENSATE) 406#define V_CSR14_COMPENSATE(x) _DD_MAKEVALUE(x,S_CSR14_COMPENSATE) 407#define G_CSR14_COMPENSATE(x) _DD_GETVALUE(x,S_CSR14_COMPENSATE,M_CSR14_COMPENSATE) 408 409#define M_CSR14_HALFDUPLEX10BASET _DD_MAKEMASK1(6) 410#define M_CSR14_AUTONEGOTIATE _DD_MAKEMASK1(7) 411#define M_CSR14_RXSQUELCH _DD_MAKEMASK1(8) 412#define M_CSR14_COLLSQUELCH _DD_MAKEMASK1(9) 413#define M_CSR14_COLLDETECT _DD_MAKEMASK1(10) 414#define M_CSR14_SIGQUALGEN _DD_MAKEMASK1(11) 415#define M_CSR14_LINKTEST _DD_MAKEMASK1(12) 416#define M_CSR14_AUTOPOLARITY _DD_MAKEMASK1(13) 417#define M_CSR14_SETPOLARITY _DD_MAKEMASK1(14) 418#define M_CSR14_10BASETAUIAUTO _DD_MAKEMASK1(15) 419#define M_CSR14_100BASETHALFDUP _DD_MAKEMASK1(16) /* not 21041 */ 420#define M_CSR14_100BASETFULLDUP _DD_MAKEMASK1(17) /* not 21041 */ 421#define M_CSR14_100BASET4 _DD_MAKEMASK1(18) /* not 21041 */ 422 423#define M_CSR14_10BT_HD 0x7F3F 424#define M_CSR14_10BT_FD 0x7F3D 425 426 427/* CSR15: SIA Mode 2 register (21143 and 21041) */ 428 429#define M_CSR15_GP_JABBERDIS _DD_MAKEMASK1(0) /* 21041 only */ 430#define M_CSR15_GP_HOSTUNJAB _DD_MAKEMASK1(1) 431#define M_CSR15_GP_JABBERCLK _DD_MAKEMASK1(2) 432#define M_CSR15_GP_AUIBNC _DD_MAKEMASK1(3) 433#define M_CSR15_GP_RXWATCHDIS _DD_MAKEMASK1(4) 434#define M_CSR15_GP_RXWATCHREL _DD_MAKEMASK1(5) 435 436/* (CSR15: 21143 only) */ 437 438#define S_CSR15_GP_GPDATA 16 439#define M_CSR15_GP_GPDATA _DD_MAKEMASK(4,S_CSR15_GP_GPDATA) 440#define V_CSR15_GP_GPDATA(x) _DD_MAKEVALUE(x,S_CSR15_GP_GPDATA) 441#define G_CSR15_GP_GPDATA(x) _DD_GETVALUE(x,S_CSR15_GP_GPDATA,M_CSR15_GP_GPDATA) 442 443#define M_CSR15_GP_LED0 _DD_MAKEMASK1(20) 444#define M_CSR15_GP_LED1 _DD_MAKEMASK1(21) 445#define M_CSR15_GP_LED2 _DD_MAKEMASK1(22) 446#define M_CSR15_GP_LED3 _DD_MAKEMASK1(23) 447#define M_CSR15_GP_INTPORT0 _DD_MAKEMASK1(24) 448#define M_CSR15_GP_INTPORT1 _DD_MAKEMASK1(25) 449#define M_CSR15_GP_RXMATCH _DD_MAKEMASK1(26) 450#define M_CSR15_GP_CONTROLWRITE _DD_MAKEMASK1(27) 451#define M_CSR15_GP_GPINT0 _DD_MAKEMASK1(28) 452#define M_CSR15_GP_GPINT1 _DD_MAKEMASK1(29) 453#define M_CSR15_GP_RXMATCHINT _DD_MAKEMASK1(30) 454 455#define M_CSR15_DEFAULT_VALUE 0x00050008 456#define M_CSR15_CONFIG_GEPS_LEDS 0x08af0000 457 458/* (CSR15: 21041 only) */ 459 460#define M_CSR15_GP_LED1ENB _DD_MAKEMASK1(6) 461#define M_CSR15_GP_LED1VALUE _DD_MAKEMASK1(7) 462#define M_CSR15_GP_TSTCLK _DD_MAKEMASK1(8) 463#define M_CSR15_GP_FORCEUNSQ _DD_MAKEMASK1(9) 464#define M_CSR15_GP_FORCEFAIL _DD_MAKEMASK1(10) 465#define M_CSR15_GP_LEDSTRDIS _DD_MAKEMASK1(11) 466#define M_CSR15_GP_PLLTEST _DD_MAKEMASK1(12) 467#define M_CSR15_GP_FORCERXLOW _DD_MAKEMASK1(13) 468#define M_CSR15_GP_LED2ENB _DD_MAKEMASK1(14) 469#define M_CSR15_GP_LED2VALUE _DD_MAKEMASK1(15) 470 471 472/* CSR15: Watchdog Timer register (21140) */ 473 474#define M_CSR15_WT_JABBER _DD_MAKEMASK1(0) 475#define M_CSR15_WT_HOSTUNJAB _DD_MAKEMASK1(1) 476#define M_CSR15_WT_JABBERCLK _DD_MAKEMASK1(2) 477#define M_CSR15_WT_RXWATCHDIS _DD_MAKEMASK1(4) 478#define M_CSR15_WT_RXWATCHREL _DD_MAKEMASK1(5) 479 480 481/* ********************************************************************* 482 * Receive Descriptors 483 ********************************************************************* */ 484 485#define M_RDES0_OWNSYS 0 486#define M_RDES0_OWNADAP _DD_MAKEMASK1(31) 487 488#define S_RDES0_FRAMELEN 16 489#define M_RDES0_FRAMELEN _DD_MAKEMASK(14,S_RDES0_FRAMELEN) 490#define V_RDES0_FRAMELEN(x) _DD_MAKEVALUE(x,S_RDES0_FRAMELEN) 491#define G_RDES0_FRAMELEN(x) _DD_GETVALUE(x,S_RDES0_FRAMELEN,M_RDES0_FRAMELEN) 492 493#define M_RDES0_ZERO _DD_MAKEMASK1(0) 494#define M_RDES0_OVFL _DD_MAKEMAKS1(0) /* 21041 only */ 495#define M_RDES0_CRCERR _DD_MAKEMASK1(1) 496#define M_RDES0_DRIBBLE _DD_MAKEMASK1(2) 497#define M_RDES0_MIIERROR _DD_MAKEMASK1(3) /* not 21041 */ 498#define M_RDES0_WDOGTIMER _DD_MAKEMASK1(4) 499#define M_RDES0_FRAMETYPE _DD_MAKEMASK1(5) 500#define M_RDES0_COLLSEEN _DD_MAKEMASK1(6) 501#define M_RDES0_FRAMETOOLONG _DD_MAKEMASK1(7) 502#define M_RDES0_LASTDES _DD_MAKEMASK1(8) 503#define M_RDES0_FIRSTDES _DD_MAKEMASK1(9) 504#define M_RDES0_MCASTFRAME _DD_MAKEMASK1(10) 505#define M_RDES0_RUNTFRAME _DD_MAKEMASK1(11) 506 507#define S_RDES0_DATATYPE 12 508#define M_RDES0_DATATYPE _DD_MAKEMASK(2,S_RDES0_DATATYPE) 509#define V_RDES0_DATATYPE(x) _DD_MAKEVALUE(x,S_RDES0_DATATYPE) 510#define G_RDES0_DATATYPE(x) _DD_GETVALUE(x,S_RDES0_DATATYPE,M_RDES0_DATATYPE) 511 512#define M_RDES0_ERROR _DD_MAKEMASK1(14) 513#define M_RDES0_ERRORSUM _DD_MAKEMASK1(15) 514#define M_RDES0_FILTFAIL _DD_MAKEMASK1(30) /* not 21041 */ 515 516#define S_RDES1_BUF1SIZE 0 517#define M_RDES1_BUF1SIZE _DD_MAKEMASK(11,S_TDES1_BUF1SIZE) 518#define V_RDES1_BUF1SIZE(x) _DD_MAKEVALUE(x,S_RDES1_BUF1SIZE) 519#define G_RDES1_BUF1SIZE(x) _DD_GETVALUE(x,S_RDES1_BUF1SIZE,M_RDES1_BUF1SIZE) 520 521#define S_RDES1_BUF2SIZE 11 522#define M_RDES1_BUF2SIZE _DD_MAKEMASK(11,S_TDES2_BUF2SIZE) 523#define V_RDES1_BUF2SIZE(x) _DD_MAKEVALUE(x,S_RDES1_BUF2SIZE) 524#define G_RDES1_BUF2SIZE(x) _DD_GETVALUE(x,S_RDES1_BUF2SIZE,M_RDES1_BUF2SIZE) 525 526#define M_RDES1_CHAINED _DD_MAKEMASK1(24) 527#define M_RDES1_ENDOFRING _DD_MAKEMASK1(25) 528 529#define M_RDES2_BUFADDR 0xFFFFFFFF 530#define M_RDES3_BUFADDR 0xFFFFFFFF 531 532/* ********************************************************************* 533 * Transmit Descriptors 534 ********************************************************************* */ 535 536#define M_TDES0_OWNSYS 0 537#define M_TDES0_OWNADAP _DD_MAKEMASK1(31) 538 539#define M_TDES0_DEFERRED _DD_MAKEMASK1(0) 540#define M_TDES0_UNDERFLOW _DD_MAKEMASK1(1) 541#define M_TDES0_LINK_FAIL _DD_MAKEMASK1(2) 542 543#define S_TDES0_COLLCOUNT 3 544#define M_TDES0_COLLCOUNT _DD_MAKEMASK(4,S_TDES0_COLLCOUNT) 545#define V_TDES0_COLLCOUNT(x) _DD_MAKEVALUE(x,S_TDES0_COLLCOUNT) 546#define G_TDES0_COLLCOUNT(x) _DD_GETVALUE(x,S_TDES0_COLLCOUNT,M_TDES0_COLLCOUNT) 547 548#define M_TDES0_HEARTBEAT_FAIL _DD_MAKEMASK1(7) 549#define M_TDES0_EXCESSIVE_COLLISIONS _DD_MAKEMASK1(8) 550#define M_TDES0_LATE_COLLISION _DD_MAKEMASK1(9) 551#define M_TDES0_NO_CARRIER _DD_MAKEMASK1(10) 552#define M_TDES0_LOSS_OF_CARRIER _DD_MAKEMASK1(11) 553#define M_TDES0_TX_JABBER_TIMEOUT _DD_MAKEMASK1(14) 554#define M_TDES0_ERROR_SUMMARY _DD_MAKEMASK1(15) 555#define M_TDES0_OWN_BIT _DD_MAKEMASK1(31) 556 557#define S_TDES1_BUF1SIZE 0 558#define M_TDES1_BUF1SIZE _DD_MAKEMASK(11,S_TDES1_BUF1SIZE) 559#define V_TDES1_BUF1SIZE(x) _DD_MAKEVALUE(x,S_TDES1_BUF1SIZE) 560#define G_TDES1_BUF1SIZE(x) _DD_GETVALUE(x,S_TDES1_BUF1SIZE,M_TDES1_BUF1SIZE) 561 562#define S_TDES1_BUF2SIZE 11 563#define M_TDES1_BUF2SIZE _DD_MAKEMASK(11,S_TDES2_BUF2SIZE) 564#define V_TDES1_BUF2SIZE(x) _DD_MAKEVALUE(x,S_TDES1_BUF2SIZE) 565#define G_TDES1_BUF2SIZE(x) _DD_GETVALUE(x,S_TDES1_BUF2SIZE,M_TDES1_BUF2SIZE) 566 567#define M_TDES1_FT0 _DD_MAKEMASK1(22) 568#define M_TDES1_NOPADDING _DD_MAKEMASK1(23) 569#define M_TDES1_CHAINED _DD_MAKEMASK1(24) 570#define M_TDES1_ENDOFRING _DD_MAKEMASK1(25) 571#define M_TDES1_NOADDCRC _DD_MAKEMASK1(26) 572#define M_TDES1_SETUP _DD_MAKEMASK1(27) 573#define M_TDES1_FT1 _DD_MAKEMASK1(28) 574#define M_TDES1_FIRSTSEG _DD_MAKEMASK1(29) 575#define M_TDES1_LASTSEG _DD_MAKEMASK1(30) 576#define M_TDES1_INTERRUPT _DD_MAKEMASK1(31) 577 578#define M_TDES2_BUFADDR 0xFFFFFFFF 579#define M_TDES3_BUFADDR 0xFFFFFFFF 580 581 582/* CAM */ 583 584#define CAM_HASH_THRESHOLD 14 585#define CAM_PERFECT_ENTRIES 16 586 587#define CAM_SETUP_BUFFER_SIZE 192 588 589#endif /* _DC21143_H_ */ 590