1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * BCM570X (10/100/1K EthernetMAC) registers File: bcm5700.c 5 * 6 ********************************************************************* 7 * 8 * Copyright 2000,2001,2002,2003 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and 13 * conditions. Subject to these conditions, you may download, 14 * copy, install, use, modify and distribute modified or unmodified 15 * copies of this software in source and/or binary form. No title 16 * or ownership is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions 20 * as they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products derived 25 * from this software without the prior written permission of 26 * Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 40 * THE POSSIBILITY OF SUCH DAMAGE. 41 ********************************************************************* */ 42 43#ifndef _BCM5700_H_ 44#define _BCM5700_H_ 45 46/* 47 * Register and bit definitions for the Broadcom BCM570X family (aka 48 * Tigon3) of Integrated MACs. 49 * 50 * The 5700 option for external SSRAM is ignored, since no subsequent 51 * chips support it, nor do the 5700 evaluation boards. 52 * 53 * References: 54 * 55 * Host Programmer Interface Specification for the BCM570X Family 56 * of Highly-Integrated Media Access Controllers, 570X-PG106-R. 57 * Broadcom Corp., 16215 Alton Parkway, Irvine CA, 09/27/02 58 * 59 * Simplified Programmer Interface Specification for the BCM570X Family 60 * of Highly Integrated Media Access Controllers, 570X-PG202-R. 61 * Broadcom Corp., 16215 Alton Parkway, Irvine CA, 10/14/02 62 */ 63 64#define K_PCI_VENDOR_BROADCOM 0x14e4 65#define K_PCI_ID_BCM5700 0x1644 66#define K_PCI_ID_BCM5701 0x1645 67#define K_PCI_ID_BCM5702 0x16A6 68#define K_PCI_ID_BCM5703 0x1647 69#define K_PCI_ID_BCM5703a 0x16A7 70#define K_PCI_ID_BCM5703b 0x16C7 71#define K_PCI_ID_BCM5704C 0x1648 72#define K_PCI_ID_BCM5704S 0x16A8 73#define K_PCI_ID_BCM5705 0x1653 74#define K_PCI_ID_BCM5780 0x1668 75 76#define _DD_MAKEMASK1(n) (1 << (n)) 77#define _DD_MAKEMASK(v,n) ((((1)<<(v))-1) << (n)) 78#define _DD_MAKEVALUE(v,n) ((v) << (n)) 79#define _DD_GETVALUE(v,n,m) (((v) & (m)) >> (n)) 80 81 82/* Registers 0x0000 - 0x00FF are PCI Configuration registers (shadow) */ 83 84#define PCI_PCIX_CMD_REG 0x40 85#define PCI_PCIX_STAT_REG 0x44 86 87#define PCI_PMC_REG 0x48 88#define PCI_PMCSR_REG 0x4C 89 90#define PCI_VPD_CAP_REG 0x50 91#define PCI_VPD_DATA_REG 0x54 92 93#define PCI_MSI_CTL_REG 0x58 94#define PCI_MSI_ADDR_REG 0x5C /* 8 bytes */ 95#define PCI_MSI_DATA_REG 0x64 96 97#define R_MISC_HOST_CTRL 0x0068 98#define R_DMA_RW_CTRL 0x006C 99#define R_PCI_STATE 0x0070 100#define R_PCI_CLK_CTRL 0x0074 101#define R_REG_BASE_ADDR 0x0078 102#define R_MEMWIN_BASE_ADDR 0x007C 103#define R_REG_DATA 0x0080 104#define R_MEMWIN_DATA 0x0084 105/* For 5700 and 5701, 0x0088-0x0090 shadow 0x6800-0x6808 */ 106#define R_INT_MBOX0 0x00B0 /* 8 bytes, shadows R_INT_MBOX(0) */ 107 108/* Registers 0x0200 - 0x03FF are High Priority Mailbox registers */ 109 110#define R_INT_MBOX(n) (0x0200 + 8*(n)) /* 0 <= n < 4 */ 111#define R_GEN_MBOX(n) (0x0220 + 8*(n)-8) /* 1 <= n <= 8 */ 112#define R_RELOAD_STATS_MBOX 0x0260 113#define R_RCV_BD_STD_PI 0x0268 114#define R_RCV_BD_JUMBO_PI 0x0270 115#define R_RCV_BD_MINI_PI 0x0278 116#define R_RCV_BD_RTN_CI(n) (0x0280 + 8*(n)-8) /* 1 <= n <= 16 */ 117#define R_SND_BD_PI(n) (0x0300 + 8*(n)-8) /* 1 <= n <= 16 */ 118#define R_SND_BD_NIC_PI(n) (0x0380 + 8*(n)-8) /* 1 <= n <= 16 */ 119 120/* Registers 0x0400 - 0x0BFF are MAC Control registers */ 121 122#define R_MAC_MODE 0x0400 123#define R_MAC_STATUS 0x0404 124#define R_MAC_EVENT_ENB 0x0408 125#define R_MAC_LED_CTRL 0x040C 126 127#define R_MAC_ADDR1_HIGH 0x0410 128#define R_MAC_ADDR1_LOW 0x0414 129#define R_MAC_ADDR2_HIGH 0x0418 130#define R_MAC_ADDR2_LOW 0x041C 131#define R_MAC_ADDR3_HIGH 0x0420 132#define R_MAC_ADDR3_LOW 0x0424 133#define R_MAC_ADDR4_HIGH 0x0428 134#define R_MAC_ADDR4_LOW 0x042C 135 136#define R_WOL_PATTERN_PTR 0x0430 137#define R_WOL_PATTERN_CFG 0x0434 138#define R_TX_BACKOFF 0x0438 139#define R_RX_MTU 0x043C 140#define R_PCS_TEST 0x0440 141#define R_TX_AUTONEG 0x0444 142#define R_RX_AUTONEG 0x0448 143 144#define R_MI_COMM 0x044C 145#define R_MI_STATUS 0x0450 146#define R_MI_MODE 0x0454 147 148#define R_AUTOPOLL_STAT 0x0458 149#define R_TX_MODE 0x045C 150#define R_TX_STAT 0x0460 151#define R_TX_LENS 0x0464 152#define R_RX_MODE 0x0468 153#define R_RX_STAT 0x046C 154 155#define R_MAC_HASH(n) (0x0470 + 4*(n)) /* 0 <= n < 4 */ 156 157#define R_RX_BD_RULES_CTRL(n) (0x0480 + 8*(n)) /* 0 <= n < 16 */ 158#define R_RX_BD_RULES_MASK(n) (0x0484 + 8*(n)) 159 160#define R_RX_RULES_CFG 0x0500 161#define R_RX_FRAMES_LOW 0x0504 162#define R_MAC_HASH_EXT(n) (0x0520 + 4*(n)) /* 0 <= n < 4 */ 163#define R_MAC_ADDR_EXT(n) (0x0530 + 8*(n)) /* 0 <= n < 12 */ 164#define R_SERDES_CTRL 0x0590 165#define R_SERDES_STAT 0x0594 166#define R_RX_STATS_MEM 0x0800 167#define R_TX_STATS_MEM 0x0880 168 169 170/* 171 * Note on Buffer Descriptor (BD) Ring indices: 172 * Numbering follows Broadcom literature, which uses indices 1-16. 173 * PI = producer index, CI = consumer index. 174 */ 175 176/* Registers 0x0C00 - 0x0FFF are Send Data Initiator Control registers */ 177 178#define R_SND_DATA_MODE 0x0C00 179#define R_SND_DATA_STAT 0x0C04 180#define R_SND_DATA_STATS_CTRL 0x0C08 181#define R_SND_DATA_STATS_ENB 0x0C0C 182#define R_SND_DATA_STATS_INCR 0x0C10 183 184#define R_STATS_CTR_SND_COS(n) (0x0C80 + 4*(n)-4) /* 1 <= n <= 16 */ 185#define R_STATS_DMA_RDQ_FULL 0x0CC0 186#define R_STATS_DMA_HP_RDQ_FULL 0x0CC4 187#define R_STATS_SDCQ_FULL 0x0CC8 188#define R_STATS_NIC_SET_SND_PI 0x0CCC 189#define R_STATS_STAT_UPDATED 0x0CD0 190#define R_STATS_IRQS 0x0CD4 191#define R_STATS_IRQS_AVOIDED 0x0CD8 192#define R_STATS_SND_THRSH_HIT 0x0CDC 193 194/* Registers 0x1000 - 0x13FF are Send Data Completion Control registers */ 195 196#define R_SND_DATA_COMP_MODE 0x1000 197 198/* Registers 0x1400 - 0x17FF are Send BD Ring Selection Control registers */ 199 200#define R_SND_BD_SEL_MODE 0x1400 201#define R_SND_BD_SEL_STAT 0x1404 202#define R_SND_BD_DIAG 0x1408 203#define R_SND_BD_SEL_CI(n) (0x1440 + 4*(n)-4) /* 1 <= n <= 16 */ 204 205/* Registers 0x1800 - 0x1BFF are Send BD Initiator Control registers */ 206 207#define R_SND_BD_INIT_MODE 0x1800 208#define R_SND_BD_INIT_STAT 0x1804 209#define R_SND_BD_INIT_PI(n) (0x1808 + 4*(n)-4) /* 1 <= n <= 16 */ 210 211/* Registers 0x1C00 - 0x1FFF are Send BD Completion Control registers */ 212 213#define R_SND_BD_COMP_MODE 0x1C00 214 215/* Registers 0x2000 - 0x23FF are Receive List Placement Control registers */ 216 217#define R_RCV_LIST_MODE 0x2000 218#define R_RCV_LIST_STAT 0x2004 219#define R_RCV_LIST_LOCK 0x2008 220#define R_RCV_NONEMPTY_BITS 0x200C 221#define R_RCV_LIST_CFG 0x2010 222#define R_RCV_LIST_STATS_CTRL 0x2014 223#define R_RCV_LIST_STATS_ENB 0x2018 224#define R_RCV_LIST_STATS_INC 0x201C 225#define R_RCV_LIST_HEAD(n) (0x2100 + 16*(n)-16) /* 1 <= n <= 16 */ 226#define R_RCV_LIST_TAIL(n) (0x2104 + 16*(n)-16) 227#define R_RCV_LIST_CNT(n) (0x2108 + 16*(n)-16) 228#define R_STATS_CTR_RCV_COS(n) (0x2200 + 4*(n)-4) /* 1 <= n <= 16 */ 229#define R_STATS_FILT_DROP 0x2240 230#define R_STATS_DMA_WRQ_FULL 0x2244 231#define R_STATS_DMA_HP_WRQ_FULL 0x2248 232#define R_STATS_NO_RCV_BDS 0x224C 233#define R_STATS_IN_DISCARDS 0x2250 234#define R_STATS_IN_ERRORS 0x2254 235#define R_STATS_RCV_THRSH_HIT 0x2258 236 237/* Registers 0x2400 - 0x27FF are Receive Data/BD Initiator Control registers */ 238 239#define R_RCV_DATA_INIT_MODE 0x2400 240#define R_RCV_DATA_INIT_STAT 0x2404 241#define R_JUMBO_RCV_BD_RCB 0x2440 /* 16 bytes */ 242#define R_STD_RCV_BD_RCB 0x2450 /* 16 bytes */ 243#define R_MINI_RCV_BD_RCB 0x2460 /* 16 bytes */ 244#define R_RCV_BD_INIT_JUMBO_CI 0x2470 245#define R_RCV_BD_INIT_STD_CI 0x2474 246#define R_RCV_BD_INIT_MINI_CI 0x2478 247#define R_RCV_BD_INIT_RTN_PI(n) (0x2480 + 4*(n)-4) /* 1 <= n <= 16 */ 248#define R_RCV_BD_INIT_DIAG 0x24C0 249 250/* Registers 0x2800 - 0x2BFF are Receive Data Completion Control registers */ 251 252#define R_RCV_COMP_MODE 0x2800 253 254/* Registers 0x2C00 - 0x2FFF are Receive BD Initiator Control registers */ 255 256#define R_RCV_BD_INIT_MODE 0x2C00 257#define R_RCV_BD_INIT_STAT 0x2C04 258#define R_RCV_BD_INIT_JUMBO_PI 0x2C08 259#define R_RCV_BD_INIT_STD_PI 0x2C0C 260#define R_RCV_BD_INIT_MINI_PI 0x2C10 261#define R_MINI_RCV_BD_THRESH 0x2C14 262#define R_STD_RCV_BD_THRESH 0x2C18 263#define R_JUMBO_RCV_BD_THRESH 0x2C1C 264 265/* Registers 0x3000 - 0x33FF are Receive BD Completion Control registers */ 266 267#define R_RCV_BD_COMP_MODE 0x3000 268#define R_RCV_BD_COMP_STAT 0x3004 269#define R_NIC_JUMBO_RCV_BD_PI 0x3008 270#define R_NIC_STD_RCV_BD_PI 0x300C 271#define R_NIC_MINI_RCV_BD_PI 0x3010 272 273/* Registers 0x3400 - 0x37FF are Receive List Selector Control registers */ 274 275#define R_RCV_LIST_SEL_MODE 0x3400 276#define R_RCV_LIST_SEL_STATUS 0x3404 277 278/* Registers 0x3800 - 0x3BFF are Mbuf Cluster Free registers */ 279 280#define R_MBUF_FREE_MODE 0x3800 281#define R_MBUF_FREE_STATUS 0x3804 282 283/* Registers 0x3C00 - 0x3FFF are Host Coalescing Control registers */ 284 285#define R_HOST_COAL_MODE 0x3C00 286#define R_HOST_COAL_STAT 0x3C04 287#define R_RCV_COAL_TICKS 0x3C08 288#define R_SND_COAL_TICKS 0x3C0C 289#define R_RCV_COAL_MAX_CNT 0x3C10 290#define R_SND_COAL_MAX_CNT 0x3C14 291#define R_RCV_COAL_INT_TICKS 0x3C18 292#define R_SND_COAL_INT_TICKS 0x3C1C 293#define R_RCV_COAL_INT_CNT 0x3C20 294#define R_SND_COAL_INT_CNT 0x3C24 295#define R_STATS_TICKS 0x3C28 296#define R_STATS_HOST_ADDR 0x3C30 /* 8 bytes */ 297#define R_STATUS_HOST_ADDR 0x3C38 /* 8 bytes */ 298#define R_STATS_BASE_ADDR 0x3C40 299#define R_STATUS_BASE_ADDR 0x3C44 300#define R_FLOW_ATTN 0x3C48 301#define R_NIC_JUMBO_RCV_BD_CI 0x3C50 302#define R_NIC_STD_RCV_BD_CI 0x3C54 303#define R_NIC_MINI_RCV_BD_CI 0x3C58 304#define R_NIC_RTN_PI(n) (0x3C80 + 4*(n)-4) /* 1 <= n <= 16 */ 305#define R_NIC_SND_BD_CD(n) (0x3CC0 + 4*(n)-4) /* 1 <= n <= 16 */ 306 307/* Registers 0x4000 - 0x43FF are Memory Arbiter registers */ 308 309#define R_MEM_MODE 0x4000 310#define R_MEM_STATUS 0x4004 311#define R_MEM_TRAP_LOW 0x4008 312#define R_MEM_TRAP_HIGH 0x400C 313 314 315/* Registers 0x4400 - 0x47FF are Buffer Manager Control registers */ 316 317#define R_BMGR_MODE 0x4400 318#define R_BMGR_STATUS 0x4404 319#define R_BMGR_MBUF_BASE 0x4408 320#define R_BMGR_MBUF_LEN 0x440C 321#define R_BMGR_MBUF_DMA_LOW 0x4410 322#define R_BMGR_MBUF_RX_LOW 0x4414 323#define R_BMGR_MBUF_HIGH 0x4418 324 325#define R_BMGR_DMA_BASE 0x442C 326#define R_BMGR_DMA_LEN 0x4430 327#define R_BMGR_DMA_LOW 0x4434 328#define R_BMGR_DMA_HIGH 0x4438 329 330#define R_BMGR_DIAG1 0x444C 331#define R_BMGR_DIAG2 0x4450 332#define R_BMGR_DIAG3 0x4454 333#define R_BMGR_RCV_FLOW_THRESH 0x4458 334 335/* Registers 0x4800 - 0x4BFF are Read DMA Control registers */ 336 337#define R_RD_DMA_MODE 0x4800 338#define R_RD_DMA_STAT 0x4804 339 340#define RD_DMA_MODE_FIFO_SIZE_128 _DD_MAKEMASK1(17) 341 342/* Registers 0x4C00 - 0x4FFF are Write DMA Control registers */ 343 344#define R_WR_DMA_MODE 0x4C00 345#define R_WR_DMA_STAT 0x4C04 346 347/* Registers 0x5000 - 0x53FF are RX RISC registers */ 348 349#define R_RX_RISC_MODE 0x5000 350#define R_RX_RISC_STATE 0x5004 351#define R_RX_RISC_PC 0x501C 352 353/* Registers 0x5400 - 0x57FF are TX RISC registers */ 354 355#define R_TX_RISC_MODE 0x5400 356#define R_TX_RISC_STATE 0x5404 357#define R_TX_RISC_PC 0x541C 358 359/* Registers 0x5800 - 0x5BFF are Low Priority Mailbox registers (8 bytes) */ 360 361#define R_LP_INT_MBOX(n) (0x5800 + 8*(n)) /* 0 <= n < 4 */ 362#define R_LP_GEN_MBOX(n) (0x5820 + 8*(n)-8) /* 1 <= n <= 8 */ 363#define R_LP_RELOAD_STATS_MBOX 0x5860 364#define R_LP_RCV_BD_STD_PI 0x5868 365#define R_LP_RCV_BD_JUMBO_PI 0x5870 366#define R_LP_RCV_BD_MINI_PI 0x5878 367#define R_LP_RCV_BD_RTN_CI(n) (0x5880 + 8*(n)-8) /* 1 <= n <= 16 */ 368#define R_LP_SND_BD_PI(n) (0x5900 + 8*(n)-8) /* 1 <= n <= 16 */ 369 370/* Registers 0x5C00 - 0x5C03 are Flow Through Queues */ 371 372#define R_FTQ_RESET 0x5C00 373 374/* Registers 0x6000 - 0x63FF are Message Signaled Interrupt registers */ 375 376#define R_MSI_MODE 0x6000 377#define R_MSI_STATUS 0x6004 378#define R_MSI_FIFO_ACCESS 0x6008 379 380/* Registers 0x6400 - 0x67FF are DMA Completion registers */ 381 382#define R_DMA_COMP_MODE 0x6400 383 384/* Registers 0x6800 - 0x68ff are General Control registers */ 385 386#define R_MODE_CTRL 0x6800 387#define R_MISC_CFG 0x6804 388#define R_MISC_LOCAL_CTRL 0x6808 389#define R_TIMER 0x680C 390#define R_MEM_PWRUP 0x6030 /* 8 bytes */ 391#define R_EEPROM_ADDR 0x6838 392#define R_EEPROM_DATA 0x683C 393#define R_EEPROM_CTRL 0x6840 394#define R_MDI_CTRL 0x6844 395#define R_EEPROM_DELAY 0x6848 396 397/* Registers 0x6C00 - 0x6CFF are ASF Support registers (NYI) */ 398 399/* Registers 0x7000 - 0x7024 are NVM Interface registers (NYI) */ 400 401 402/* PCI Capability registers (should be moved to PCI headers) */ 403 404/* PCI-X Capability and Command Register (0x40) */ 405 406#define PCIX_CMD_DPREC_ENABLE 0x00010000 407#define PCIX_CMD_RLXORDER_ENABLE 0x00020000 408#define PCIX_CMD_RD_CNT_SHIFT 18 409#define PCIX_CMD_RD_CNT_MASK 0x000C0000 410#define PCIX_CMD_MAX_SPLIT_SHIFT 20 411#define PCIX_CMD_MAX_SPLIT_MASK 0x00700000 412 413/* PCI-X Status Register (0x44) */ 414 415 416/* Generic bit fields shared by most MODE and STATUS registers */ 417 418#define M_MODE_RESET _DD_MAKEMASK1(0) 419#define M_MODE_ENABLE _DD_MAKEMASK1(1) 420#define M_MODE_ATTNENABLE _DD_MAKEMASK1(2) 421 422#define M_STAT_ERROR _DD_MAKEMASK1(1) 423 424/* Generic bit fields shared by STATS_CTRL registers */ 425 426#define M_STATS_ENABLE _DD_MAKEMASK1(0) 427#define M_STATS_FASTUPDATE _DD_MAKEMASK1(1) 428#define M_STATS_CLEAR _DD_MAKEMASK1(2) 429#define M_STATS_FLUSH _DD_MAKEMASK1(3) 430#define M_STATS_ZERO _DD_MAKEMASK1(4) 431 432/* Private PCI Configuration registers (p 335) */ 433 434/* MHC: Miscellaneous Host Control Register (0x68) */ 435 436#define M_MHC_CLEARINTA _DD_MAKEMASK1(0) 437#define M_MHC_MASKPCIINT _DD_MAKEMASK1(1) 438#define M_MHC_ENBYTESWAP _DD_MAKEMASK1(2) 439#define M_MHC_ENWORDSWAP _DD_MAKEMASK1(3) 440#define M_MHC_ENPCISTATERW _DD_MAKEMASK1(4) 441#define M_MHC_ENCLKCTRLRW _DD_MAKEMASK1(5) 442#define M_MHC_ENREGWORDSWAP _DD_MAKEMASK1(6) 443#define M_MHC_ENINDIRECT _DD_MAKEMASK1(7) 444#define S_MHC_ASICREV 16 445#define M_MHC_ASICREV _DD_MAKEMASK(16,S_MHC_ASICREV) 446#define G_MHC_ASICREV(x) _DD_GETVALUE(x,S_MHC_ASICREV,M_MHC_ASICREV) 447 448/* DMAC: DMA Read/Write Control Register (0x6c) */ 449 450#define S_DMAC_MINDMA 0 451#define M_DMAC_MINDMA _DD_MAKEMASK(8,S_DMAC_MINDMA) 452#define V_DMAC_MINDMA(x) _DD_MAKEVALUE(x,S_DMAC_MINDMA) 453#define G_DMAC_MINDMA(x) _DD_GETVALUE(x,S_DMAC_MINDMA,M_DMAC_MINDMA) 454 455#define S_DMAC_RDBDY 8 /* 570{0,1} only */ 456#define M_DMAC_RDBDY _DD_MAKEMASK(3,S_DMAC_RDBDY) 457#define V_DMAC_RDBDY(x) _DD_MAKEVALUE(x,S_DMAC_RDBDY) 458#define G_DMAC_RDBDY(x) _DD_GETVALUE(x,S_DMAC_RDBDY,M_DMAC_RDBDY) 459 460#define S_DMAC_WRBDY 11 /* 570{0,1} only */ 461#define M_DMAC_WRBDY _DD_MAKEMASK(3,S_DMAC_WRBDY) 462#define V_DMAC_WRBDY(x) _DD_MAKEVALUE(x,S_DMAC_WRBDY) 463#define G_DMAC_WRBDY(x) _DD_GETVALUE(x,S_DMAC_WRBDY,M_DMAC_WRBDY) 464 465#define S_DMAC_ONEDMA 14 466#define M_DMAC_ONEDMA _DD_MAKEMASK(2,S_DMAC_ONEDMA) 467#define V_DMAC_ONEDMA(x) _DD_MAKEVALUE(x,S_DMAC_ONEDMA) 468#define G_DMAC_ONEDMA(x) _DD_GETVALUE(x,S_DMAC_ONEDMA,M_DMAC_WRBDY) 469 470#define S_DMAC_RDWMK 16 471#define M_DMAC_RDWMK _DD_MAKEMASK(3,S_DMAC_RDWMK) 472#define V_DMAC_RDWMK(x) _DD_MAKEVALUE(x,S_DMAC_RDWMK) 473#define G_DMAC_RDWMK(x) _DD_GETVALUE(x,S_DMAC_RDWMK,M_DMAC_RDWMK) 474 475#define S_DMAC_WRWMK 19 476#define M_DMAC_WRWMK _DD_MAKEMASK(3,S_DMAC_WRWMK) 477#define V_DMAC_WRWMK(x) _DD_MAKEVALUE(x,S_DMAC_WRWMK) 478#define G_DMAC_WRWMK(x) _DD_GETVALUE(x,S_DMAC_WRWMK,M_DMAC_WRWMK) 479 480#define M_DMAC_MEMRDMULT _DD_MAKEMASK1(22) /* 570{0,1} only */ 481#define M_DMAC_BEALL _DD_MAKEMASK1(23) /* 570{0,1} only */ 482#define M_DMAC_ENBUGFIX _DD_MAKEMASK1(23) /* 570{3,4} only */ 483 484#define S_DMAC_RDCMD 24 /* 570{0,1} only */ 485#define M_DMAC_RDCMD _DD_MAKEMASK(4,S_DMAC_RDCMD) 486#define V_DMAC_RDCMD(x) _DD_MAKEVALUE(x,S_DMAC_RDCMD) 487#define G_DMAC_RDCMD(x) _DD_GETVALUE(x,S_DMAC_RDCMD,M_DMAC_RDCMD) 488#define K_PCI_MEMRD 0x6 489 490#define S_DMAC_WRCMD 28 491#define M_DMAC_WRCMD _DD_MAKEMASK(4,S_DMAC_WRCMD) 492#define V_DMAC_WRCMD(x) _DD_MAKEVALUE(x,S_DMAC_WRCMD) 493#define G_DMAC_WRCMD(x) _DD_GETVALUE(x,S_DMAC_WRCMD,M_DMAC_WRCMD) 494#define K_PCI_MEMWR 0x7 495 496/* PCIS: PCI State Register (0x70) */ 497 498#define M_PCIS_RESET _DD_MAKEMASK1(0) 499#define M_PCIS_INT _DD_MAKEMASK1(1) 500#define M_PCIS_MODE _DD_MAKEMASK1(2) 501#define M_PCIS_33MHZ _DD_MAKEMASK1(3) 502#define M_PCIS_32BIT _DD_MAKEMASK1(4) 503#define M_PCIS_ROMEN _DD_MAKEMASK1(5) 504#define M_PCIS_ROMRETRY _DD_MAKEMASK1(6) 505#define M_PCIS_FLATVIEW _DD_MAKEMASK1(8) 506 507#define S_PCIS_MAXRETRY 9 /* 570{0,1} only */ 508#define M_PCIS_MAXRETRY _DD_MAKEMASK(3,S_PCIS_MAXRETRY) 509#define V_PCIS_MAXRETRY(x) _DD_MAKEVALUE(x,S_PCIS_MAXRETRY) 510#define G_PCIS_MAXRETRY(x) _DD_GETVALUE(x,S_PCIS_MAXRETRY,M_PCIS_MAXRETRY) 511 512#define M_PCIS_RETRYSAME _DD_MAKEMASK1(13) /* not 570{0,1} */ 513#define M_PCIS_CARDBUSMODE _DD_MAKEMASK1(14) /* 5705 only */ 514#define M_PCIS_FORCERETRY _DD_MAKEMASK1(15) /* 5705 only */ 515 516/* PCI Clock Control Register (0x74) */ 517 518/* Register Base Address Register (0x78) */ 519 520/* Memory Window Base Address Register (0x7c) */ 521 522 523/* High Priority Mailboxes (p 323) */ 524 525 526/* Ethernet MAC Control registers (p 358) */ 527 528/* MACM: Ethernet MAC Mode Register (0x400) */ 529 530#define M_MACM_GLBRESET _DD_MAKEMASK1(0) 531#define M_MACM_HALFDUPLEX _DD_MAKEMASK1(1) 532 533#define S_MACM_PORTMODE 2 534#define M_MACM_PORTMODE _DD_MAKEMASK(2,S_MACM_PORTMODE) 535#define V_MACM_PORTMODE(x) _DD_MAKEVALUE(x,S_MACM_PORTMODE) 536#define G_MACM_PORTMODE(x) _DD_GETVALUE(x,S_MACM_PORTMODE,M_MACM_PORTMODE) 537#define K_MACM_PORTMODE_NONE 0x0 538#define K_MACM_PORTMODE_MII 0x1 539#define K_MACM_PORTMODE_GMII 0x2 540#define K_MACM_PORTMODE_TBI 0x3 541 542#define M_MACM_LOOPBACK _DD_MAKEMASK1(4) 543#define M_MACM_TAGGEDMAC _DD_MAKEMASK1(7) 544#define M_MACM_TXBURST _DD_MAKEMASK1(8) 545#define M_MACM_MAXDEFER _DD_MAKEMASK1(9) 546#define M_MACM_LINKPOLARITY _DD_MAKEMASK1(10) 547#define M_MACM_RXSTATSENB _DD_MAKEMASK1(11) 548#define M_MACM_RXSTATSCLR _DD_MAKEMASK1(12) 549#define M_MACM_RXSTATSFLUSH _DD_MAKEMASK1(13) 550#define M_MACM_TXSTATSENB _DD_MAKEMASK1(14) 551#define M_MACM_TXSTATSCLR _DD_MAKEMASK1(15) 552#define M_MACM_TXSTATSFLUSH _DD_MAKEMASK1(16) 553#define M_MACM_SENDCFGS _DD_MAKEMASK1(17) 554#define M_MACM_MAGICPKT _DD_MAKEMASK1(18) 555#define M_MACM_ACPI _DD_MAKEMASK1(19) 556#define M_MACM_MIPENB _DD_MAKEMASK1(20) 557#define M_MACM_TDEENB _DD_MAKEMASK1(21) 558#define M_MACM_RDEENB _DD_MAKEMASK1(22) 559#define M_MACM_FHDEENB _DD_MAKEMASK1(23) 560 561/* MACSTAT: Ethernet MAC Status Register (0x404) */ 562/* MACEVNT: Ethernet MAC Event Enable Register (0x408) */ 563 564/* Status Register only */ 565#define M_MACSTAT_PCSSYNC _DD_MAKEMASK1(0) 566#define M_MACSTAT_SIGDET _DD_MAKEMASK1(1) 567#define M_MACSTAT_RCVCFG _DD_MAKEMASK1(2) 568#define M_MACSTAT_CFGCHNG _DD_MAKEMASK1(3) 569#define M_MACSTAT_SYNCCHNG _DD_MAKEMASK1(4) 570/* Status and Enable Registers */ 571#define M_EVT_PORTERR _DD_MAKEMASK1(10) 572#define M_EVT_LINKCHNG _DD_MAKEMASK1(12) 573#define M_EVT_MICOMPLETE _DD_MAKEMASK1(22) 574#define M_EVT_MIINT _DD_MAKEMASK1(23) 575#define M_EVT_APERR _DD_MAKEMASK1(24) 576#define M_EVT_ODIERR _DD_MAKEMASK1(25) 577#define M_EVT_RXSTATOVRUN _DD_MAKEMASK1(26) 578#define M_EVT_TXSTATOVRUN _DD_MAKEMASK1(27) 579 580/* MICOMM: MI Communication Register (0x44c) */ 581 582#define S_MICOMM_DATA 0 583#define M_MICOMM_DATA _DD_MAKEMASK(16,S_MICOMM_DATA) 584#define V_MICOMM_DATA(x) _DD_MAKEVALUE(x,S_MICOMM_DATA) 585#define G_MICOMM_DATA(x) _DD_GETVALUE(x,S_MICOMM_DATA,M_MICOMM_DATA) 586 587#define S_MICOMM_REG 16 588#define M_MICOMM_REG _DD_MAKEMASK(5,S_MICOMM_REG) 589#define V_MICOMM_REG(x) _DD_MAKEVALUE(x,S_MICOMM_REG) 590#define G_MICOMM_REG(x) _DD_GETVALUE(x,S_MICOMM_REG,M_MICOMM_REG) 591 592#define S_MICOMM_PHY 21 593#define M_MICOMM_PHY _DD_MAKEMASK(5,S_MICOMM_PHY) 594#define V_MICOMM_PHY(x) _DD_MAKEVALUE(x,S_MICOMM_PHY) 595#define G_MICOMM_PHY(x) _DD_GETVALUE(x,S_MICOMM_PHY,M_MICOMM_PHY) 596 597#define S_MICOMM_CMD 26 598#define M_MICOMM_CMD _DD_MAKEMASK(2,S_MICOMM_CMD) 599#define V_MICOMM_CMD(x) _DD_MAKEVALUE(x,S_MICOMM_CMD) 600#define G_MICOMM_CMD(x) _DD_GETVALUE(x,S_MICOMM_CMD,M_MICOMM_CMD) 601#define K_MICOMM_CMD_WR 0x1 602#define K_MICOMM_CMD_RD 0x2 603#define V_MICOMM_CMD_WR V_MICOMM_CMD(K_MICOMM_CMD_WR) 604#define V_MICOMM_CMD_RD V_MICOMM_CMD(K_MICOMM_CMD_RD) 605 606#define M_MICOMM_RDFAIL _DD_MAKEMASK1(28) 607#define M_MICOMM_BUSY _DD_MAKEMASK1(29) 608 609/* MISTAT: MI Status Register (0x450) */ 610 611#define M_MISTAT_LINKED _DD_MAKEMASK1(0) 612#define M_MISTAT_10MBPS _DD_MAKEMASK1(1) 613 614/* MIMODE: MI Mode Register (0x454) */ 615 616#define M_MIMODE_SHORTPREAMBLE _DD_MAKEMASK1(1) 617#define M_MIMODE_POLLING _DD_MAKEMASK1(4) 618 619#define S_MIMODE_CLKCNT 16 620#define M_MIMODE_CLKCNT _DD_MAKEMASK(5,S_MIMODE_CLKCNT) 621#define V_MIMODE_CLKCNT(x) _DD_MAKEVALUE(x,S_MIMODE_CLKCNT) 622#define G_MIMODE_CLKCNT(x) _DD_GETVALUE(x,S_MIMODE_CLKCNT,M_MIMODE_CLKCNT) 623 624/* TXLEN: Transmit MAC Lengths Register (0x464) */ 625 626#define S_TXLEN_SLOT 0 627#define M_TXLEN_SLOT _DD_MAKEMASK(8,S_TXLEN_SLOT) 628#define V_TXLEN_SLOT(x) _DD_MAKEVALUE(x,S_TXLEN_SLOT) 629#define G_TXLEN_SLOT(x) _DD_GETVALUE(x,S_TXLEN_SLOT,M_TXLEN_SLOT) 630 631#define S_TXLEN_IPG 8 632#define M_TXLEN_IPG _DD_MAKEMASK(4,S_TXLEN_IPG) 633#define V_TXLEN_IPG(x) _DD_MAKEVALUE(x,S_TXLEN_IPG) 634#define G_TXLEN_IPG(x) _DD_GETVALUE(x,S_TXLEN_IPG,M_TXLEN_IPG) 635 636#define S_TXLEN_IPGCRS 12 637#define M_TXLEN_IPGCRS _DD_MAKEMASK(2,S_TXLEN_IPGCRS) 638#define V_TXLEN_IPGCRS(x) _DD_MAKEVALUE(x,S_TXLEN_IPGCRS) 639#define G_TXLEN_IPGCRS(x) _DD_GETVALUE(x,S_TXLEN_IPGCRS,M_TXLEN_IPGCRS) 640 641/* RULESCFG: Receive Rules Configuration Register (0x500) */ 642 643#define S_RULESCFG_DEFAULT 3 644#define M_RULESCFG_DEFAULT _DD_MAKEMASK(5,S_RULESCFG_DEFAULT) 645#define V_RULESCFG_DEFAULT(x) _DD_MAKEVALUE(x,S_RULESCFG_DEFAULT) 646#define G_RULESCFG_DEFAULT(x) _DD_GETVALUE(x,S_RULESCFG_DEFAULT,M_RULESCFG_DEFAULT) 647 648 649/* Send Data Initiator Control Registers (p 383) */ 650/* Send BD Ring Selector Control Registers (p 387) */ 651/* Send BD Initiator Control Registers (p 389) */ 652 653 654/* Receive List Placement Control Registers (p 392) */ 655 656/* LISTCFG: Receive List Placement Configuration Register (0x2010) */ 657 658#define S_LISTCFG_GROUP 0 659#define M_LISTCFG_GROUP _DD_MAKEMASK(3,S_LISTCFG_GROUP) 660#define V_LISTCFG_GROUP(x) _DD_MAKEVALUE(x,S_LISTCFG_GROUP) 661#define G_LISTCFG_GROUP(x) _DD_GETVALUE(x,S_LISTCFG_GROUP,M_LISTCFG_GROUP) 662 663#define S_LISTCFG_ACTIVE 3 664#define M_LISTCFG_ACTIVE _DD_MAKEMASK(5,S_LISTCFG_ACTIVE) 665#define V_LISTCFG_ACTIVE(x) _DD_MAKEVALUE(x,S_LISTCFG_ACTIVE) 666#define G_LISTCFG_ACTIVE(x) _DD_GETVALUE(x,S_LISTCFG_ACTIVE,M_LISTCFG_ACTIVE) 667 668#define S_LISTCFG_BAD 8 669#define M_LISTCFG_BAD _DD_MAKEMASK(5,S_LISTCFG_BAD) 670#define V_LISTCFG_BAD(x) _DD_MAKEVALUE(x,S_LISTCFG_BAD) 671#define G_LISTCFG_BAD(x) _DD_GETVALUE(x,S_LISTCFG_BAD,M_LISTCFG_BAD) 672 673#define S_LISTCFG_DEFAULT 13 674#define M_LISTCFG_DEFAULT _DD_MAKEMASK(2,S_LISTCFG_DEFAULT) 675#define V_LISTCFG_DEFAULT(x) _DD_MAKEVALUE(x,S_LISTCFG_DEFAULT) 676#define G_LISTCFG_DEFAULT(x) _DD_GETVALUE(x,S_LISTCFG_DEFAULT,M_LISTCFG_DEFAULT) 677 678 679/* Receive Data and Receive BD Initiator Control Registers (p 399) */ 680 681/* RCVINITMODE: Receive Data and Receive BD Initiator Mode Register (0x2400) */ 682 683#define M_RCVINITMODE_JUMBO _DD_MAKEMASK1(2) 684#define M_RCVINITMODE_FRMSIZE _DD_MAKEMASK1(3) 685#define M_RCVINITMODE_RTNSIZE _DD_MAKEMASK1(4) 686 687 688/* Receive Initiator Control Registers (p 404) */ 689/* Receive BD Completion Control Registers (p 406) */ 690/* Receive List Selector Control Registers (p 408) */ 691/* Mbuf Cluster Free Registers (p 409) */ 692 693 694/* Host Coalescing Control registers (p 410) */ 695 696/* HCM: Host Coalescing Mode Register (0x3C00) */ 697 698#define M_HCM_RESET _DD_MAKEMASK1(0) 699#define M_HCM_ENABLE _DD_MAKEMASK1(1) 700#define M_HCM_ATTN _DD_MAKEMASK1(2) 701#define M_HCM_COAL_NOW _DD_MAKEMASK1(3) 702 703#define S_HCM_MSIBITS 4 704#define M_HCM_MSIBITS _DD_MAKEMASK(3,S_HCM_MSIBITS) 705#define V_HCM_MSIBITS(x) _DD_MAKEVALUE(x,S_HCM_MSIBITS) 706#define G_HCM_MSIBITS _DD_GETVALUE(x,S_HCM_MSIBITS,M_HCM_MSIBITS) 707 708#define S_HCM_SBSIZE 7 709#define M_HCM_SBSIZE _DD_MAKEMASK(2,S_HCM_SBSIZE) 710#define V_HCM_SBSIZE(x) _DD_MAKEVALUE(x,S_HCM_SBSIZE) 711#define G_HCM_SBSIZE _DD_GETVALUE(x,S_HCM_SBSIZE,M_HCM_SBSIZE) 712#define K_HCM_SBSIZE_80 0x0 713#define K_HCM_SBSIZE_64 0x1 714#define K_HCM_SBSIZE_32 0x2 715/* ... more ... */ 716 717 718/* Memory Arbiter Registers (p 420) */ 719 720/* MAM: Memory Arbiter Mode Register (0x4000) */ 721 722#define M_MAM_RESET _DD_MAKEMASK1(0) 723#define M_MAM_ENABLE _DD_MAKEMASK1(1) 724 725/* Memory Arbiter Status Register (0x4004) */ 726 727/* Memory Arbiter Trap Low and Trap High Registers (0x4008, 0x400C) */ 728 729 730/* Buffer Manager Control Registers (p 424) */ 731 732/* BMODE: Buffer Manager Control Register (0x4400) */ 733 734#define M_BMODE_RESET _DD_MAKEMASK1(0) 735#define M_BMODE_ENABLE _DD_MAKEMASK1(1) 736#define M_BMODE_ATTN _DD_MAKEMASK1(2) 737#define M_BMODE_TEST _DD_MAKEMASK1(3) 738#define M_BMODE_MBUFLOWATTN _DD_MAKEMASK1(4) 739 740 741/* Read DMA Control Registers (p 428) */ 742/* Write DMA Control Registers (p 431) */ 743 744/* Bit fields shared by DMA_MODE and DMA_STATUS registers */ 745 746#define M_ATTN_TGTABORT _DD_MAKEMASK1(2) 747#define M_ATTN_MSTRABORT _DD_MAKEMASK1(3) 748#define M_ATTN_PERR _DD_MAKEMASK1(4) 749#define M_ATTN_ADDROVFL _DD_MAKEMASK1(5) 750#define M_ATTN_FIFOOVFL _DD_MAKEMASK1(6) 751#define M_ATTN_FIFOUNFL _DD_MAKEMASK1(7) 752#define M_ATTN_FIFOREAD _DD_MAKEMASK1(8) 753#define M_ATTN_LENERR _DD_MAKEMASK1(9) 754#define M_ATTN_ALL (M_ATTN_TGTABORT | M_ATTN_MSTRABORT | \ 755 M_ATTN_PERR | M_ATTN_ADDROVFL | \ 756 M_ATTN_FIFOOVFL | M_ATTN_FIFOUNFL | \ 757 M_ATTN_FIFOREAD | M_ATTN_LENERR) 758 759/* Read DMA Mode Register (0x4800) */ 760/* Write DMA Mode Register (0x4C00) */ 761 762/* Read DMA Status Register (0x4804) */ 763/* Write DMA Status Register (0x4C04) */ 764 765 766/* RX RISC Registers (p 433) */ 767/* TX RISC Registers (p 437) */ 768/* Low Priority Mailboxes (p 441) */ 769/* Flow Through Queues (p 445) */ 770 771 772/* Message Signaled Interrupt Registers (p 447) */ 773 774/* MSIMODE: MSI Mode Register (0x6000) */ 775 776#define M_MSIMODE_RESET _DD_MAKEMASK1(0) 777#define M_MSIMODE_ENABLE _DD_MAKEMASK1(1) 778#define M_MSIMODE_TGTABORT _DD_MAKEMASK1(2) 779#define M_MSIMODE_MSTRABORT _DD_MAKEMASK1(3) 780#define M_MSIMODE_PARITYERR _DD_MAKEMASK1(4) 781#define M_MSIMODE_FIFOUNRUN _DD_MAKEMASK1(5) 782#define M_MSIMODE_FIFOOVRUN _DD_MAKEMASK1(6) 783 784#define S_MSIMODE_PRIORITY 30 785#define M_MSIMODE_PRIORITY _DD_MAKEMASK(2,S_MSIMODE_PRIORITY) 786#define V_MSIMODE_PRIORITY(x) _DD_MAKEVALUE(x,S_MSIMODE_PRIORITY) 787#define G_MSIMODE_PRIORITY(x) _DD_GETVALUE(x,S_MSIMODE_PRIORITY,M_MSIMODE_PRIORITY) 788 789/* MSISTAT: MSI Status Register (0x6004) */ 790 791#define M_MSISTAT_TGTABORT _DD_MAKEMASK1(2) 792#define M_MSISTAT_MSTRABORT _DD_MAKEMASK1(3) 793#define M_MSISTAT_PARITYERR _DD_MAKEMASK1(4) 794#define M_MSISTAT_FIFOUNRUN _DD_MAKEMASK1(5) 795#define M_MSISTAT_FIFOOVRUN _DD_MAKEMASK1(6) 796 797/* MSIDATA: MSI FIFO Access Register (0x6008) */ 798 799#define S_MSIFIFO_DATA 0 800#define M_MSIFIFO_DATA _DD_MAKEMASK(3,S_MSIFIFO_DATA) 801#define V_MSIFIFO_DATA(x) _DD_MAKEVALUE(x,S_MSIFIFO_DATA) 802#define G_MSIFIFO_DATA(x) _DD_GETVALUE(x,S_MSIFIFO_DATA,M_MSIFIFO_DATA) 803 804#define M_MSIFIFO_OVFL _DD_MAKEMASK1(3) 805 806 807/* DMA Completion Registers (p 449) */ 808 809 810/* General Control registers (p 450) */ 811 812/* MCTL: Miscellaneous Host Control Register (0x6800) */ 813 814#define M_MCTL_UPDATE _DD_MAKEMASK1(0) 815#define M_MCTL_BSWAPCTRL _DD_MAKEMASK1(1) 816#define M_MCTL_WSWAPCTRL _DD_MAKEMASK1(2) 817#define M_MCTL_BSWAPDATA _DD_MAKEMASK1(4) 818#define M_MCTL_WSWAPDATA _DD_MAKEMASK1(5) 819#define M_MCTL_NOCRACK _DD_MAKEMASK1(9) 820#define M_MCTL_NOCRC _DD_MAKEMASK1(10) 821#define M_MCTL_ACCEPTBAD _DD_MAKEMASK1(11) 822#define M_MCTL_NOTXINT _DD_MAKEMASK1(13) 823#define M_MCTL_NORTRNINT _DD_MAKEMASK1(14) 824#define M_MCTL_PCI32 _DD_MAKEMASK1(15) 825#define M_MCTL_HOSTUP _DD_MAKEMASK1(16) 826#define M_MCTL_HOSTBDS _DD_MAKEMASK1(17) 827#define M_MCTL_NOTXPHSUM _DD_MAKEMASK1(20) 828#define M_MCTL_NORXPHSUM _DD_MAKEMASK1(23) 829#define M_MCTL_TXINT _DD_MAKEMASK1(24) 830#define M_MCTL_RXINT _DD_MAKEMASK1(25) 831#define M_MCTL_MACINT _DD_MAKEMASK1(26) 832#define M_MCTL_DMAINT _DD_MAKEMASK1(27) 833#define M_MCTL_FLOWINT _DD_MAKEMASK1(28) 834#define M_MCTL_4XRINGS _DD_MAKEMASK1(29) 835#define M_MCTL_MCASTEN _DD_MAKEMASK1(30) 836 837/* MCFG: Miscellaneous Configuration Register (0x6804) */ 838 839#define M_MCFG_CORERESET _DD_MAKEMASK1(0) 840#define S_MCFG_PRESCALER 1 841#define M_MCFG_PRESCALER _DD_MAKEMASK(7,S_MCFG_PRESCALER) 842#define V_MCFG_PRESCALER(x) _DD_MAKEVALUE(x,S_MCFG_PRESCALER) 843#define G_MCFG_PRESCALER(x) _DD_GETVALUE(x,S_MCFG_PRESCALER,M_MCFG_PRESCALER) 844 845/* MLCTL: Miscellaneous Local Control Register (0x6808) */ 846 847#define M_MLCTL_INTSTATE _DD_MAKEMASK1(0) 848#define M_MLCTL_INTCLR _DD_MAKEMASK1(1) 849#define M_MLCTL_INTSET _DD_MAKEMASK1(2) 850#define M_MLCTL_INTATTN _DD_MAKEMASK1(3) 851/* ... */ 852#define M_MLCTL_EPAUTOACCESS _DD_MAKEMASK1(24) 853 854/* EPADDR: Serial EEPROM Address Register (0x6838) */ 855 856#define S_EPADDR_ADDR 0 857#define M_EPADDR_ADDR (_DD_MAKEMASK(16,S_EPADDR_ADDR) & ~3) 858#define V_EPADDR_ADDR(x) _DD_MAKEVALUE(x,S_EPADDR_ADDR) 859#define G_EPADDR_ADDR(x) _DD_GETVALUE(x,S_EPADDR_ADDR,M_EPADDR_ADDR) 860 861#define S_EPADDR_HPERIOD 16 862#define M_EPADDR_HPERIOD _DD_MAKEMASK(9,S_EPADDR_HPERIOD) 863#define V_EPADDR_HPERIOD(x) _DD_MAKEVALUE(x,S_EPADDR_HPERIOD) 864#define G_EPADDR_HPERIOD(x) _DD_GETVALUE(x,S_EPADDR_HPERIOD,M_EPADDR_HPERIOD) 865 866#define M_EPADDR_START _DD_MAKEMASK1(25) 867 868#define S_EPADDR_DEVID 26 869#define M_EPADDR_DEVID _DD_MAKEMASK(3,S_EPADDR_DEVID) 870#define V_EPADDR_DEVID(x) _DD_MAKEVALUE(x,S_EPADDR_DEVID) 871#define G_EPADDR_DEVID(x) _DD_GETVALUE(x,S_EPADDR_DEVID,M_EPADDR_DEVID) 872 873#define M_EPADDR_RESET _DD_MAKEMASK1(29) 874#define M_EPADDR_COMPLETE _DD_MAKEMASK1(30) 875#define M_EPADDR_RW _DD_MAKEMASK1(31) 876 877/* EPDATA: Serial EEPROM Data Register (0x683C) */ 878 879/* EPCTL: Serial EEPROM Control Register (0x6840) */ 880 881#define M_EPCTL_CLOCKTS0 _DD_MAKEMASK1(0) 882#define M_EPCTL_CLOCKO _DD_MAKEMASK1(1) 883#define M_EPCTL_CLOCKI _DD_MAKEMASK1(2) 884#define M_EPCTL_DATATSO _DD_MAKEMASK1(3) 885#define M_EPCTL_DATAO _DD_MAKEMASK1(4) 886#define M_EPCTL_DATAI _DD_MAKEMASK1(5) 887 888/* MDCTL: MDI Control Register (0x6844) */ 889 890#define M_MDCTL_DATA _DD_MAKEMASK1(0) 891#define M_MDCTL_ENABLE _DD_MAKEMASK1(1) 892#define M_MDCTL_SELECT _DD_MAKEMASK1(2) 893#define M_MDCTL_CLOCK _DD_MAKEMASK1(3) 894 895 896/* Ring Control Blocks (p 97) */ 897 898#define RCB_HOST_ADDR_HIGH 0x0 899#define RCB_HOST_ADDR_LOW 0x4 900#define RCB_CTRL 0x8 901#define RCB_NIC_ADDR 0xC 902 903#define RCB_SIZE 0x10 904 905#define RCB_FLAG_USE_EXT_RCV_BD _DD_MAKEMASK1(0) 906#define RCB_FLAG_RING_DISABLED _DD_MAKEMASK1(1) 907 908#define S_RCB_MAXLEN 16 909#define M_RCB_MAXLEN _DD_MAKEMASK(16,S_RCB_MAXLEN) 910#define V_RCB_MAXLEN(x) _DD_MAKEVALUE(x,S_RCB_MAXLEN) 911#define G_RCB_MAXLEN(x) _DD_GETVALUE(x,S_RCB_MAXLEN,M_RCB_MAXLEN) 912 913 914/* On-chip Memory Map (Tables 70 and 71, pp 178-179) This is the map 915 for the 5700 with no external SRAM, the 5701, 5702 and 5703. The 916 5705 does not fully implement some ranges and maps the buffer pool 917 differently. */ 918 919/* Locations 0x0000 - 0x00FF are Page Zero */ 920 921/* Locations 0x0100 - 0x01FF are Send Producer Ring RCBs */ 922 923#define A_SND_RCBS 0x0100 924#define L_SND_RCBS (16*RCB_SIZE) 925#define A_SND_RCB(n) (A_SND_RCBS + ((n)-1)*RCB_SIZE) 926 927/* Locations 0x0200 - 0x02FF are Receive Return Ring RCBs */ 928 929#define A_RTN_RCBS 0x0200 930#define L_RTN_RCBS (16*RCB_SIZE) 931#define A_RTN_RCB(n) (A_RTN_RCBS + ((n)-1)*RCB_SIZE) 932 933/* Locations 0x0300 - 0x0AFF are Statistics Block */ 934 935#define A_MAC_STATS 0x0300 936#define L_MAC_STATS (0x0B00-A_MAC_STATS) 937 938/* Locations 0x0B00 - 0x0B4F are Status Block */ 939 940#define A_MAC_STATUS 0x0B00 941#define L_MAC_STATUS (0x0B50-A_MAC_STATUS) 942 943/* Locations 0x0B50 - 0x0FFF are Software General Communication */ 944 945#define A_PXE_MAILBOX 0x0B50 946#define T3_MAGIC_NUMBER 0x4B657654 947 948/* Locations 0x1000 - 0x1FFF are unmapped */ 949 950/* Locations 0x2000 - 0x3FFF are DMA Descriptors */ 951 952#define A_DMA_DESCS 0x2000 953#define L_DMA_DESCS (0x4000-A_DMA_DESCS) 954 955/* Locations 0x4000 - 0x5FFF are Send Rings 1-4 */ 956 957#define A_SND_RINGS 0x4000 958#define L_SND_RINGS (0x6000-A_SND_RINGS) 959 960/* Locations 0x6000 - 0x6FFF are Standard Receive Rings */ 961 962#define A_STD_RCV_RINGS 0x6000 963#define L_STD_RCV_RINGS (0x7000-A_STD_RCV_RINGS) 964 965/* Locations 0x7000 - 0x7FFF are Jumbo Receive Rings */ 966 967#define A_JUMBO_RCV_RINGS 0x7000 968#define L_JUMBO_RCV_RINGS (0x8000-A_JUMBO_RCV_RINGS) 969 970/* Locations 0x08000 - 0x0FFFF are Buffer Pool 1 */ 971/* Locations 0x10000 - 0x17FFF are Buffer Pool 2 */ 972/* Locations 0x18000 - 0x1FFFF are Buffer Pool 3 */ 973 974#define A_BUFFER_POOL 0x08000 975#define L_BUFFER_POOL (0x20000-A_BUFFER_POOL) 976 977/* Locations 0x08000 - 0x09FFF are TXMBUF (5705) */ 978/* Locations 0x10000 - 0x1DFFF are RXMBUF (5705) */ 979 980#define A_TXMBUF 0x08000 981#define L_TXMBUF (0x0A000-A_TXMBUF) 982#define A_RXMBUF 0x10000 983#define L_RXMBUF (0x1E000-A_RXMBUF) 984 985 986/* Indices of (8-byte) counters in the Statistics Block. */ 987 988#define ifHCInOctets 32 989#define etherStatsFragments 34 990#define ifHCInUcastPkts 35 991#define ifHCInMulticastPkts 36 992#define ifHCInBroadcastPkts 37 993#define dot3StatsFCSErrors 38 994#define dot3StatsAlignmentErrors 39 995#define xonPauseFramesReceived 40 996#define xoffPauseFramesReceived 41 997#define macControlFramesReceived 42 998#define xoffSateEntered 43 999#define dot3StatsFrameTooLongs 44 1000#define etherStatsJabbers 45 1001#define etherStatsUndersizePkts 46 1002#define inRangeLengthError 47 1003#define outRangeLengthError 48 1004#define etherStatsPkts64Octets 49 1005#define etherStatsPkts65to127Octets 50 1006#define etherStatsPkts128to255Octets 51 1007#define etherStatsPkts256to511Octets 52 1008#define etherStatsPkts512to1023Octets 53 1009#define etherStatsPkts1024to1522Octets 54 1010#define etherStatsPkts1523to2047Octets 55 1011#define etherStatsPkts2048to4095Octets 56 1012#define etherStatsPkts4096to8191Octets 57 1013#define etherStatsPkts8192to9022Octets 58 1014 1015#define ifHCOutOctets 96 1016#define etherStatsCollisions 98 1017#define outXonSent 99 1018#define outXoffSent 100 1019#define flowControlDone 101 1020#define dot3StatsInternalMacTransmitErrors 102 1021#define dot3StatsSingleCollisionFrames 103 1022#define dot3StatsMultipleCollisionFrames 104 1023#define dot3StatsDeferredTransmissions 105 1024#define dot3StatsExcessiveCollisions 107 1025#define dot3StatsLateCollisions 108 1026#define dot3Collided2Times 109 1027#define dot3Collided3Times 110 1028#define dot3Collided4Times 111 1029#define dot3Collided5Times 112 1030#define dot3Collided6Times 113 1031#define dot3Collided7Times 114 1032#define dot3Collided8Times 115 1033#define dot3Collided9Times 116 1034#define dot3Collided10Times 117 1035#define dot3Collided11Times 118 1036#define dot3Collided12Times 119 1037#define dot3Collided13Times 120 1038#define dot3Collided14Times 121 1039#define dot3Collided15Times 122 1040#define ifHCOutUcastPkts 123 1041#define ifHCOutMulticastPkts 124 1042#define ifHCOutBroadcastPkts 125 1043#define dot3StatsCarrierSenseErrors 126 1044#define ifOutDiscards 127 1045#define ifOutErrors 128 1046 1047#define COSifHCInPkts1 160 1048#define COSifHCInPkts2 161 1049#define COSifHCInPkts3 162 1050#define COSifHCInPkts4 163 1051#define COSifHCInPkts5 164 1052#define COSifHCInPkts6 165 1053#define COSifHCInPkts7 166 1054#define COSifHCInPkts8 167 1055#define COSifHCInPkts9 168 1056#define COSifHCInPkts10 169 1057#define COSifHCInPkts11 170 1058#define COSifHCInPkts12 171 1059#define COSifHCInPkts13 172 1060#define COSifHCInPkts14 173 1061#define COSifHCInPkts15 174 1062#define COSifHCInPkts16 175 1063#define COSFramesDroppedDueToFilters 176 1064#define nicDmaWriteQueueFull 177 1065#define nicDmaWriteHighPriQueueFull 178 1066#define nicNoMoreRxBDs 179 1067#define ifInDiscards 180 1068#define ifInErrors 181 1069#define nicRecvThresholdHit 182 1070 1071#define COSifHCOutPkts1 192 1072#define COSifHCOutPkts2 193 1073#define COSifHCOutPkts3 194 1074#define COSifHCOutPkts4 195 1075#define COSifHCOutPkts5 196 1076#define COSifHCOutPkts6 197 1077#define COSifHCOutPkts7 198 1078#define COSifHCOutPkts8 199 1079#define COSifHCOutPkts9 200 1080#define COSifHCOutPkts10 201 1081#define COSifHCOutPkts11 202 1082#define COSifHCOutPkts12 203 1083#define COSifHCOutPkts13 204 1084#define COSifHCOutPkts14 205 1085#define COSifHCOutPkts15 206 1086#define COSifHCOutPkts16 207 1087#define nicDmaReadQueueFull 208 1088#define nicDmaReadHighPriQueueFull 209 1089#define nicSendDataCompQueueFull 210 1090#define nicRingSetSendProdIndex 211 1091#define nicRingStatusUpdate 212 1092#define nicInterrupts 213 1093#define nicAvoidedInterrupts 214 1094#define nicSendThresholdHit 215 1095 1096#endif /* _BCM_5700_H_ */ 1097