1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * BCM440X (10/100 Ethernet MAC) registers File: bcm4401.h 5 * 6 ********************************************************************* 7 * 8 * Copyright 2000,2001,2002,2003 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and 13 * conditions. Subject to these conditions, you may download, 14 * copy, install, use, modify and distribute modified or unmodified 15 * copies of this software in source and/or binary form. No title 16 * or ownership is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions 20 * as they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products derived 25 * from this software without the prior written permission of 26 * Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 40 * THE POSSIBILITY OF SUCH DAMAGE. 41 ********************************************************************* */ 42 43#ifndef _BCM4400_H_ 44#define _BCM4400_H_ 45 46/* 47 * Register and bit definitions for the Broadcom BCM440X family 48 * of 10/100 MACs with integrated PHY. Similar controllers are used 49 * in certain SOC products. 50 */ 51 52/* 53 * References: 54 * 55 * Programmer's Guide BCM440X PCI 10/100 Ethernet and 56 * V.90/V.92 Controller, 440X-PG00-R 57 * Broadcom Corp., 16215 Alton Parkway, Irvine CA, 08/23/02 58 * 59 * BCM4401 PCI 10/100 Ethernet Controller Data Sheet, 4401-DS104-R 60 * Broadcom Corp., 16215 Alton Parkway, Irvine CA, 1/30/03 61 */ 62 63#define _DD_MAKEMASK1(n) (1 << (n)) 64#define _DD_MAKEMASK(v,n) ((((1)<<(v))-1) << (n)) 65#define _DD_MAKEVALUE(v,n) ((v) << (n)) 66#define _DD_GETVALUE(v,n,m) (((v) & (m)) >> (n)) 67 68#define K_PCI_VENDOR_BROADCOM 0x14e4 69#define K_PCI_ID_BCM4401 0x4401 /* Rev A0, A1 */ 70#define K_PCI_ID_BCM4401_B 0x170C /* Rev B0 and later */ 71#define K_PCI_ID_BCM4402 0x4402 /* used by HND */ 72 73/* PCI Configuration Registers (440X extensions) */ 74 75#define PCI_PMC_REG 0x40 76#define PCI_PMCSR_REG 0x44 77#define PCI_PMDATA_REG 0x48 78 79#define PCI_PCIBAR0WINDOW_REG 0x80 80#define PCI_PCIBAR1WINDOW_REG 0x84 81#define PCI_SPROMCONTROL_REG 0x88 82#define PCI_BAR1BURSTCTRL_REG 0x8C 83#define PCI_PCIINTSTATUS_REG 0x90 84#define PCI_PCIINTMASK_REG 0x94 85#define PCI_SBMAILBOX_REG 0x98 86#define PCI_BACKPLANEADDR_REG 0xA0 87#define PCI_BACKPLANEDATA_REG 0xA4 88 89 90/* SBISR: PCI Interrupt Status Register (0x90, R/W) */ 91/* SBIMR: PCI Interrupt Mask Register (0x94, R/W) */ 92 93#define S_SBINT_BM 0 /* SBMailbox */ 94#define M_SBINT_BM _DD_MAKEMASK(2,S_SBINT_BM) 95#define V_SBINT_BM(x) _DD_MAKEVALUE(x,S_SBINT_BM) 96#define G_SBINT_BM(x) _DD_GETVALUE(x,S_SBINT_BM,M_SBINT_BM) 97 98#define M_SBINT_SB _DD_MAKEMASK1(2) /* SBError */ 99 100#define S_SBINT_IM 8 /* SBIntMask */ 101#define M_SBINT_IM _DD_MAKEMASK(8,S_SBINT_IM) 102#define V_SBINT_IM(x) _DD_MAKEVALUE(x,S_SBINT_IM) 103#define G_SBINT_IM(x) _DD_GETVALUE(x,S_SBINT_IM,M_SBINT_IM) 104 105 106/* 107 * The 440x products contain multiple cores that communicate via a 108 * system backplane internal to the chip. The 4401 includes a MAC 109 * core (with indirect access to the internal PHY) and a PCI core. 110 * The 4402 adds a codec core, which appears in 4401 enumeration space. 111 * 112 * Each core occupies 4K (0x1000) bytes of "enumeration" space. Each 113 * includes a configuration region at offset 0xF00 consisting of 114 * registers to identify the core and map its resources. Some cores, 115 * including the MAC, have a standard DMA engine; if so, its registers 116 * appear at offset 0x200. 117 * 118 * In theory, the positioning of address spaces for each core is 119 * programmable; in practice, a standard configuration is loaded from 120 * EEPROM on reset (see data sheet), and the MAC core's enumeration 121 * space is thereafter accessible via BAR 0. */ 122 123 124/* System backplane addresses of cores */ 125 126#ifndef SB_PCI_BASE /* XXX this should not be here */ 127#define SB_ENET_BASE 0x18000000 128#define SB_CODEC_BASE 0x18001000 /* bond-out on 4402 only */ 129#define SB_PCI_BASE 0x18002000 130#endif 131 132 133/* Ethernet 10/100 Core (Section 5, Table 102) */ 134 135#define R_DEV_CONTROL 0x000 136#define R_BIST_STATUS 0x00C 137#define R_WAKEUP_LENGTH 0x010 138#define R_INT_STATUS 0x020 139#define R_INT_MASK 0x024 140#define R_GP_TIMER 0x028 141#define R_ENET_FT_ADDR 0x090 142#define R_ENET_FT_DATA 0x094 143#define R_EMAC_XMT_MAX_BURST 0x0A0 144#define R_EMAC_RCV_MAX_BURST 0x0A4 145#define R_EMAC_CONTROL 0x0A8 146#define R_INT_RECV_LAZY 0x100 147 148/* Core DMA Engine Registers (Section 3) */ 149 150#define R_XMT_CONTROL 0x200 151#define R_XMT_ADDR 0x204 152#define R_XMT_PTR 0x208 153#define R_XMT_STATUS 0x20C 154#define R_RCV_CONTROL 0x210 155#define R_RCV_ADDR 0x214 156#define R_RCV_PTR 0x218 157#define R_RCV_STATUS 0x21C 158 159/* EMAC Registers */ 160 161#define R_RCV_CONFIG 0x400 162#define R_RCV_MAX_LENGTH 0x404 163#define R_XMT_MAX_LENGTH 0x408 164#define R_MII_STATUS_CONTROL 0x410 165#define R_MII_DATA 0x414 166#define R_ENET_INT_MASK 0x418 167#define R_ENET_INT_STATUS 0x41C 168#define R_CAM_DATA_L 0x420 169#define R_CAM_DATA_H 0x424 170#define R_CAM_CONTROL 0x428 171#define R_ENET_CONTROL 0x42C 172#define R_XMT_CONTROL1 0x430 173#define R_XMT_WATERMARK 0x434 174#define R_MIB_CONTROL 0x438 175#define R_MIB_COUNTERS 0x500 /* Block base address */ 176 177/* Core Configuration Space Registers (Section 2, Table 3) */ 178 179#define R_SBIMSTATE 0xF90 180#define R_SBINTVEC 0xF94 181#define R_SBTMSTATELOW 0xF98 182#define R_SBTMSTATEHI 0xF9C 183#define R_SBBWA0 0xFA0 184#define R_SBIMCONFIGLOW 0xFA8 185#define R_SBIMCONFIGHIGH 0xFAC 186#define R_SBADMATCH0 0xFB0 187#define R_SBTMCONFIGLOW 0xFB8 188#define R_SBTMCONFIGHIGH 0xFBC 189#define R_SBBCONFIG 0xFC0 190#define R_SBBSTATE 0xFC8 191#define R_SBACTCNFG 0xFD8 192#define R_SBFLAGST 0xFE8 193#define R_SBIDLOW 0xFF8 194#define R_SBIDHIGH 0xFFC 195 196 197/* Ethernet PHY MII (Section 5, Table 103) */ 198 199#define R_BMCR 0x00 200#define R_BMSR 0x01 201#define R_PHYIDR1 0x02 202#define R_PHYIDR2 0x03 203#define R_ANAR 0x04 204#define R_ANLPAR 0x05 205#define R_ANER 0x06 206#define R_NEXT_PAGE 0x07 207#define R_LP_NEXT_PAGE 0x08 208 209#define R_100X_AUX_CONTROL 0x10 210#define R_100X_AUX_STATUS 0x11 211#define R_100X_RCV_ERROR_CTR 0x12 212#define R_100X_CARR_SENSE_CTR 0x13 213#define R_100X_DISCONNECT_CRT 0x14 214#define R_AUX_CTL_STATUS 0x18 215#define R_AUX_STATUS_SUMMARY 0x19 216#define R_INTERRUPT 0x1A 217#define R_AUX_MODE_2 0x1B 218#define R_10BT_T_ERR_GEN_STAT 0x1C 219#define R_AUX_MODE 0x1D 220#define R_AUX_MULTI_PHY 0x1E 221 222 223/* Codec Core (Section 4) - BCM4402 only, not supported. */ 224 225 226/* PCI Core (Section 6) */ 227 228/* Extended PCI Configuration Space */ 229 230#define R_PCI_BAR0_WINDOW 0x080 231#define R_PCI_BAR1_WINDOW 0x084 232#define R_BAR1_BURST_CONTROL 0x08C 233#define R_PCI_INT_STATUS 0x090 234#define R_PCI_INT_MASK 0x094 235#define R_PCI_TO_SB_MAILBOX 0x098 236 237#define R_BACKPLANE_ADDRESS 0x0A0 238#define R_BACKPLANE_DATA 0x0A4 239 240/* PCI Enumeration Space */ 241 242#define R_SB_TO_PCI_MAILBOX 0x028 243#define R_BROADCAST_ADDRESS 0x050 244#define R_BROADCAST_DATA 0x054 245#define R_GPIO_INPUT 0x060 246#define R_GPIO_OUTPUT 0x064 247#define R_GPIO_OUT_EN 0x068 248#define R_GPIO_CONTROL 0x06C 249 250#define R_SB_TO_PCI_TRANSLATION0 0x100 251#define R_SB_TO_PCI_TRANSLATION1 0x104 252#define R_SB_TO_PCI_TRANSLATION2 0x108 /* Not documented */ 253 254 255/* Core Configuration Space Registers. */ 256 257/* These registers are found at the top of the 4K window for each core. */ 258 259/* SBIS: System Backplace Initiator State Register (0xF90, R/W) */ 260 261#define S_SBIS_PC 0 /* PipeCount */ 262#define M_SBIS_PC _DD_MAKEMASK(4,S_SBIS_PC) 263#define V_SBIS_PC(x) _DD_MAKEVALUE(x,S_SBIS_PC) 264#define G_SBIS_PC(x) _DD_GETVALUE(x,S_SBIS_PC,M_SBIS_PC) 265 266#define S_SBIS_PL 4 /* Policy */ 267#define M_SBIS_PL _DD_MAKEMASK(2,S_SBIS_PL) 268#define V_SBIS_PL(x) _DD_MAKEVALUE(x,S_SBIS_PL) 269#define G_SBIS_PL(x) _DD_GETVALUE(x,S_SBIS_PL,M_SBIS_PL) 270 271#define M_SBIS_IE _DD_MAKEMASK1(17) /* InbandError */ 272#define M_SBIS_TO _DD_MAKEMASK1(18) /* TimeOut */ 273 274/* SBINT: System Backplane Interrupt Vector Register (0xF94, R/W) */ 275 276#define S_SBINT_MK 0 /* Mask */ 277#define M_SBINT_MK _DD_MAKEMASK(3,S_SBINT_MK) 278#define V_SBINT_MK(x) _DD_MAKEVALUE(x,S_SBINT_MK) 279#define G_SBINT_MK(x) _DD_GETVALUE(x,S_SBINT_MK,M_SBINT_MK) 280#define K_SBINT_PCI (1<<0) 281#define K_SBINT_ENET_MAC (1<<1) 282#define K_SBINT_CODEC (1<<2) 283 284/* SBTS(LO): System Backplane Target State Low Register (0xF98, R/W) */ 285 286#define M_SBTS_RS _DD_MAKEMASK1(0) /* Reset */ 287#define M_SBTS_RJ _DD_MAKEMASK1(1) /* Reject */ 288#define M_SBTS_CE _DD_MAKEMASK1(16) /* ClockEnable */ 289#define M_SBTS_FC _DD_MAKEMASK1(17) /* ForceGatedClocks */ 290 291#define S_SBTS_FL 18 /* Flags */ 292#define M_SBTS_FL _DD_MAKEMASK(12,S_SBTS_FL) 293#define V_SBTS_FL(x) _DD_MAKEVALUE(x,S_SBTS_FL) 294#define G_SBTS_FL(x) _DD_GETVALUE(x,S_SBTS_FL,M_SBTS_FL) 295 296#define M_SBTS_PE _DD_MAKEMASK1(30) /* PMEEnable */ 297#define M_SBTS_BE _DD_MAKEMASK1(31) /* BISTEnable */ 298 299/* SBTS(HI): System Backplane Target State High Register (0xF9C, R/W) */ 300 301#define M_SBTS_SE _DD_MAKEMASK1(0) /* SError */ 302#define M_SBTS_IN _DD_MAKEMASK1(1) /* Interrupt */ 303#define M_SBTS_BY _DD_MAKEMASK1(2) /* Busy */ 304#define M_SBTS_GC _DD_MAKEMASK1(29) /* GatedClkRequest */ 305#define M_SBTS_BF _DD_MAKEMASK1(30) /* BISTFail */ 306#define M_SBTS_BD _DD_MAKEMASK1(31) /* BISTDone */ 307 308/* SBFS: System Backplane Flag Status Register (0xFE8, RO) */ 309 310#define M_SBFS_MI _DD_MAKEMASK1(7) /* MII pins disabled */ 311 312/* SBID(LO): System Backplane Identification Low Register (0xFF8, RO) */ 313 314#define S_SBID_CS 0 /* ConfigSpace */ 315#define M_SBID_CS _DD_MAKEMASK(3,S_SBID_CS) 316#define V_SBID_CS(x) _DD_MAKEVALUE(x,S_SBID_CS) 317#define G_SBID_CS(x) _DD_GETVALUE(x,S_SBID_CS,M_SBID_CS) 318 319#define S_SBID_AR 3 /* AddressRanges */ 320#define M_SBID_AR _DD_MAKEMASK(3,S_SBID_AR) 321#define V_SBID_AR(x) _DD_MAKEVALUE(x,S_SBID_AR) 322#define G_SBID_AR(x) _DD_GETVALUE(x,S_SBID_AR,M_SBID_AR) 323 324#define M_SBID_SC _DD_MAKEMASK1(6) /* Synch */ 325#define M_SBID_IT _DD_MAKEMASK1(7) /* Initiator */ 326 327#define S_SBID_MN 8 /* MinLatency */ 328#define M_SBID_MN _DD_MAKEMASK(4,S_SBID_MN) 329#define V_SBID_MN(x) _DD_MAKEVALUE(x,S_SBID_MN) 330#define G_SBID_MN(x) _DD_GETVALUE(x,S_SBID_MN,M_SBID_MN) 331 332#define S_SBID_MX 12 /* MaxLatency */ 333#define M_SBID_MX _DD_MAKEMASK(4,S_SBID_MX) 334#define V_SBID_MX(x) _DD_MAKEVALUE(x,S_SBID_MX) 335#define G_SBID_MX(x) _DD_GETVALUE(x,S_SBID_MX,M_SBID_MX) 336 337#define M_SBID_FI _DD_MAKEMASK1(16) /* FirstInitiator */ 338#define M_SBID_NT _DD_MAKEMASK1(17) /* NoTarget */ 339 340#define S_SBID_CC 18 /* CycleCounterWidth */ 341#define M_SBID_CC _DD_MAKEMASK(2,S_SBID_CC) 342#define V_SBID_CC(x) _DD_MAKEVALUE(x,S_SBID_CC) 343#define G_SBID_CC(x) _DD_GETVALUE(x,S_SBID_CC,M_SBID_CC) 344 345#define S_SBID_TP 20 /* TargetPorts */ 346#define M_SBID_TP _DD_MAKEMASK(4,S_SBID_TP) 347#define V_SBID_TP(x) _DD_MAKEVALUE(x,S_SBID_TP) 348#define G_SBID_TP(x) _DD_GETVALUE(x,S_SBID_TP,M_SBID_TP) 349 350#define S_SBID_IP 24 /* InitPorts */ 351#define M_SBID_IP _DD_MAKEMASK(4,S_SBID_IP) 352#define V_SBID_IP(x) _DD_MAKEVALUE(x,S_SBID_IP) 353#define G_SBID_IP(x) _DD_GETVALUE(x,S_SBID_IP,M_SBID_IP) 354 355/* SBID(HI): System Backplane Identification High Register (0xFFC, RO) */ 356 357#define S_SBID_RV 0 /* Revision */ 358#define M_SBID_RV _DD_MAKEMASK(4,S_SBID_RV) 359#define V_SBID_RV(x) _DD_MAKEVALUE(x,S_SBID_RV) 360#define G_SBID_RV(x) _DD_GETVALUE(x,S_SBID_RV,M_SBID_RV) 361 362#define S_SBID_CR 4 /* Core */ 363#define M_SBID_CR _DD_MAKEMASK(12,S_SBID_CR) 364#define V_SBID_CR(x) _DD_MAKEVALUE(x,S_SBID_CR) 365#define G_SBID_CR(x) _DD_GETVALUE(x,S_SBID_CR,M_SBID_CR) 366#define K_CR_PCI 0x804 367#define K_CR_ENET_MAC 0x806 368#define K_CR_CODEC 0x807 369 370#define S_SBID_VN 16 /* Vendor */ 371#define M_SBID_VN _DD_MAKEMASK(16,S_SBID_VN) 372#define V_SBID_VN(x) _DD_MAKEVALUE(x,S_SBID_VN) 373#define G_SBID_VN(x) _DD_GETVALUE(x,S_SBID_VN,M_SBID_VN) 374#define K_VN_BROADCOM 0x4243 375 376 377/* Ethernet MAC Registers */ 378 379/* DVCTL: Device Control Register (0x000, R/W) */ 380 381#define M_DVCTL_PM _DD_MAKEMASK1(7) /* PatMatchEn */ 382#define M_DVCTL_IP _DD_MAKEMASK1(10) /* InternalEPHY */ 383#define M_DVCTL_ER _DD_MAKEMASK1(15) /* EPHYReset */ 384#define M_DVCTL_MP _DD_MAKEMASK1(16) /* MIIPHYModeEn */ 385#define M_DVCTL_CO _DD_MAKEMASK1(17) /* ClkOutputEn */ 386 387#define S_DVCTL_PA 18 /* PHYAddrReg */ 388#define M_DVCTL_PA _DD_MAKEMASK(5,S_DVCTL_PA) 389#define V_DVCTL_PA(x) _DD_MAKEVALUE(x,S_DVCTL_PA) 390#define G_DVCTL_PA(x) _DD_GETVALUE(x,S_DVCTL_PA,M_DVCTL_PA) 391 392/* BIST: Built-In Self Test Register (0x00C, RO) */ 393 394#define S_BIST_BS 0 /* BISTStatus */ 395#define M_BIST_BS _DD_MAKEMASK(2,S_BIST_BS) 396#define V_BIST_BS(x) _DD_MAKEVALUE(x,S_BIST_BS) 397#define G_BIST_BS(x) _DD_GETVALUE(x,S_BIST_BS,M_BIST_BS) 398 399/* WKUP: Wakeup Length Register (0x010, R/W) */ 400 401#define S_WKUP_P0 0 /* Pattern0 */ 402#define M_WKUP_P0 _DD_MAKEMASK(7,S_WKUP_P0) 403#define V_WKUP_P0(x) _DD_MAKEVALUE(x,S_WKUP_P0) 404#define G_WKUP_P0(x) _DD_GETVALUE(x,S_WKUP_P0,M_WKUP_P0) 405 406#define M_WKUP_D0 _DD_MAKEMASK1(7) /* Disable0 */ 407 408#define S_WKUP_P1 0 /* Pattern1 */ 409#define M_WKUP_P1 _DD_MAKEMASK(7,S_WKUP_P1) 410#define V_WKUP_P1(x) _DD_MAKEVALUE(x,S_WKUP_P1) 411#define G_WKUP_P1(x) _DD_GETVALUE(x,S_WKUP_P1,M_WKUP_P1) 412 413#define M_WKUP_D1 _DD_MAKEMASK1(15) /* Disable1 */ 414 415#define S_WKUP_P2 0 /* Pattern2 */ 416#define M_WKUP_P2 _DD_MAKEMASK(7,S_WKUP_P2) 417#define V_WKUP_P2(x) _DD_MAKEVALUE(x,S_WKUP_P2) 418#define G_WKUP_P2(x) _DD_GETVALUE(x,S_WKUP_P2,M_WKUP_P2) 419 420#define M_WKUP_D2 _DD_MAKEMASK1(23) /* Disable2 */ 421 422#define S_WKUP_P3 0 /* Pattern3 */ 423#define M_WKUP_P3 _DD_MAKEMASK(7,S_WKUP_P3) 424#define V_WKUP_P3(x) _DD_MAKEVALUE(x,S_WKUP_P3) 425#define G_WKUP_P3(x) _DD_GETVALUE(x,S_WKUP_P3,M_WKUP_P3) 426 427#define M_WKUP_D3 _DD_MAKEMASK1(31) /* Disable3 */ 428 429/* ISR: Interrupt Status Register (0x020, R/W) */ 430/* IMR: Interrupt Mask Register (0x024, R/W) */ 431 432#define M_INT_PM _DD_MAKEMASK1(6) /* PME */ 433#define M_INT_TO _DD_MAKEMASK1(7) /* TimeOut */ 434#define M_INT_DE _DD_MAKEMASK1(10) /* DescErr */ 435#define M_INT_DA _DD_MAKEMASK1(11) /* DataErr */ 436#define M_INT_DP _DD_MAKEMASK1(12) /* DescProtoErr */ 437#define M_INT_RU _DD_MAKEMASK1(13) /* RcvDescUf */ 438#define M_INT_RO _DD_MAKEMASK1(14) /* RcvFIFOOf */ 439#define M_INT_XU _DD_MAKEMASK1(15) /* XmtFIFOUf */ 440#define M_INT_RI _DD_MAKEMASK1(16) /* RcvInt */ 441#define M_INT_XI _DD_MAKEMASK1(24) /* XmtInt */ 442#define M_INT_EI _DD_MAKEMASK1(26) /* EMACInterrupt */ 443#define M_INT_IW _DD_MAKEMASK1(27) /* IntMIIWrite */ 444#define M_INT_IR _DD_MAKEMASK1(28) /* IntMIIRead */ 445 446/* EMCTL: Ethernet MAC Control Register (0x0A8, R/W) */ 447 448#define M_EMCTL_CC _DD_MAKEMASK1(0) /* CRCCheckXmt */ 449#define M_EMCTL_EP _DD_MAKEMASK1(2) /* EPHYPowerDown */ 450#define M_EMCTL_ED _DD_MAKEMASK1(3) /* EPHYEnergyDetect */ 451 452#define S_EMCTL_LC 5 /* LEDControl */ 453#define M_EMCTL_LC _DD_MAKEMASK(3,S_EMCTL_LC) 454#define V_EMCTL_LC(x) _DD_MAKEVALUE(x,S_EMCTL_LC) 455#define G_EMCTL_LC(x) _DD_GETVALUE(x,S_EMCTL_LC,M_EMCTL_LC) 456 457/* EMFLOW: Ethernet MAC Flow Control Register (0x0AC, R/W) */ 458 459#define S_EMFLOW_RF 0 /* RcvFlowControl */ 460#define M_EMFLOW_RF _DD_MAKEMASK(8,S_EMFLOW_RF) 461#define V_EMFLOW_RF(x) _DD_MAKEVALUE(x,S_EMFLOW_RF) 462#define G_EMFLOW_RF(x) _DD_GETVALUE(x,S_EMFLOWL_RF,M_EFLOW_RF) 463 464#define M_EMFLOW_PE _DD_MAKEMASK1(15) /* PauseEn */ 465 466 467/* INTLZY: Interrupt Receive Lazy Timeout Register (0x100, R/W) */ 468 469#define S_INTLZY_TO 0 /* TimeOut */ 470#define M_INTLZY_TO _DD_MAKEMASK(24,S_INTLZY_TO) 471#define V_INTLZY_TO(x) _DD_MAKEVALUE(x,S_INTLZY_TO) 472#define G_INTLZY_TO(x) _DD_GETVALUE(x,S_INTLZY_TO,M_INTLZY_TO) 473 474#define S_INTLZY_FC 24 /* FrameCount */ 475#define M_INTLZY_FC _DD_MAKEMASK(8,S_INTLZY_FC) 476#define V_INTLZY_FC(x) _DD_MAKEVALUE(x,S_INTLZY_FC) 477#define G_INTLZY_FC(x) _DD_GETVALUE(x,S_INTLZY_FC,M_INTLZY_FC) 478 479 480/* RCFG: Receiver Configuration Register (0x400, R/W) */ 481 482#define M_RCFG_DB _DD_MAKEMASK1(0) /* DisB */ 483#define M_RCFG_AM _DD_MAKEMASK1(1) /* AccMult */ 484#define M_RCFG_RD _DD_MAKEMASK1(2) /* RcvDisableTx */ 485#define M_RCFG_PR _DD_MAKEMASK1(3) /* Prom */ 486#define M_RCFG_LB _DD_MAKEMASK1(4) /* Lpbk */ 487#define M_RCFG_EF _DD_MAKEMASK1(5) /* EnFlow */ 488#define M_RCFG_UF _DD_MAKEMASK1(6) /* UniFlow */ 489#define M_RCFG_RF _DD_MAKEMASK1(7) /* RejectFilter */ 490 491 492/* MIICTL: MII Status/Control Register (0x410, R/W) */ 493 494#define S_MIICTL_MD 0 /* MDC */ 495#define M_MIICTL_MD _DD_MAKEMASK(7,S_MIICTL_MD) 496#define V_MIICTL_MD(x) _DD_MAKEVALUE(x,S_MIICTL_MD) 497#define G_MIICTL_MD(x) _DD_GETVALUE(x,S_MIICTL_MD,M_MIICTL_MD) 498 499#define M_MIICTL_PR _DD_MAKEMASK1(7) /* PreEn */ 500 501/* MIIDATA: MII Data Register (0x414, R/W) */ 502 503#define S_MIIDATA_D 0 /* Data */ 504#define M_MIIDATA_D _DD_MAKEMASK(16,S_MIIDATA_D) 505#define V_MIIDATA_D(x) _DD_MAKEVALUE(x,S_MIIDATA_D) 506#define G_MIIDATA_D(x) _DD_GETVALUE(x,S_MIIDATA_D,M_MIIDATA_D) 507 508#define S_MIIDATA_TA 16 /* Turnaround */ 509#define M_MIIDATA_TA _DD_MAKEMASK(2,S_MIIDATA_TA) 510#define V_MIIDATA_TA(x) _DD_MAKEVALUE(x,S_MIIDATA_TA) 511#define G_MIIDATA_TA(x) _DD_GETVALUE(x,S_MIIDATA_TA,M_MIIDATA_TA) 512#define K_TA_VALID 0x2 513 514#define S_MIIDATA_RA 18 /* RegAddr */ 515#define M_MIIDATA_RA _DD_MAKEMASK(5,S_MIIDATA_RA) 516#define V_MIIDATA_RA(x) _DD_MAKEVALUE(x,S_MIIDATA_RA) 517#define G_MIIDATA_RA(x) _DD_GETVALUE(x,S_MIIDATA_RA,M_MIIDATA_RA) 518 519#define S_MIIDATA_PM 23 /* PhysMedia */ 520#define M_MIIDATA_PM _DD_MAKEMASK(5,S_MIIDATA_PM) 521#define V_MIIDATA_PM(x) _DD_MAKEVALUE(x,S_MIIDATA_PM) 522#define G_MIIDATA_PM(x) _DD_GETVALUE(x,S_MIIDATA_PM,M_MIIDATA_PM) 523 524#define S_MIIDATA_OP 28 /* Opcode */ 525#define M_MIIDATA_OP _DD_MAKEMASK(2,S_MIIDATA_OP) 526#define V_MIIDATA_OP(x) _DD_MAKEVALUE(x,S_MIIDATA_OP) 527#define G_MIIDATA_OP(x) _DD_GETVALUE(x,S_MIIDATA_OP,M_MIIDATA_OP) 528#define K_MII_OP_WRITE 0x1 529#define K_MII_OP_READ 0x2 530 531#define S_MIIDATA_SB 30 /* StartBits */ 532#define M_MIIDATA_SB _DD_MAKEMASK(2,S_MIIDATA_SB) 533#define V_MIIDATA_SB(x) _DD_MAKEVALUE(x,S_MIIDATA_SB) 534#define G_MIIDATA_SB(x) _DD_GETVALUE(x,S_MIIDATA_SB,M_MIIDATA_SB) 535#define K_MII_START 0x1 536 537/* EIMR: Ethernet Interrupt Mask Register (0x418, R/W) */ 538/* EISR: Ethernet Interrupt Status Register (0x41C, R/W) */ 539 540#define M_EINT_MI _DD_MAKEMASK1(0) /* MIIInt */ 541#define M_EINT_MB _DD_MAKEMASK1(1) /* MIBInt */ 542#define M_EINT_FM _DD_MAKEMASK1(2) /* FlowInt */ 543 544/* CAM: CAM Data Low Register (0x420, R/W) */ 545 546#define S_CAM_CD_L 0 /* CAMDataL */ 547#define M_CAM_CD_L _DD_MAKEMASK(32,S_CAM_CD_L) 548#define V_CAM_CD_L(x) _DD_MAKEVALUE(x,S_CAM_CD_L) 549#define G_CAM_CD_L(x) _DD_GETVALUE(x,S_CAM_CD_L,M_CAM_CD_L) 550 551/* CAM: CAM Data High Register (0x424, R/W) */ 552 553#define S_CAM_CD_H 0 /* CAMDataH */ 554#define M_CAM_CD_H _DD_MAKEMASK(16,S_CAM_CD_H) 555#define V_CAM_CD_H(x) _DD_MAKEVALUE(x,S_CAM_CD_H) 556#define G_CAM_CD_H(x) _DD_GETVALUE(x,S_CAM_CD_H,M_CAM_CD_H) 557 558#define M_CAM_VB _DD_MAKEMASK1(16) /* ValidBit */ 559 560/* CAMCTL: CAM Control Register (0x428, R/W) */ 561 562#define M_CAMCTL_CE _DD_MAKEMASK1(0) /* CAMEnable */ 563#define M_CAMCTL_MS _DD_MAKEMASK1(1) /* MaskSelect */ 564#define M_CAMCTL_CR _DD_MAKEMASK1(2) /* CAMRead */ 565#define M_CAMCTL_CW _DD_MAKEMASK1(3) /* CAMWrite */ 566 567#define S_CAMCTL_IX 16 /* Index */ 568#define M_CAMCTL_IX _DD_MAKEMASK(6,S_CAMCTL_IX) 569#define V_CAMCTL_IX(x) _DD_MAKEVALUE(x,S_CAMCTL_IX) 570#define G_CAMCTL_IX(x) _DD_GETVALUE(x,S_CAMCTL_IX,M_CAMCTL_IX) 571 572#define M_CAMCTL_CB _DD_MAKEMASK1(31) /* CAMBusy */ 573 574/* ECTL: Ethernet Control Register (0x42C, R/W) */ 575 576#define M_ECTL_EE _DD_MAKEMASK1(0) /* EMACEnable */ 577#define M_ECTL_ED _DD_MAKEMASK1(1) /* EMACDisable */ 578#define M_ECTL_ES _DD_MAKEMASK1(2) /* EMACSoftReset */ 579#define M_ECTL_EP _DD_MAKEMASK1(3) /* ExtPHYSelect */ 580 581/* TCTL: Transmit Control Register (0x430, R/W) */ 582 583#define M_TCTL_FD _DD_MAKEMASK1(0) /* FullDuplex */ 584#define M_TCTL_FM _DD_MAKEMASK1(1) /* FlowMode */ 585#define M_TCTL_SB _DD_MAKEMASK1(2) /* SingleBackoffEn */ 586#define M_TCTL_SS _DD_MAKEMASK1(3) /* SmSlotTime */ 587 588/* MIBCTL: MIB Control Register (0x438, R/W) */ 589 590#define M_MIBCTL_RO _DD_MAKEMASK1(0) /* RO */ 591 592 593/* DMA Control Registers */ 594 595/* XCTL: Transmit Channel Control Register (0x200, R/W) */ 596 597#define M_XCTL_XE _DD_MAKEMASK1(0) /* XmtEn */ 598#define M_XCTL_SE _DD_MAKEMASK1(1) /* SuspEn */ 599#define M_XCTL_LE _DD_MAKEMASK1(2) /* LoopbackEn */ 600#define M_XCTL_FP _DD_MAKEMASK1(3) /* FairPriority */ 601 602/* XADDR: Transmit Descriptor Table Address Register (0x204, R/W) */ 603 604#define S_XADDR_BA 12 /* BaseAddr */ 605#define M_XADDR_BA _DD_MAKEMASK(20,S_XADDR_BA) 606#define V_XADDR_BA(x) _DD_MAKEVALUE(x,S_XADDR_BA) 607#define G_XADDR_BA(x) _DD_GETVALUE(x,S_XADDR_BA,M_XADDR_BA) 608 609/* XPTR: Transmit Descriptor Table Pointer Register (0x208, R/W) */ 610 611#define S_XPTR_LD 0 /* LastDscr */ 612#define M_XPTR_LD _DD_MAKEMASK(12,S_XPTR_LD) 613#define V_XPTR_LD(x) _DD_MAKEVALUE(x,S_XPTR_LD) 614#define G_XPTR_LD(x) _DD_GETVALUE(x,S_XPTR_LD,M_XPTR_LD) 615 616/* XSTAT: Transmit Channel Status Register (0x20C, RO) */ 617 618#define S_XSTAT_CD 0 /* CurrDscr */ 619#define M_XSTAT_CD _DD_MAKEMASK(12,S_XSTAT_CD) 620#define V_XSTAT_CD(x) _DD_MAKEVALUE(x,S_XSTAT_CD) 621#define G_XSTAT_CD(x) _DD_GETVALUE(x,S_XSTAT_CD,M_XSTAT_CD) 622 623#define S_XSTAT_XS 12 /* XmtState */ 624#define M_XSTAT_XS _DD_MAKEMASK(4,S_XSTAT_XS) 625#define V_XSTAT_XS(x) _DD_MAKEVALUE(x,S_XSTAT_XS) 626#define G_XSTAT_XS(x) _DD_GETVALUE(x,S_XSTAT_XS,M_XSTAT_XS) 627#define K_XS_DISABLED 0x0 628#define K_XS_ACTIVE 0x1 629#define K_XS_IDLE_WAIT 0x2 630#define K_XS_STOPPED 0x3 631#define K_XS_SUSPEND_PENDING 0x4 632 633#define S_XSTAT_XE 16 /* XmtErr */ 634#define M_XSTAT_XE _DD_MAKEMASK(4,S_XSTAT_XE) 635#define V_XSTAT_XE(x) _DD_MAKEVALUE(x,S_XSTAT_XE) 636#define G_XSTAT_XE(x) _DD_GETVALUE(x,S_XSTAT_XE,M_XSTAT_XE) 637#define K_XE_NONE 0x0 638#define K_XE_DSCR_PROTOCOL 0x1 639#define K_XE_FIFO_UNDERRUN 0x2 640#define K_XE_DATA_TRANSFER 0x3 641#define K_XE_DSCR_READ 0x4 642 643/* RCTL: Receive Channel Control Register (0x210, R/W) */ 644 645#define M_RCTL_RE _DD_MAKEMASK1(0) /* RcvEn */ 646 647#define S_RCTL_RO 1 /* RcvOffset */ 648#define M_RCTL_RO _DD_MAKEMASK(7,S_RCTL_RO) 649#define V_RCTL_RO(x) _DD_MAKEVALUE(x,S_RCTL_RO) 650#define G_RCTL_RO(x) _DD_GETVALUE(x,S_RCTL_RO,M_RCTL_RO) 651 652#define M_RCTL_FM _DD_MAKEMASK1(8) /* FIFOMode */ 653 654/* RADDR: Receive Descriptor Table Address Register (0x214, R/W) */ 655 656#define S_RADDR_BA 12 /* BaseAddr */ 657#define M_RADDR_BA _DD_MAKEMASK(20,S_RADDR_BA) 658#define V_RADDR_BA(x) _DD_MAKEVALUE(x,S_RADDR_BA) 659#define G_RADDR_BA(x) _DD_GETVALUE(x,S_RADDR_BA,M_RADDR_BA) 660 661/* RPTR: Receive Descriptor Table Pointer Register (0x218, R/W) */ 662 663#define S_RPTR_LD 0 /* LastDscr */ 664#define M_RPTR_LD _DD_MAKEMASK(12,S_RPTR_LD) 665#define V_RPTR_LD(x) _DD_MAKEVALUE(x,S_RPTR_LD) 666#define G_RPTR_LD(x) _DD_GETVALUE(x,S_RPTR_LD,M_RPTR_LD) 667 668/* RSTAT: Receive Channel Status Register (0x21C, RO) */ 669 670#define S_RSTAT_CD 0 /* CurrDscr */ 671#define M_RSTAT_CD _DD_MAKEMASK(12,S_RSTAT_CD) 672#define V_RSTAT_CD(x) _DD_MAKEVALUE(x,S_RSTAT_CD) 673#define G_RSTAT_CD(x) _DD_GETVALUE(x,S_RSTAT_CD,M_RSTAT_CD) 674 675#define S_RSTAT_RS 12 /* RcvState */ 676#define M_RSTAT_RS _DD_MAKEMASK(4,S_RSTAT_RS) 677#define V_RSTAT_RS(x) _DD_MAKEVALUE(x,S_RSTAT_RS) 678#define G_RSTAT_RS(x) _DD_GETVALUE(x,S_RSTAT_RS,M_RSTAT_RS) 679#define K_RS_DISABLED 0x0 680#define K_RS_ACTIVE 0x1 681#define K_RS_IDLE_WAIT 0x2 682#define K_RS_STOPPED 0x3 683 684#define S_RSTAT_RE 16 /* RcvErr */ 685#define M_RSTAT_RE _DD_MAKEMASK(4,S_RSTAT_RE) 686#define V_RSTAT_RE(x) _DD_MAKEVALUE(x,S_RSTAT_RE) 687#define G_RSTAT_RE(x) _DD_GETVALUE(x,S_RSTAT_RE,M_RSTAT_RE) 688#define K_RE_NONE 0x0 689#define K_RE_DSCR_PROTOCOL 0x1 690#define K_RE_FIFO_OVERFLOW 0x2 691#define K_RE_DATA_TRANSFER 0x3 692#define K_RE_DSCR_READ 0x4 693 694 695/* DMA Descriptor Structure (Table 66) */ 696 697/* Word 0: Flags and Count */ 698 699#define S_DSCR0_BC 0 /* BufCount */ 700#define M_DSCR0_BC _DD_MAKEMASK(13,S_DSCR0_BC) 701#define V_DSCR0_BC(x) _DD_MAKEVALUE(x,S_DSCR0_BC) 702#define G_DSCR0_BC(x) _DD_GETVALUE(x,S_DSCR0_BC,M_DSCR0_BC) 703 704#define S_DSCR0_FL 20 /* Flags */ 705#define M_DSCR0_FL _DD_MAKEMASK(8,S_DSCR0_FL) 706#define V_DSCR0_FL(x) _DD_MAKEVALUE(x,S_DSCR0_FL) 707#define G_DSCR0_FL(x) _DD_GETVALUE(x,S_DSCR0_FL,M_DSCR0_FL) 708 709#define M_DSCR0_ET _DD_MAKEMASK1(28) /* EOT */ 710#define M_DSCR0_IC _DD_MAKEMASK1(29) /* IOC */ 711#define M_DSCR0_EF _DD_MAKEMASK1(30) /* EOF */ 712#define M_DSCR0_SF _DD_MAKEMASK1(31) /* SOF */ 713 714/* Word 1: Data Buffer Pointer */ 715 716#define S_DSCR1_DB 0 /* DataBufPtr */ 717#define M_DSCR1_DB _DD_MAKEMASK(32, S_DSCR1_DB) 718#define V_DSCR1_DB(x) _DD_MAKEVALUE(x,S_DSCR1_DB) 719#define G_DSCR1_DB(x) _DD_GETVALUE(x,S_DSCR1_DB,M_DSCR1_DB) 720 721 722/* DMA Receive Headers (Table 67) */ 723 724#define S_RCVHDR0_CD 0 /* FrameLen (!) */ 725#define M_RCVHDR0_CD _DD_MAKEMASK(16,S_RCVHDR0_CD) 726#define V_RCVHDR0_CD(x) _DD_MAKEVALUE(x,S_RCVHDR0_CD) 727#define G_RCVHDR0_CD(x) _DD_GETVALUE(x,S_RCVHDR0_CD,M_RCVHDR0_CD) 728 729#define S_RCVHDR0_DC 24 /* DescrCnt */ 730#define M_RCVHDR0_DC _DD_MAKEMASK(4,S_RCVHDR0_DC) 731#define V_RCVHDR0_DC(x) _DD_MAKEVALUE(x,S_RCVHDR0_DC) 732#define G_RCVHDR0_DC(x) _DD_GETVALUE(x,S_RCVHDR0_DC,M_RCVHDR0_DC) 733 734/* The following flags are documented for the 4710 core but not for the 4401 */ 735#define M_RCVHDR0_L _DD_MAKEMASK1(27) /* Last */ 736#define M_RCVHDR0_F _DD_MAKEMASK1(26) /* First */ 737#define M_RCVHDR0_W _DD_MAKEMASK1(25) /* Wrap */ 738#define M_RCVHDR0_MISS _DD_MAKEMASK1(23) /* Miss */ 739#define M_RCVHDR0_BRDCAST _DD_MAKEMASK1(22) /* Broadcast */ 740#define M_RCVHDR0_MULT _DD_MAKEMASK1(21) /* Multicast */ 741#define M_RCVHDR0_LG _DD_MAKEMASK1(20) /* Large */ 742#define M_RCVHDR0_NO _DD_MAKEMASK1(19) /* NonOctet Aligned */ 743#define M_RCVHDR0_RXER _DD_MAKEMASK1(18) /* Symbol Error */ 744#define M_RCVHDR0_CRC _DD_MAKEMASK1(17) /* CRC */ 745#define M_RCVHDR0_OV _DD_MAKEMASK1(16) /* Overflow */ 746#define M_RCVHDR0_ERRORS (M_RCVHDR0_NO | M_RCVHDR0_RXER | M_RCVHDR0_CRC \ 747 | M_RCVHDR0_OV) 748 749 750/* Offsets of MIB counters in Statistics Block (Table 161) 751 Registers are 16 bits except as noted. */ 752 753#define TX_GD_OCTETS 0x500 /* 32 bits */ 754#define TX_GD_PKTS 0x504 755#define TX_ALL_OCTETS 0x508 /* 32 bits */ 756#define TX_ALL_PKTS 0x50C 757#define TX_BRDCAST 0x510 758#define TX_MULT 0x514 759#define TX_64 0x518 760#define TX_65_127 0x51C 761#define TX_128_255 0x520 762#define TX_256_511 0x524 763#define TX_512_1023 0x528 764#define TX_1024_MAX 0x52C 765#define TX_JAB 0x530 766#define TX_OVR 0x534 767#define TX_FRAG 0x538 768#define TX_UNDERRUN 0x53C 769#define TX_COL 0x540 770#define TX_1_COL 0x544 771#define TX_M_COL 0x548 772#define TX_EX_COL 0x54C 773#define TX_LATE 0x550 774#define TX_DEF 0x554 775#define TX_CRS 0x558 776#define TX_PAUS 0x55C 777 778#define RX_GD_OCTETS 0x580 /* 32 bits */ 779#define RX_GD_PKTS 0x584 780#define RX_ALL_OCTETS 0x588 /* 32 bits */ 781#define RX_ALL_PKTS 0x58C 782#define RX_BRDCAST 0x590 783#define RX_MULT 0x594 784#define RX_64 0x598 785#define RX_65_127 0x59C 786#define RX_128_255 0x5A0 787#define RX_256_511 0x5A4 788#define RX_512_1023 0x5A8 789#define RX_1024_MAX 0x5AC 790#define RX_JAB 0x5B0 791#define RX_OVR 0x5B4 792#define RX_FRAG 0x5B8 793#define RX_DROP 0x5BC 794#define RX_CRC_ALIGN 0x5C0 795#define RX_UND 0x5C4 796#define RX_CRC 0x5C8 797#define RX_ALIGN 0x5CC 798#define RX_SYM 0x5D0 799#define RX_PAUSE 0x5D4 800#define RX_CNTRL 0x5D8 801 802 803/* In the default mapping, the top 4K of the BAR0 window maps into the 804 SPROM. Note that access latency is high and the corresponding code 805 must be prepared to avoid or deal with bus errors caused by PCI 806 timeouts. */ 807 808#define SPROM_BASE 0x1000 809 810#define SPROM_MAC_ADDR 0x4E /* 6 bytes */ 811#define SPROM_PHY_ADDR 90 /* 2 bytes, bits [4:0] (undoc) */ 812 813 814/* Ethernet PHY Registers (see also mii.h) */ 815 816/* PHYINT: Interrupt Register (0x1A, R/W) */ 817 818#define M_PHYINT_IS _DD_MAKEMASK1(0) /* InterruptStatus */ 819#define M_PHYINT_LC _DD_MAKEMASK1(1) /* LinkChangeInt */ 820#define M_PHYINT_SP _DD_MAKEMASK1(2) /* SpeedChangeInt */ 821#define M_PHYINT_DC _DD_MAKEMASK1(3) /* DuplexChangeInt */ 822#define M_PHYINT_MI _DD_MAKEMASK1(8) /* MasterIntMask */ 823#define M_PHYINT_LI _DD_MAKEMASK1(9) /* LinkIntMask */ 824#define M_PHYINT_SI _DD_MAKEMASK1(10) /* SpeedIntMask */ 825#define M_PHYINT_FD _DD_MAKEMASK1(11) /* FullDuplexIntMask */ 826#define M_PHYINT_IE _DD_MAKEMASK1(14) /* InterruptEnable */ 827 828/* PHYAUX2: Auxiliary Mode 2 Register (0x1B, R/W) */ 829 830#define M_PHYAUX2_QP _DD_MAKEMASK1(1) /* QualParallelDet */ 831#define M_PHYAUX2_AL _DD_MAKEMASK1(2) /* ActivityLinkLED */ 832#define M_PHYAUX2_LF _DD_MAKEMASK1(5) /* ActivityLEDForce */ 833#define M_PHYAUX2_TM _DD_MAKEMASK1(6) /* TrafficMeterLED */ 834#define M_PHYAUX2_BE _DD_MAKEMASK1(7) /* Block10BTEcho */ 835#define M_PHYAUX2_HF _DD_MAKEMASK1(9) /* HSTRFIFO */ 836#define M_PHYAUX2_TR _DD_MAKEMASK1(10) /* TokenRing */ 837#define M_PHYAUX2_DC _DD_MAKEMASK1(11) /* 10BTDribbleCorr */ 838 839 840/* PCI Core Registers */ 841 842/* SBXLAT: System Backplane to PCI Translation 0 Register (0x100, R/W) */ 843/* SBXLAT: System Backplane to PCI Translation 1 Register (0x104, R/W) */ 844/* SBXLAT: System Backplane to PCI Translation 2 Register (0x108, R/W) */ 845 846#define S_SBXLAT_AT 0 /* AccessType */ 847#define M_SBXLAT_AT _DD_MAKEMASK(2,S_SBXLAT_AT) 848#define V_SBXLAT_AT(x) _DD_MAKEVALUE(x,S_SBXLAT_AT) 849#define G_SBXLAT_AT(x) _DD_GETVALUE(x,S_SBXLAT_AT,M_SBXLAT_AT) 850#define K_AT_RW 0 851#define K_AT_IO_RW 1 852#define K_AT_CFG0_RW 2 853#define K_AT_CFG1_RW 3 854 855#define M_SBXLAT_PE _DD_MAKEMASK1(2) /* PrefetchEn */ 856#define M_SBXLAT_WB _DD_MAKEMASK1(3) /* WriteBurstEn */ 857 858#define S_SBXLAT_UA 26 /* UpperAddress */ 859#define M_SBXLAT_UA _DD_MAKEMASK(6,S_SBXLAT_UA) 860#define V_SBXLAT_UA(x) _DD_MAKEVALUE(x,S_SBXLAT_UA) 861#define G_SBXLAT_UA(x) _DD_GETVALUE(x,S_SBXLAT_UA,M_SBXLAT_UA) 862 863#endif /* _BCM4400_H_ */ 864