1/*  *********************************************************************
2    *  Broadcom Common Firmware Environment (CFE)
3    *
4    *  Board-specific PCI description		File: mousse_pci.c
5    *
6    *  This file describes the board-specific PCI slots/devices
7    *  and wiring thereof.
8    *
9    *  Author:  Ed Satterthwaite
10    *
11    *********************************************************************
12    *
13    *  Copyright 2004
14    *  Broadcom Corporation. All rights reserved.
15    *
16    *  This software is furnished under license and may be used and
17    *  copied only in accordance with the following terms and
18    *  conditions.  Subject to these conditions, you may download,
19    *  copy, install, use, modify and distribute modified or unmodified
20    *  copies of this software in source and/or binary form.  No title
21    *  or ownership is transferred hereby.
22    *
23    *  1) Any source code used, modified or distributed must reproduce
24    *     and retain this copyright notice and list of conditions
25    *     as they appear in the source file.
26    *
27    *  2) No right is granted to use any trade name, trademark, or
28    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
29    *     name may not be used to endorse or promote products derived
30    *     from this software without the prior written permission of
31    *     Broadcom Corporation.
32    *
33    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
34    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
35    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
36    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
37    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
38    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
39    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
41    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
42    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
43    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
44    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
45    *     THE POSSIBILITY OF SUCH DAMAGE.
46    ********************************************************************* */
47
48#include "lib_types.h"
49
50#include "pcireg.h"
51#include "pcivar.h"
52#include "pci_internal.h"
53
54/* PCI interrupt mapping on the MOUSSE card.  For bus 0, device id 14
55   is implemented as a PCI connector.  The only on-board device has
56   id 13 (dc21143 10/100 NIC), but the design allows an 82371 (south
57   bridge) with id 15, which is not stuffed.
58
59   All interrupts are routed via the MPLD to the mpc8240 as IRQ1 .. IRQ4.
60
61     Slot    IDSEL   DevID   IRQ{1,2,3,4}  shift
62     (HB)     gnd      0       {-,-,-,-}     -  (NC)
63    (21143)   13      13       {1,-,-,-}     0
64      0       14      14       {3,3,3,3}     1  (all ints wired together)
65   [(82371    15      15       {0,-,-,-}     -  (not stuffed)]
66
67   There is also a CPCI connector, with PCI A|C and PCI B|D both directed
68   to IRQ2.  A standard backplane maps IDSEL 31:25 to CPCI logical slots
69   2 to 8:
70             IDSEL   DevID  cPCI Logical Slot  shift
71              31      10         2               1
72              25      25         8               3
73              26      26         7               2
74              27      27         6               1
75              28      28         5               0
76              29      29         4               3
77              30      30         3               2
78*/
79
80/* Return the base shift of a slot or device on the motherboard.
81   This is board specific, for the MOUSSE only. */
82uint8_t
83pci_int_shift_0(pcitag_t tag)
84{
85    int bus, device;
86
87    pci_break_tag(tag, NULL, &bus, &device, NULL);
88    if (bus == 0) {
89	switch (device) {
90	    case 13:  return 0;
91	    case 14:  return 1;   /* arbitrary */
92
93	    /* CPCI backplane */
94	    case 10:  return 1;
95	    case 25:  return 3;
96	    case 26:  return 2;
97	    case 27:  return 1;
98	    case 28:  return 0;
99	    case 29:  return 3;
100	    case 30:  return 2;
101
102	    default:  return 0;   /* for now */
103	    }
104	}
105    else
106	return 0;
107}
108
109/* Return the mapping of a device/function interrupt to an
110   interrupt line (IRQ number). */
111uint8_t
112pci_int_map_0(pcitag_t tag)
113{
114    pcireg_t data;
115    int pin, bus, device;
116
117    data = pci_conf_read(tag, PCI_BPARAM_INTERRUPT_REG);
118    pin = PCI_INTERRUPT_PIN(data);
119    if (pin == 0) {
120	/* No IRQ used. */
121	return 0;
122	}
123
124    pci_break_tag(tag, NULL, &bus, &device, NULL);
125
126    if (bus == 0) {
127	switch (device) {
128	    case 13:  return 1;
129	    case 14:  return 3;
130	    case 15:  return 0;
131
132            /* via cPCI connector */
133	    case 10: case 25: case 26: case 27: case 28: case 29: case 30:
134		return 2;
135
136	    default: return 0;
137	    }
138	}
139    else
140	return 0;
141}
142