1/*  *********************************************************************
2    *  PPC Board Support Package
3    *
4    *  Board-specific initialization		File: MOUSSE_INIT.S
5    *
6    *  This module contains the assembly-language part of the init
7    *  code for this board support package.  The routine
8    *  "board_earlyinit" lives here.
9    *
10    *  This board support package is for the MPC8245 Mousse board
11    *
12    *  Author:  Mitch Lichtenberg
13    *
14    *********************************************************************
15    *
16    *  Copyright 2000,2001,2002,2003
17    *  Broadcom Corporation. All rights reserved.
18    *
19    *  This software is furnished under license and may be used and
20    *  copied only in accordance with the following terms and
21    *  conditions.  Subject to these conditions, you may download,
22    *  copy, install, use, modify and distribute modified or unmodified
23    *  copies of this software in source and/or binary form.  No title
24    *  or ownership is transferred hereby.
25    *
26    *  1) Any source code used, modified or distributed must reproduce
27    *     and retain this copyright notice and list of conditions
28    *     as they appear in the source file.
29    *
30    *  2) No right is granted to use any trade name, trademark, or
31    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
32    *     name may not be used to endorse or promote products derived
33    *     from this software without the prior written permission of
34    *     Broadcom Corporation.
35    *
36    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
37    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
38    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
39    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
40    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
41    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
42    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
44    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
45    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
46    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
47    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
48    *     THE POSSIBILITY OF SUCH DAMAGE.
49    ********************************************************************* */
50
51
52#include "ppcdefs.h"
53#include "ppcmacros.h"
54#include "bsp_config.h"
55#include "mousse.h"
56#include "init_engine.h"
57#include "mpc824x.h"
58
59
60/*  *********************************************************************
61    *  Global Offset Table
62    ********************************************************************* */
63
64#if CFG_RELOC
65BEGIN_GOT()
66GOT_ENTRY(board_draminittab)
67END_GOT()
68#endif
69
70		.text
71
72/*  *********************************************************************
73    *  Macros
74    ********************************************************************* */
75
76#define DRAM_BASE	0
77#define DRAM_SIZE	64	/* megabytes */
78
79
80/*  *********************************************************************
81    *  BOARD_EARLYINIT()
82    *
83    *  Initialize board registers.  This is the earliest
84    *  time the BSP gets control.  This routine cannot assume that
85    *  memory is operational, and therefore all code in this routine
86    *  must run from registers only.  The lr register must not
87    *  be modified, as it contains the return address.
88    *
89    *  This routine will be called from uncached space, before
90    *  the caches are initialized.
91    *
92    *  Among other things, this is where the GPIO registers get
93    *  programmed to make on-board LEDs function, or other startup
94    *  that has to be done before anything will work.
95    *
96    *  Input parameters:
97    *  	   nothing
98    *
99    *  Return value:
100    *  	   nothing
101    ********************************************************************* */
102
103LEAF(board_earlyinit)
104
105
106	blr
107
108END(board_earlyinit)
109
110
111/*  *********************************************************************
112    *  BOARD_DRAM_INIT
113    *
114    *  Initialize DRAM controller.
115    *
116    *  Input parameters:
117    *  	   nothing
118    *
119    *  Return value:
120    *  	   r3 - dram size in megabytes
121    ********************************************************************* */
122
123LEAF(board_dram_init)
124
125	mflr	r29
126
127	/* LOAD_GOT trashes LR, but we saved it above. */
128	LOAD_GOT(GOT_REG)
129	LDADDR(r6,board_draminittab)
130
131	bl	init_engine
132
133	li	r3,DRAM_SIZE
134
135	mtlr	r29
136
137	blr
138
139END(board_dram_init)
140
141
142
143/*  *********************************************************************
144    *  BOARD_SETLEDS(x)
145    *
146    *  Set LEDs for boot-time progress indication.  Not used if
147    *  the board does not have progress LEDs.  This routine
148    *  must not call any other routines.
149    *
150    *  Input parameters:
151    *  	   r3 - LED value (8 bits per character, 4 characters)
152    *
153    *  Return value:
154    *  	   nothing
155    *
156    *  Registers used:
157    *  	   r3,r5,r6
158    ********************************************************************* */
159
160#define WAIT_SERIAL(base,tmp1,tmp2) \
16188: lbz tmp1,5(base) ; \
162   andi. tmp2,tmp1,0x40 ; \
163   bc 12,2,88b
164
165LEAF(board_setleds)
166
167#if CFG_SERIAL_LEDS
168
169	LDCONST(r5, 0xffe08080)
170
171	li	r6, 0x83
172	stb	r6, 3(r5)
173	li	r6, 0x0a
174	stb	r6, 0(r5)
175	li	r6, 0x00
176	stb	r6, 1(r5)
177	li	r6, 0x03
178	stb	r6, 3(r5)
179	li	r6, 0x0b
180	stb	r6, 4(r5)
181
182	WAIT_SERIAL(r5,r6,r0)
183	li	r0,0x5B		/* [ */
184	stb	r0, 0(r5)
185	sync
186
187	rlwinm	r3,r3,8,0,31
188
189	WAIT_SERIAL(r5,r6,r0)
190	stb	r3, 0(r5)
191	sync
192
193	rlwinm	r3,r3,8,0,31
194
195	WAIT_SERIAL(r5,r6,r0)
196	stb	r3, 0(r5)
197	sync
198
199	rlwinm	r3,r3,8,0,31
200
201	WAIT_SERIAL(r5,r6,r0)
202	stb	r3, 0(r5)
203	sync
204
205	rlwinm	r3,r3,8,0,31
206
207	WAIT_SERIAL(r5,r6,r0)
208	stb	r3, 0(r5)
209	sync
210
211	WAIT_SERIAL(r5,r6,r0)
212	li	r0,0x5D		/* ] */
213	stb	r0, 0(r5)
214	sync
215#endif
216
217
218	blr
219
220END(board_setleds)
221
222
223
224/*  *********************************************************************
225    *  BOARD_OUTNUM
226    *
227    *  Write a number to the serial port.
228    *
229    *  Input parameters:
230    *  	   r3 - number to write
231    *
232    *  Return value:
233    *  	   nothing
234    *
235    *  Registers used:
236    *      r5,r6,r4
237    ********************************************************************* */
238
239LEAF(board_outnum)
240
241	LDCONST(r5, 0xffe08080)
242
243	WAIT_SERIAL(r5,r6,r0)
244	li	r0,0x5B		/* [ */
245	stb	r0, 0(r5)
246	sync
247
248	rlwinm	r3,r3,4,0,31
249	andi.   r4,r3,0x0F
250	addi	r4,r4,0x30
251	cmpwi	r4,0x39
252	ble	1f
253	addi	r4,r4,(0x41-0x3A)
2541:	WAIT_SERIAL(r5,r6,r0)
255	stb	r4,0(r5)
256	sync
257
258	rlwinm	r3,r3,4,0,31
259	andi.   r4,r3,0x0F
260	addi	r4,r4,0x30
261	cmpwi	r4,0x39
262	ble	1f
263	addi	r4,r4,(0x41-0x3A)
2641:	WAIT_SERIAL(r5,r6,r0)
265	stb	r4,0(r5)
266	sync
267
268	rlwinm	r3,r3,4,0,31
269	andi.   r4,r3,0x0F
270	addi	r4,r4,0x30
271	cmpwi	r4,0x39
272	ble	1f
273	addi	r4,r4,(0x41-0x3A)
2741:	WAIT_SERIAL(r5,r6,r0)
275	stb	r4,0(r5)
276	sync
277
278	rlwinm	r3,r3,4,0,31
279	andi.   r4,r3,0x0F
280	addi	r4,r4,0x30
281	cmpwi	r4,0x39
282	ble	1f
283	addi	r4,r4,(0x41-0x3A)
2841:	WAIT_SERIAL(r5,r6,r0)
285	stb	r4,0(r5)
286	sync
287
288	rlwinm	r3,r3,4,0,31
289	andi.   r4,r3,0x0F
290	addi	r4,r4,0x30
291	cmpwi	r4,0x39
292	ble	1f
293	addi	r4,r4,(0x41-0x3A)
2941:	WAIT_SERIAL(r5,r6,r0)
295	stb	r4,0(r5)
296	sync
297
298	rlwinm	r3,r3,4,0,31
299	andi.   r4,r3,0x0F
300	addi	r4,r4,0x30
301	cmpwi	r4,0x39
302	ble	1f
303	addi	r4,r4,(0x41-0x3A)
3041:	WAIT_SERIAL(r5,r6,r0)
305	stb	r4,0(r5)
306	sync
307
308	rlwinm	r3,r3,4,0,31
309	andi.   r4,r3,0x0F
310	addi	r4,r4,0x30
311	cmpwi	r4,0x39
312	ble	1f
313	addi	r4,r4,(0x41-0x3A)
3141:	WAIT_SERIAL(r5,r6,r0)
315	stb	r4,0(r5)
316	sync
317
318	rlwinm	r3,r3,4,0,31
319	andi.   r4,r3,0x0F
320	addi	r4,r4,0x30
321	cmpwi	r4,0x39
322	ble	1f
323	addi	r4,r4,(0x41-0x3A)
3241:	WAIT_SERIAL(r5,r6,r0)
325	stb	r4,0(r5)
326	sync
327
328	WAIT_SERIAL(r5,r6,r0)
329	li	r0,0x5D		/* ] */
330	stb	r0, 0(r5)
331	sync
332
333	blr
334END(board_outnum)
335
336
337
338/*  *********************************************************************
339    *  Initialization table for memory controller.
340    *
341    *  This table is processsed by the "init_engine" to
342    *  orchestrate writes to PCI space and CPU MSRs.
343    ********************************************************************* */
344
345#ifndef CFG_DRAM_ECC
346#define CFG_DRAM_ECC	0
347#endif
348
349#if CFG_DRAM_ECC
350#define MCCR1_ECC_BITS M_MCCR1_PCKEN
351#define MCCR2_ECC_BITS (M_MCCR2_WRPARCHK | M_MCCR2_INLPARNOECC | M_MCCR2_RMWPAR)
352#define MCCR3_ECC_BITS 0
353#define MCCR4_ECC_BITS M_MC4_BUFTYPE0
354#else
355#define MCCR1_ECC_BITS 0
356#define MCCR2_ECC_BITS 0
357#define MCCR3_ECC_BITS 0
358#define MCCR4_ECC_BITS M_MCCR4_BUFTYPE1
359#endif
360
361#define MC_MCCR_BSTOPRE 0x79
362
363
364board_draminittab:
365
366
367	/*
368	 * Initialize memory controller.
369	 */
370
371	IET_PCI32(MPC_MCCR1,V_MCCR1_ROMNAL(8) | V_MCCR1_ROMFAL(8) | M_MCCR1_SREN |
372	        MCCR1_ECC_BITS |
373		V_MCCR1_BANKnROW(0,K_MCCR1_ROW10)  |
374		V_MCCR1_BANKnROW(1,K_MCCR1_ROW10)  |
375		V_MCCR1_BANKnROW(2,K_MCCR1_ROW10)  |
376		V_MCCR1_BANKnROW(3,K_MCCR1_ROW10)  |
377		V_MCCR1_BANKnROW(4,K_MCCR1_ROW10)  |
378		V_MCCR1_BANKnROW(5,K_MCCR1_ROW10)  |
379		V_MCCR1_BANKnROW(6,K_MCCR1_ROW10)  |
380		V_MCCR1_BANKnROW(7,K_MCCR1_ROW10))
381
382
383	IET_PCI32(MPC_MCCR2,V_MCCR2_TSWAIT(0) | V_MCCR2_ASRISE(8) | V_MCCR2_ASFALL(4) |
384		MCCR2_ECC_BITS |
385		V_MCCR2_REFINT(0xf5))
386
387	IET_PCI32(MPC_MCCR3,V_MCCR3_BSTOPRE(((MC_MCCR_BSTOPRE >> 4) & 0x0F)) |
388		V_MCCR3_REFREC(8) |
389                MCCR3_ECC_BITS |
390		V_MCCR3_RDLAT(4+CFG_DRAM_ECC))
391
392	IET_PCI32(MPC_MCCR4,V_MCCR4_PRETOACT(3) | V_MCCR4_ACTOPRE(5) |
393		V_MCCR4_ACTORW(3) |
394                MCCR4_ECC_BITS |
395		V_MCCR4_BSTOPRE01((MC_MCCR_BSTOPRE >> 8) & 3) |
396		V_MCCR4_SDMODE(0x32) |
397		V_MCCR4_BSTOPRE69(MC_MCCR_BSTOPRE & 0x0F))
398#if CFG_DRAM_ECC
399	IET_PCI32(MPC_ERREN1,xxx)
400#endif
401	IET_PCI32(MPC_MSAR1,0xC0804000)
402	IET_PCI32(MPC_MSAR2,0xc0804000)
403
404	IET_PCI32(MPC_XMSAR1,0x00000000)
405	IET_PCI32(MPC_XMSAR2,0x01010101)
406
407	IET_PCI32(MPC_MEAR1,0xffbf7f3f)
408	IET_PCI32(MPC_MEAR2,0xffbf7f3f)
409
410	IET_PCI32(MPC_XMEAR1,0x00000000)
411	IET_PCI32(MPC_XMEAR2,0x01010101)
412
413	IET_PCI8(MPC_ODCR,0x7f)
414
415	IET_PCI8(MPC_MBEN,0x03)
416
417	IET_PCI8(MPC_PGMODE,0x32)
418
419	IET_DELAY(0x10)
420	IET_PCI32X(MPC_MCCR1,0xFFFFFFFF,M_MCCR1_MEMGO)
421	IET_DELAY(0x4000)
422
423	/*
424	 * Done with memory controller.
425	 */
426
427	IET_PCI32(MPC_EUMBBAR,A_MOUSSE_EUMBBAR_VAL)
428
429
430	/*
431	 * setup BATs
432	 */
433
434	/* BAT 0 : SDRAM */
435	IET_IBAT(0,(DRAM_BASE | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
436		   (DRAM_BASE | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_MEMCOHERENCE))
437	IET_DBAT(0,(DRAM_BASE | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
438		   (DRAM_BASE | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_MEMCOHERENCE))
439
440        /* BAT 1 : DOC */
441	IET_IBAT(1,(0x70000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
442		   (0x70000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
443	IET_DBAT(1,(0x70000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
444		   (0x70000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
445
446        /* BAT 2 : PCI */
447	IET_IBAT(2,(0x80000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
448		   (0x80000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
449	IET_DBAT(2,(0x80000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
450		   (0x80000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
451
452        /* BAT 3 : EUMBAR, FLASH, PLD */
453	IET_IBAT(3,(0xF0000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
454		   (0xF0000000 | V_BATL_PP(K_BATL_PP_RDWR) | 0/*M_BATL_INHIBIT*/))
455	IET_DBAT(3,(0xF0000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
456		   (0xF0000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
457
458	IET_ENABBATS()
459
460	IET_SPRX(SPR_HID0,0xffffffff,(M_HID0_DCE|M_HID0_DCFI))
461	IET_SPRX(SPR_HID0,~M_HID0_DCFI,M_HID0_DCE)
462
463	IET_EOT()
464
465
466/*  *********************************************************************
467    *  Misc functions
468    ********************************************************************* */
469
470
471	.globl read_hid0
472read_hid0:
473
474	mfspr r3,SPR_HID0
475	blr
476
477	.globl write_hid0
478write_hid0:
479
480	isync
481	mtspr SPR_HID0,r3
482	sync
483	isync
484	eieio
485	blr
486
487	.globl read_hid1
488read_hid1:
489
490	mfspr r3,SPR_HID1
491	blr
492
493	.globl read_msr
494read_msr:
495
496	mfmsr r3
497	blr
498
499	.globl write_msr
500write_msr:
501
502	isync
503	mtmsr r3
504	sync
505	isync
506	eieio
507	blr
508
509	.globl read_bats
510read_bats:
511	mfspr r0,SPR_IBAT0U
512	stw    r0,0(r3)
513	mfspr r0,SPR_IBAT0L
514	stw    r0,4(r3)
515	mfspr r0,SPR_IBAT1U
516	stw    r0,8(r3)
517	mfspr r0,SPR_IBAT1L
518	stw    r0,12(r3)
519	mfspr r0,SPR_IBAT2U
520	stw    r0,16(r3)
521	mfspr r0,SPR_IBAT2L
522	stw    r0,20(r3)
523	mfspr r0,SPR_IBAT3U
524	stw    r0,24(r3)
525	mfspr r0,SPR_IBAT3L
526	stw    r0,28(r3)
527
528	mfspr r0,SPR_DBAT0U
529	stw    r0,32(r3)
530	mfspr r0,SPR_DBAT0L
531	stw    r0,36(r3)
532	mfspr r0,SPR_DBAT1U
533	stw    r0,40(r3)
534	mfspr r0,SPR_DBAT1L
535	stw    r0,44(r3)
536	mfspr r0,SPR_DBAT2U
537	stw    r0,48(r3)
538	mfspr r0,SPR_DBAT2L
539	stw    r0,52(r3)
540	mfspr r0,SPR_DBAT3U
541	stw    r0,56(r3)
542	mfspr r0,SPR_DBAT3L
543	stw    r0,60(r3)
544
545	blr
546
547
548