1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Memory Controller constants File: sb1250_mc.h 5 * 6 * This module contains constants and macros useful for 7 * programming the memory controller. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2005 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49#ifndef _SB1250_MC_H 50#define _SB1250_MC_H 51 52#include "sb1250_defs.h" 53 54/* 55 * Memory Channel Config Register (table 6-14) 56 */ 57 58#define S_MC_RESERVED0 0 59#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0) 60 61#define S_MC_CHANNEL_SEL 8 62#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL) 63#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL) 64#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL) 65 66#define S_MC_BANK0_MAP 16 67#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP) 68#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP) 69#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP) 70 71#define K_MC_BANK0_MAP_DEFAULT 0x00 72#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) 73 74#define S_MC_BANK1_MAP 20 75#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP) 76#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP) 77#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP) 78 79#define K_MC_BANK1_MAP_DEFAULT 0x08 80#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) 81 82#define S_MC_BANK2_MAP 24 83#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP) 84#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP) 85#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP) 86 87#define K_MC_BANK2_MAP_DEFAULT 0x09 88#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) 89 90#define S_MC_BANK3_MAP 28 91#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP) 92#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP) 93#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP) 94 95#define K_MC_BANK3_MAP_DEFAULT 0x0C 96#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) 97 98#define M_MC_RESERVED1 _SB_MAKEMASK(8,32) 99 100#define S_MC_QUEUE_SIZE 40 101#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE) 102#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE) 103#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE) 104#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) 105 106#define S_MC_AGE_LIMIT 44 107#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT) 108#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT) 109#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT) 110#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) 111 112#define S_MC_WR_LIMIT 48 113#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT) 114#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT) 115#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT) 116#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) 117 118#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) 119 120#define M_MC_RESERVED2 _SB_MAKEMASK(3,53) 121 122#define S_MC_CS_MODE 56 123#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE) 124#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE) 125#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE) 126 127#define K_MC_CS_MODE_MSB_CS 0 128#define K_MC_CS_MODE_INTLV_CS 15 129#define K_MC_CS_MODE_MIXED_CS_10 12 130#define K_MC_CS_MODE_MIXED_CS_30 6 131#define K_MC_CS_MODE_MIXED_CS_32 3 132 133#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) 134#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) 135#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10) 136#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30) 137#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32) 138 139#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) 140#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) 141#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) 142#define M_MC_DEBUG _SB_MAKEMASK1(63) 143 144#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \ 145 V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \ 146 V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \ 147 M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT 148 149 150/* 151 * Memory clock config register (Table 6-15) 152 * 153 * Note: this field has been updated to be consistent with the errata to 0.2 154 */ 155 156#define S_MC_CLK_RATIO 0 157#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO) 158#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO) 159#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO) 160 161#define K_MC_CLK_RATIO_2X 4 162#define K_MC_CLK_RATIO_25X 5 163#define K_MC_CLK_RATIO_3X 6 164#define K_MC_CLK_RATIO_35X 7 165#define K_MC_CLK_RATIO_4X 8 166#define K_MC_CLK_RATIO_45X 9 167 168#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X) 169#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) 170#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) 171#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) 172#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) 173#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) 174#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X 175 176#define S_MC_REF_RATE 8 177#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE) 178#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE) 179#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE) 180 181#define K_MC_REF_RATE_100MHz 0x62 182#define K_MC_REF_RATE_133MHz 0x81 183#define K_MC_REF_RATE_200MHz 0xC4 184 185#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) 186#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) 187#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) 188#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz 189 190#define S_MC_CLOCK_DRIVE 16 191#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE) 192#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE) 193#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE) 194#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) 195 196#define S_MC_DATA_DRIVE 20 197#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE) 198#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE) 199#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE) 200#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) 201 202#define S_MC_ADDR_DRIVE 24 203#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE) 204#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE) 205#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE) 206#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) 207 208#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 209#define M_MC_REF_DISABLE _SB_MAKEMASK1(30) 210#endif /* 1250 PASS3 || 112x PASS1 */ 211 212#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) 213 214#define S_MC_DQI_SKEW 32 215#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW) 216#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW) 217#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW) 218#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) 219 220#define S_MC_DQO_SKEW 40 221#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW) 222#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW) 223#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW) 224#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) 225 226#define S_MC_ADDR_SKEW 48 227#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW) 228#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW) 229#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW) 230#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) 231 232#define S_MC_DLL_DEFAULT 56 233#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT) 234#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT) 235#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT) 236#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) 237 238#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ 239 V_MC_ADDR_SKEW_DEFAULT | \ 240 V_MC_DQO_SKEW_DEFAULT | \ 241 V_MC_DQI_SKEW_DEFAULT | \ 242 V_MC_ADDR_DRIVE_DEFAULT | \ 243 V_MC_DATA_DRIVE_DEFAULT | \ 244 V_MC_CLOCK_DRIVE_DEFAULT | \ 245 V_MC_REF_RATE_DEFAULT 246 247 248 249/* 250 * DRAM Command Register (Table 6-13) 251 */ 252 253#define S_MC_COMMAND 0 254#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND) 255#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND) 256#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND) 257 258#define K_MC_COMMAND_EMRS 0 259#define K_MC_COMMAND_MRS 1 260#define K_MC_COMMAND_PRE 2 261#define K_MC_COMMAND_AR 3 262#define K_MC_COMMAND_SETRFSH 4 263#define K_MC_COMMAND_CLRRFSH 5 264#define K_MC_COMMAND_SETPWRDN 6 265#define K_MC_COMMAND_CLRPWRDN 7 266 267#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) 268#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) 269#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) 270#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) 271#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) 272#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) 273#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) 274#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) 275 276#define M_MC_CS0 _SB_MAKEMASK1(4) 277#define M_MC_CS1 _SB_MAKEMASK1(5) 278#define M_MC_CS2 _SB_MAKEMASK1(6) 279#define M_MC_CS3 _SB_MAKEMASK1(7) 280 281/* 282 * DRAM Mode Register (Table 6-14) 283 */ 284 285#define S_MC_EMODE 0 286#define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE) 287#define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE) 288#define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE) 289#define V_MC_EMODE_DEFAULT V_MC_EMODE(0) 290 291#define S_MC_MODE 16 292#define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE) 293#define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE) 294#define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE) 295#define V_MC_MODE_DEFAULT V_MC_MODE(0x22) 296 297#define S_MC_DRAM_TYPE 32 298#define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE) 299#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE) 300#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE) 301 302#define K_MC_DRAM_TYPE_JEDEC 0 303#define K_MC_DRAM_TYPE_FCRAM 1 304#define K_MC_DRAM_TYPE_SGRAM 2 305 306#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) 307#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) 308#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) 309 310#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35) 311 312#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 313#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) 314#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37) 315#endif /* 1250 PASS3 || 112x PASS1 */ 316 317 318 319/* 320 * SDRAM Timing Register (Table 6-15) 321 */ 322 323#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60) 324#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61) 325#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) 326 327#define S_MC_tFIFO 56 328#define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO) 329#define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO) 330#define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO) 331#define K_MC_tFIFO_DEFAULT 1 332#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) 333 334#define S_MC_tRFC 52 335#define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC) 336#define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC) 337#define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC) 338#define K_MC_tRFC_DEFAULT 12 339#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) 340 341#if SIBYTE_HDR_FEATURE(1250, PASS3) 342#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */ 343#endif 344 345#define S_MC_tCwCr 40 346#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr) 347#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr) 348#define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr) 349#define K_MC_tCwCr_DEFAULT 4 350#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) 351 352#define S_MC_tRCr 28 353#define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr) 354#define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr) 355#define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr) 356#define K_MC_tRCr_DEFAULT 9 357#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) 358 359#define S_MC_tRCw 24 360#define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw) 361#define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw) 362#define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw) 363#define K_MC_tRCw_DEFAULT 10 364#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) 365 366#define S_MC_tRRD 20 367#define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD) 368#define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD) 369#define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD) 370#define K_MC_tRRD_DEFAULT 2 371#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) 372 373#define S_MC_tRP 16 374#define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP) 375#define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP) 376#define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP) 377#define K_MC_tRP_DEFAULT 4 378#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) 379 380#define S_MC_tCwD 8 381#define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD) 382#define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD) 383#define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD) 384#define K_MC_tCwD_DEFAULT 1 385#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) 386 387#define M_tCrDh _SB_MAKEMASK1(7) 388#define M_MC_tCrDh M_tCrDh 389 390#define S_MC_tCrD 4 391#define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD) 392#define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD) 393#define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD) 394#define K_MC_tCrD_DEFAULT 2 395#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) 396 397#define S_MC_tRCD 0 398#define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD) 399#define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD) 400#define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD) 401#define K_MC_tRCD_DEFAULT 3 402#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) 403 404#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ 405 V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ 406 V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ 407 V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ 408 V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ 409 V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ 410 V_MC_tRP(K_MC_tRP_DEFAULT) | \ 411 V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ 412 V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ 413 V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ 414 M_MC_r2rIDLE_TWOCYCLES 415 416/* 417 * Errata says these are not the default 418 * M_MC_w2rIDLE_TWOCYCLES | \ 419 * M_MC_r2wIDLE_TWOCYCLES | \ 420 */ 421 422 423/* 424 * Chip Select Start Address Register (Table 6-17) 425 */ 426 427#define S_MC_CS0_START 0 428#define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START) 429#define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START) 430#define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START) 431 432#define S_MC_CS1_START 16 433#define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START) 434#define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START) 435#define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START) 436 437#define S_MC_CS2_START 32 438#define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START) 439#define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START) 440#define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START) 441 442#define S_MC_CS3_START 48 443#define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START) 444#define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START) 445#define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START) 446 447/* 448 * Chip Select End Address Register (Table 6-18) 449 */ 450 451#define S_MC_CS0_END 0 452#define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END) 453#define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END) 454#define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END) 455 456#define S_MC_CS1_END 16 457#define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END) 458#define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END) 459#define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END) 460 461#define S_MC_CS2_END 32 462#define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END) 463#define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END) 464#define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END) 465 466#define S_MC_CS3_END 48 467#define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END) 468#define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END) 469#define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END) 470 471/* 472 * Chip Select Interleave Register (Table 6-19) 473 */ 474 475#define S_MC_INTLV_RESERVED 0 476#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED) 477 478#define S_MC_INTERLEAVE 7 479#define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE) 480#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE) 481 482#define S_MC_INTLV_MBZ 25 483#define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ) 484 485/* 486 * Row Address Bits Register (Table 6-20) 487 */ 488 489#define S_MC_RAS_RESERVED 0 490#define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED) 491 492#define S_MC_RAS_SELECT 12 493#define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT) 494#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT) 495 496#define S_MC_RAS_MBZ 37 497#define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ) 498 499 500/* 501 * Column Address Bits Register (Table 6-21) 502 */ 503 504#define S_MC_CAS_RESERVED 0 505#define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED) 506 507#define S_MC_CAS_SELECT 5 508#define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT) 509#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT) 510 511#define S_MC_CAS_MBZ 23 512#define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ) 513 514 515/* 516 * Bank Address Address Bits Register (Table 6-22) 517 */ 518 519#define S_MC_BA_RESERVED 0 520#define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED) 521 522#define S_MC_BA_SELECT 5 523#define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT) 524#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT) 525 526#define S_MC_BA_MBZ 25 527#define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ) 528 529/* 530 * Chip Select Attribute Register (Table 6-23) 531 */ 532 533#define K_MC_CS_ATTR_CLOSED 0 534#define K_MC_CS_ATTR_CASCHECK 1 535#define K_MC_CS_ATTR_HINT 2 536#define K_MC_CS_ATTR_OPEN 3 537 538#define S_MC_CS0_PAGE 0 539#define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE) 540#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE) 541#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE) 542 543#define S_MC_CS1_PAGE 16 544#define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE) 545#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE) 546#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE) 547 548#define S_MC_CS2_PAGE 32 549#define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE) 550#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE) 551#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE) 552 553#define S_MC_CS3_PAGE 48 554#define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE) 555#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE) 556#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE) 557 558/* 559 * ECC Test ECC Register (Table 6-25) 560 */ 561 562#define S_MC_ECC_INVERT 0 563#define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT) 564 565 566#endif 567