1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * JTAG Constants and Macros File: sb1250_jtag.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the System Control and Debug module on the 1250. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48#ifndef _SB1250_JTAG_H 49#define _SB1250_JTAG_H 50 51#include "sb1250_defs.h" 52 53#define SB1250_IDCODE_VAL 0x112502a1 54#define SIBYTE_IMPCODE_VAL 0x21404001 55#define SIBYTE_IMPCODE_VAL_OLD 0x20814001 56 57/* 58 * JTAG Memory region 59 */ 60 61#define K_SCD_JTAG_MEMBASE 0x0010000000 62#define K_SCD_JTAG_MEMSIZE 0x0000020000 63#define K_SCD_JTAG_MEMTOP (K_SCD_JTAG_MEMBASE+K_SCD_JTAG_MEMSIZE) 64 65 66/* 67 * JTAG Instruction Register values 68 */ 69 70#define SIBYTE_EXTEST 0x00 71#define SIBYTE_IDCODE 0x01 72#define SIBYTE_IMPCODE 0x03 73#define SIBYTE_ADDRESS 0x08 74#define SIBYTE_DATA 0x09 75#define SIBYTE_CONTROL 0x0A 76#define SIBYTE_EJTAGALL 0x0B 77#define SIBYTE_EJTAGBOOT 0x0C 78#define SIBYTE_NORMALBOOT 0x0D 79#define SIBYTE_SYSCTRL 0x20 80#define SIBYTE_TRACE 0x21 81#define SIBYTE_PERF 0x22 82#define SIBYTE_TRCTRL 0x23 83#define SIBYTE_WAFERID 0x24 84#define SIBYTE_PMON 0x25 85 86#if SIBYTE_HDR_FEATURE_1250_112x 87#define SB1250_CPU0OSC 0x26 88#define SB1250_CPU0DSC 0x27 89#define SB1250_CPU0TSC 0x28 90#define SB1250_CPU1OSC 0x2A 91#define SB1250_CPU1DSC 0x2B 92#define SB1250_CPU1TSC 0x2C 93#define SB1250_SCANIOB0 0x2E 94#define SB1250_SCANIOB1 0x30 95#define SB1250_SCANL2C 0x32 96#define SB1250_SCANMC 0x34 97#define SB1250_SCANSCD 0x36 98#define SB1250_SCANALL 0x38 99#define SB1250_BSRMODE 0x3A 100#define SB1250_SCANTRCCNT 0x3B 101#define SB1250_CLAMP 0x3C 102#define SB1250_SAMPLE 0x3D 103#define SB1250_INTEST 0x3E 104#define SB1250_BYPASS 0x3F 105#endif /* 1250 || 112x */ 106 107 108/* 109 * IDCODE 110 */ 111 112#define S_JTAG_REVISION _SB_MAKE32(28) 113#define M_JTAG_REVISION _SB_MAKEMASK(4,S_JTAG_REVISION) 114#define V_JTAG_REVISION(x) _SB_MAKEVALUE(x,S_JTAG_REVISION) 115#define G_JTAG_REVISION(x) _SB_GETVALUE(x,S_JTAG_REVISION,M_JTAG_REVISION) 116 117#define S_JTAG_PARTNUM _SB_MAKE32(12) 118#define M_JTAG_PARTNUM _SB_MAKEMASK(16,S_JTAG_PARTNUM) 119#define V_JTAG_PARTNUM(x) _SB_MAKEVALUE(x,S_JTAG_PARTNUM) 120#define G_JTAG_PARTNUM(x) _SB_GETVALUE(x,S_JTAG_PARTNUM,M_JTAG_PARTNUM) 121 122/* 123 * These _PART_ fields assume PARTNUM has been extracted (and shifted 124 * to bit 0). PART_TYPE matches the SYS_SOC_TYPE from sb1250_scd.h. 125 */ 126#define S_JTAG_PART_TYPE _SB_MAKE32(0) 127#define M_JTAG_PART_TYPE _SB_MAKEMASK(4,S_JTAG_PART_TYPE) 128#define V_JTAG_PART_TYPE(x) _SB_MAKEVALUE(x,S_JTAG_PART_TYPE) 129#define G_JTAG_PART_TYPE(x) _SB_GETVALUE(x,S_JTAG_PART_TYPE,M_JTAG_PART_TYPE) 130 131#define S_JTAG_PART_L2 _SB_MAKE32(4) 132#define M_JTAG_PART_L2 _SB_MAKEMASK(4,S_JTAG_PART_L2) 133#define V_JTAG_PART_L2(x) _SB_MAKEVALUE(x,S_JTAG_PART_L2) 134#define G_JTAG_PART_L2(x) _SB_GETVALUE(x,S_JTAG_PART_L2,M_JTAG_PART_L2) 135 136#define K_JTAG_PART_L2_1024 0 137#define K_JTAG_PART_L2_512 5 138#define K_JTAG_PART_L2_256 2 139#define K_JTAG_PART_L2_128 1 140 141#define S_JTAG_PART_CPUS _SB_MAKE32(8) 142#define M_JTAG_PART_CPUS _SB_MAKEMASK(4,S_JTAG_PART_CPUS) 143#define V_JTAG_PART_CPUS(x) _SB_MAKEVALUE(x,S_JTAG_PART_CPUS) 144#define G_JTAG_PART_CPUS(x) _SB_GETVALUE(x,S_JTAG_PART_CPUS,M_JTAG_PART_CPUS) 145 146#define S_JTAG_PART_CORE _SB_MAKE32(12) 147#define M_JTAG_PART_CORE _SB_MAKEMASK(4,S_JTAG_PART_CORE) 148#define V_JTAG_PART_CORE(x) _SB_MAKEVALUE(x,S_JTAG_PART_CORE) 149#define G_JTAG_PART_CORE(x) _SB_GETVALUE(x,S_JTAG_PART_CORE,M_JTAG_PART_CORE) 150 151#define K_JTAG_PART_CORE_SB1 1 152 153 154/* 155 * EJTAG Control Register (Table 15-14) 156 */ 157 158#if SIBYTE_HDR_FEATURE_1250_112x 159#define S_JTAG_1250_CR_DM0 0 160#define M_JTAG_1250_CR_DM0 _SB_MAKEMASK1(0) 161#define M_JTAG_1250_CR_DM1 _SB_MAKEMASK1(1) 162#define S_JTAG_1250_CR_EJTAGBreak0 2 163#define M_JTAG_1250_CR_EJTAGBreak0 _SB_MAKEMASK1(2) 164#define M_JTAG_1250_CR_EJTAGBreak1 _SB_MAKEMASK1(3) 165#define S_JTAG_1250_CR_PrTrap0 4 166#define M_JTAG_1250_CR_PrTrap0 _SB_MAKEMASK1(4) 167#define M_JTAG_1250_CR_PrTrap1 _SB_MAKEMASK1(5) 168#define S_JTAG_1250_CR_ProbEn 6 169#define M_JTAG_1250_CR_ProbEn _SB_MAKEMASK1(6) 170#define M_JTAG_1250_CR_PrAcc _SB_MAKEMASK1(7) 171#define M_JTAG_1250_CR_PW _SB_MAKEMASK1(8) 172#define M_JTAG_1250_CR_PbAcc _SB_MAKEMASK1(9) 173#define M_JTAG_1250_CR_MaSl _SB_MAKEMASK1(10) 174#define M_JTAG_1250_CR_ClkStopped _SB_MAKEMASK1(11) 175 176#define G_JTAG_1250_CR_EJTAGBreak(cpu) (M_JTAG_1250_CR_EJTAGBreak0 << (cpu)) 177#define G_JTAG_1250_CR_PrTrap(cpu) (M_JTAG_1250_CR_PrTrap0 << (cpu)) 178 179#define M_SYSCFG_1250_BIG_ENDIAN _SB_MAKEMASK1(22) 180 181#define S_SYSCFG_1250_CPU_RESET_0 54 182#define M_SYSCFG_1250_CPU_RESET_0 _SB_MAKEMASK1(54) 183#define M_SYSCFG_1250_CPU_RESET_1 _SB_MAKEMASK1(55) 184 185#define M_SYSCFG_1250_UNICPU_0 _SB_MAKEMASK1(56) 186#define M_SYSCFG_1250_UNICPU_1 _SB_MAKEMASK1(57) 187#define M_SYSCFG_1250_MISR_MODE _SB_MAKEMASK1(61) 188#define M_SYSCFG_1250_SW_FLAG _SB_MAKEMASK1(63) 189 190#define M_SYSCFG_1250_CPU_RESET(n) (M_SYSCFG_1250_CPU_RESET_0 << (n)) 191#endif /* 1250 || 112x */ 192 193/* 194 * System Config "extension" bits 104:64 (Table 15-5) 195 */ 196 197#if SIBYTE_HDR_FEATURE_1250_112x 198#define M_SYSCFG_1250_CLKSTOP _SB_MAKEMASK1(32) 199#define M_SYSCFG_1250_CLKSTEP _SB_MAKEMASK1(33) 200 201#define S_SYSCFG_1250_CLKCOUNT 34 202#define M_SYSCFG_1250_CLKCOUNT _SB_MAKEMASK(8,S_SYSCFG_1250_CLKCOUNT) 203#define V_SYSCFG_1250_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYSCFG_1250_CLKCOUNT) 204#define G_SYSCFG_1250_CLKCOUNT(x) _SB_GETVALUE(x,S_SYSCFG_1250_CLKCOUNT,M_SYSCFG_1250_CLKCOUNT) 205 206#define M_SYSCFG_1250_PLL_BYPASS _SB_MAKEMASK1(42) 207 208#define M_SYSCFG_1250_SB_SOFTRES _SB_MAKEMASK1(58) 209#define M_SYSCFG_1250_SYSTEM_RESET _SB_MAKEMASK1(60) 210 211/* These masks are in the second double-word */ 212#define S_SYSCFG_1250_PLLPHASE 0 213#define M_SYSCFG_1250_PLLPHASE _SB_MAKEMASK(2,S_SYSCFG_1250_PLLPHASE) 214#define V_SYSCFG_1250_PLLPHASE(x) _SB_MAKEVALUE(x,S_SYSCFG_1250_PLLPHASE) 215#define G_SYSCFG_1250_PLLPHASE(x) _SB_GETVALUE(x,S_SYSCFG_1250_PLLPHASE,M_SYSCFG_1250_PLLPHASE) 216 217#define K_SYSCFG_1250_PLLPHASE_A 1 218#define K_SYSCFG_1250_PLLPHASE_B 3 219 220#define V_SYSCFG_1250_PLLPHASE_A V_SYSCFG_1250_PLLPHASE(K_SYSCFG_1250_PLLPHASE_A) 221#define V_SYSCFG_1250_PLLPHASE_B V_SYSCFG_1250_PLLPHASE(K_SYSCFG_1250_PLLPHASE_B) 222 223#define S_SYSCFG_1250_PLLCOUNT 2 224#define M_SYSCFG_1250_PLLCOUNT _SB_MAKEMASK(30,S_SYSCFG_1250_PLLCOUNT) 225#define V_SYSCFG_1250_PLLCOUNT(x) _SB_MAKEVALUE(x,S_SYSCFG_1250_PLLCOUNT) 226#define G_SYSCFG_1250_PLLCOUNT(x) _SB_GETVALUE(x,S_SYSCFG_1250_PLLCOUNT,M_SYSCFG_1250_PLLCOUNT) 227 228#define M_SYSCFG_1250_PLLSTOP _SB_MAKEMASK1(32) 229#define M_SYSCFG_1250_STOPSTRETCH _SB_MAKEMASK1(33) 230#define M_SYSCFG_1250_STARTCOND _SB_MAKEMASK1(34) 231#define M_SYSCFG_1250_STOPPING _SB_MAKEMASK1(35) 232#define M_SYSCFG_1250_STOPSTRDONE _SB_MAKEMASK1(36) 233#define M_SYSCFG_1250_SERZB_ARD _SB_MAKEMASK1(37) 234#define M_SYSCFG_1250_SERZB_AR _SB_MAKEMASK1(38) 235 236#define S_SYSCFG_1250_STRETCHMODE 39 237#define M_SYSCFG_1250_STRETCHMODE _SB_MAKEMASK(2,S_SYSCFG_1250_STRETCHMODE) 238#define V_SYSCFG_1250_STRETCHMODE(x) _SB_MAKEVALUE(x,S_SYSCFG_1250_STRETCHMODE) 239#define G_SYSCFG_1250_STRETCHMODE(x) _SB_GETVALUE(x,S_SYSCFG_1250_STRETCHMODE,M_SYSCFG_1250_STRETCHMODE) 240#endif /* 1250 || 112x */ 241 242/* 243 * ZBbus definitions 244 */ 245 246#if SIBYTE_HDR_FEATURE_1250_112x 247#define K_ZB_CMD_READ_SHD 0 248#define K_ZB_CMD_READ_EXC 1 249#define K_ZB_CMD_WRITE 2 250#define K_ZB_CMD_WRITEINV 3 251#define K_ZB_CMD_INV 4 252#define K_ZB_CMD_NOP 7 253#endif /* 1250 || 112x */ 254 255#define K_ZB_L1CA_CNCOH 0 256#define K_ZB_L1CA_CCOH 1 257#define K_ZB_L1CA_UNC 2 258#define K_ZB_L1CA_UNC1 3 259 260#define K_ZB_L2CA_NOALLOC 0 261#define K_ZB_L2CA_ALLOC 1 262 263#define K_ZB_DMOD_CLEAN 0 264#define K_ZB_DMOD_DIRTY 1 265 266#define K_ZB_DCODE_NOP 0 267#define K_ZB_DCODE_VLD 1 268#define K_ZB_DCODE_VLD_TCORR 2 269#define K_ZB_DCODE_VLD_DCORR 3 270#define K_ZB_DCODE_BUSERR 4 271#define K_ZB_DCODE_FATAL_BUSERR 5 272#define K_ZB_DCODE_TAG_UNCORR 6 273#define K_ZB_DCODE_DATA_UNCORR 7 274 275#endif 276