1/* ********************************************************************* 2 * BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package 3 * 4 * Register Definitions File: bcm1480_regs.h 5 * 6 * This module contains the addresses of the on-chip peripherals 7 * on the BCM1280 and BCM1480. 8 * 9 * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48#ifndef _BCM1480_REGS_H 49#define _BCM1480_REGS_H 50 51#include "sb1250_defs.h" 52 53/* ********************************************************************* 54 * Pull in the BCM1250's registers since a great deal of the 1480's 55 * functions are the same as the BCM1250. 56 ********************************************************************* */ 57 58#include "sb1250_regs.h" 59 60 61/* ********************************************************************* 62 * Some general notes: 63 * 64 * Register addresses are grouped by function and follow the order 65 * of the User Manual. 66 * 67 * For the most part, when there is more than one peripheral 68 * of the same type on the SOC, the constants below will be 69 * offsets from the base of each peripheral. For example, 70 * the MAC registers are described as offsets from the first 71 * MAC register, and there will be a MAC_REGISTER() macro 72 * to calculate the base address of a given MAC. 73 * 74 * The information in this file is based on the BCM1X55/BCM1X80 75 * User Manual, Document 1X55_1X80-UM100-R, 22/12/03. 76 * 77 * This file is basically a "what's new" header file. Since the 78 * BCM1250 and the new BCM1480 (and derivatives) share many common 79 * features, this file contains only what's new or changed from 80 * the 1250. (above, you can see that we include the 1250 symbols 81 * to get the base functionality). 82 * 83 * In software, be sure to use the correct symbols, particularly 84 * for blocks that are different between the two chip families. 85 * All BCM1480-specific symbols have _BCM1480_ in their names, 86 * and all BCM1250-specific and "base" functions that are common in 87 * both chips have no special names (this is for compatibility with 88 * older include files). Therefore, if you're working with the 89 * SCD, which is very different on each chip, A_SCD_xxx implies 90 * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 91 * version. 92 ********************************************************************* */ 93 94 95/* ********************************************************************* 96 * Memory Controller Registers (Section 6) 97 ********************************************************************* */ 98 99#define A_BCM1480_MC_BASE_0 0x0010050000 100#define A_BCM1480_MC_BASE_1 0x0010051000 101#define A_BCM1480_MC_BASE_2 0x0010052000 102#define A_BCM1480_MC_BASE_3 0x0010053000 103#define BCM1480_MC_REGISTER_SPACING 0x1000 104 105#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) 106#define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) 107 108#define R_BCM1480_MC_CONFIG 0x0000000100 109#define R_BCM1480_MC_CS_START 0x0000000120 110#define R_BCM1480_MC_CS_END 0x0000000140 111#define S_BCM1480_MC_CS_STARTEND 24 112 113#define R_BCM1480_MC_CS01_ROW0 0x0000000180 114#define R_BCM1480_MC_CS01_ROW1 0x00000001A0 115#define R_BCM1480_MC_CS23_ROW0 0x0000000200 116#define R_BCM1480_MC_CS23_ROW1 0x0000000220 117#define R_BCM1480_MC_CS01_COL0 0x0000000280 118#define R_BCM1480_MC_CS01_COL1 0x00000002A0 119#define R_BCM1480_MC_CS23_COL0 0x0000000300 120#define R_BCM1480_MC_CS23_COL1 0x0000000320 121 122#define R_BCM1480_MC_CSX_BASE 0x0000000180 123#define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */ 124#define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */ 125#define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */ 126#define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */ 127#define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */ 128 129#define R_BCM1480_MC_CS01_BA 0x0000000380 130#define R_BCM1480_MC_CS23_BA 0x00000003A0 131#define R_BCM1480_MC_DRAMCMD 0x0000000400 132#define R_BCM1480_MC_DRAMMODE 0x0000000420 133#define R_BCM1480_MC_CLOCK_CFG 0x0000000440 134#define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG 135#define R_BCM1480_MC_TEST_DATA 0x0000000480 136#define R_BCM1480_MC_TEST_ECC 0x00000004A0 137#define R_BCM1480_MC_TIMING1 0x00000004C0 138#define R_BCM1480_MC_TIMING2 0x00000004E0 139#define R_BCM1480_MC_DLL_CFG 0x0000000500 140#define R_BCM1480_MC_DRIVE_CFG 0x0000000520 141 142#if SIBYTE_HDR_FEATURE(1480, PASS2) 143#define R_BCM1480_MC_ODT 0x0000000460 144#define R_BCM1480_MC_ECC_STATUS 0x0000000540 145#endif 146 147/* Global registers (single instance) */ 148#define A_BCM1480_MC_GLB_CONFIG 0x0010054100 149#define A_BCM1480_MC_GLB_INTLV 0x0010054120 150#define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140 151#define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160 152#define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180 153#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL 0x00100541A0 154 155/* ********************************************************************* 156 * L2 Cache Control Registers (Section 5) 157 ********************************************************************* */ 158 159#define A_BCM1480_L2_BASE 0x0010040000 160 161#define A_BCM1480_L2_READ_TAG 0x0010040018 162#define A_BCM1480_L2_ECC_TAG 0x0010040038 163#define A_BCM1480_L2_MISC0_VALUE 0x0010040058 164#define A_BCM1480_L2_MISC1_VALUE 0x0010040078 165#define A_BCM1480_L2_MISC2_VALUE 0x0010040098 166#define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */ 167#define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */ 168#define A_BCM1480_L2_MAKECACHEDISABLE(x) (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12)) 169#define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */ 170#define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */ 171#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12)) 172#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12)) 173#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12)) 174#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12)) 175#define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */ 176#define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */ 177#define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */ 178#define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */ 179#define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */ 180#define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */ 181#define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8)) 182#define A_BCM1480_L2_BANK_BASE 0x00D0300000 183#define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17)) 184#define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000 185 186 187/* ********************************************************************* 188 * PCI-X Interface Registers (Section 7) 189 ********************************************************************* */ 190 191#define A_BCM1480_PCI_BASE 0x0010061400 192 193#define A_BCM1480_PCI_RESET 0x0010061400 194#define A_BCM1480_PCI_DLL 0x0010061500 195 196#define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000 197 198/* ********************************************************************* 199 * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6) 200 ********************************************************************* */ 201 202/* No register changes with Rev.C BCM1250, but one additional MAC */ 203 204#define A_BCM1480_MAC_BASE_2 0x0010066000 205 206#ifndef A_MAC_BASE_2 207#define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2 208#endif 209 210#define A_BCM1480_MAC_BASE_3 0x0010067000 211#define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3 212 213#define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038 214 215#ifndef R_MAC_DMA_OODPKTLOST 216#define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST 217#endif 218 219 220/* ********************************************************************* 221 * DUART Registers (Section 14) 222 ********************************************************************* */ 223 224/* No significant differences from BCM1250, two DUARTs */ 225 226/* Conventions, per user manual: 227 * DUART generic, channels A,B,C,D 228 * DUART0 implementing channels A,B 229 * DUART1 inplementing channels C,D 230 */ 231 232#define BCM1480_DUART_NUM_PORTS 4 233 234#define A_BCM1480_DUART0 0x0010060000 235#define A_BCM1480_DUART1 0x0010060500 236#define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) 237 238#define BCM1480_DUART_CHANREG_SPACING 0x100 239#define A_BCM1480_DUART_CHANREG(chan,reg) (A_BCM1480_DUART(chan) \ 240 + BCM1480_DUART_CHANREG_SPACING*((chan)&1) \ 241 + (reg)) 242#define R_BCM1480_DUART_CHANREG(chan,reg) (BCM1480_DUART_CHANREG_SPACING*((chan)&1) + (reg)) 243 244#define R_BCM1480_DUART_IMRREG(chan) (R_DUART_IMR_A + ((chan)&1)*DUART_IMRISR_SPACING) 245#define R_BCM1480_DUART_ISRREG(chan) (R_DUART_ISR_A + ((chan)&1)*DUART_IMRISR_SPACING) 246 247#define A_BCM1480_DUART_IMRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan)) 248#define A_BCM1480_DUART_ISRREG(chan) (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan)) 249#define A_BCM1480_DUART_IN_PORT(chan) (A_BCM1480_DUART(chan) + R_DUART_INP_ORT) 250 251/* 252 * These constants are the absolute addresses. 253 */ 254 255#define A_BCM1480_DUART_MODE_REG_1_C 0x0010060500 256#define A_BCM1480_DUART_MODE_REG_2_C 0x0010060510 257#define A_BCM1480_DUART_STATUS_C 0x0010060520 258#define A_BCM1480_DUART_CLK_SEL_C 0x0010060530 259#define A_BCM1480_DUART_FULL_CTL_C 0x0010060540 260#define A_BCM1480_DUART_CMD_C 0x0010060550 261#define A_BCM1480_DUART_RX_HOLD_C 0x0010060560 262#define A_BCM1480_DUART_TX_HOLD_C 0x0010060570 263#define A_BCM1480_DUART_OPCR_C 0x0010060580 264#define A_BCM1480_DUART_AUX_CTRL_C 0x0010060590 265 266#define A_BCM1480_DUART_MODE_REG_1_D 0x0010060600 267#define A_BCM1480_DUART_MODE_REG_2_D 0x0010060610 268#define A_BCM1480_DUART_STATUS_D 0x0010060620 269#define A_BCM1480_DUART_CLK_SEL_D 0x0010060630 270#define A_BCM1480_DUART_FULL_CTL_D 0x0010060640 271#define A_BCM1480_DUART_CMD_D 0x0010060650 272#define A_BCM1480_DUART_RX_HOLD_D 0x0010060660 273#define A_BCM1480_DUART_TX_HOLD_D 0x0010060670 274#define A_BCM1480_DUART_OPCR_D 0x0010060680 275#define A_BCM1480_DUART_AUX_CTRL_D 0x0010060690 276 277#define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060700 278#define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060710 279#define A_BCM1480_DUART_ISR_C 0x0010060720 280#define A_BCM1480_DUART_IMR_C 0x0010060730 281#define A_BCM1480_DUART_ISR_D 0x0010060740 282#define A_BCM1480_DUART_IMR_D 0x0010060750 283#define A_BCM1480_DUART_OUT_PORT_CD 0x0010060760 284#define A_BCM1480_DUART_OPCR_CD 0x0010060770 285#define A_BCM1480_DUART_IN_PORT_CD 0x0010060780 286#define A_BCM1480_DUART_ISR_CD 0x0010060790 287#define A_BCM1480_DUART_IMR_CD 0x00100607A0 288#define A_BCM1480_DUART_SET_OPR_CD 0x00100607B0 289#define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100607C0 290#define A_BCM1480_DUART_INPORT_CHNG_C 0x00100607D0 291#define A_BCM1480_DUART_INPORT_CHNG_D 0x00100607E0 292 293 294/* ********************************************************************* 295 * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16) 296 ********************************************************************* */ 297 298#define A_BCM1480_IO_PCMCIA_CFG_B 0x0010061A58 299#define A_BCM1480_IO_PCMCIA_STATUS_B 0x0010061A68 300 301/* ********************************************************************* 302 * GPIO Registers (Section 17) 303 ********************************************************************* */ 304 305/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */ 306 307#define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78 308#define R_BCM1480_GPIO_INT_ADD_TYPE (-8) 309 310#define A_GPIO_INT_ADD_TYPE A_BCM1480_GPIO_INT_ADD_TYPE 311#define R_GPIO_INT_ADD_TYPE R_BCM1480_GPIO_INT_ADD_TYPE 312 313/* ********************************************************************* 314 * SMBus Registers (Section 18) 315 ********************************************************************* */ 316 317/* No changes from BCM1250 */ 318 319/* ********************************************************************* 320 * Timer Registers (Sections 4.6) 321 ********************************************************************* */ 322 323/* BCM1480 has two additional watchdogs */ 324 325/* Watchdog timers */ 326 327#define A_BCM1480_SCD_WDOG_2 0x0010022050 328#define A_BCM1480_SCD_WDOG_3 0x0010022150 329 330#define BCM1480_SCD_NUM_WDOGS 4 331 332#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) 333#define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) 334 335#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 336#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 337#define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060 338 339#define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150 340#define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158 341#define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160 342 343/* BCM1480 has two additional compare registers */ 344 345#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT A_SCD_ZBBUS_CYCLE_COUNT 346#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00 347#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0 348#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1 349#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10 350#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18 351 352/* ********************************************************************* 353 * System Control Registers (Section 4.2) 354 ********************************************************************* */ 355 356/* Scratch register in different place */ 357 358#define A_BCM1480_SCD_SCRATCH 0x100200A0 359 360/* ********************************************************************* 361 * System Address Trap Registers (Section 4.9) 362 ********************************************************************* */ 363 364/* No changes from BCM1250 */ 365 366/* ********************************************************************* 367 * System Interrupt Mapper Registers (Sections 4.3-4.5) 368 ********************************************************************* */ 369 370#define A_BCM1480_IMR_CPU0_BASE 0x0010020000 371#define A_BCM1480_IMR_CPU1_BASE 0x0010022000 372#define A_BCM1480_IMR_CPU2_BASE 0x0010024000 373#define A_BCM1480_IMR_CPU3_BASE 0x0010026000 374#define BCM1480_IMR_REGISTER_SPACING 0x2000 375#define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 376 377#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) 378#define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) 379 380/* Most IMR registers are 128 bits, implemented as non-contiguous 381 64-bit registers high (_H) and low (_L) */ 382#define BCM1480_IMR_HL_SPACING 0x1000 383 384#define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010 385#define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018 386#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020 387#define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028 388#define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038 389#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040 390#define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048 391#define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0 392#define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8 393#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0 394#define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0 395#define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8 396#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0 397#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100 398#define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8 399#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200 400#define BCM1480_IMR_INTERRUPT_MAP_COUNT 64 401 402#define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010 403#define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018 404#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020 405#define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028 406#define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038 407#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040 408#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100 409#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200 410 411#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000 412#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100 413#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200 414#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300 415#define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100 416 417#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ 418 (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) 419#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) 420 421#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ 422#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ 423 424/* 425 * these macros work together to build the address of a mailbox 426 * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2) 427 * for mbox_0_set_cpu2 returns 0x00100240C8 428 */ 429#define R_BCM1480_IMR_MAILBOX_CPU 0x00 430#define R_BCM1480_IMR_MAILBOX_SET 0x08 431#define R_BCM1480_IMR_MAILBOX_CLR 0x10 432#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 433#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \ 434 (A_BCM1480_IMR_CPU0_BASE + \ 435 (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ 436 (cpu * BCM1480_IMR_REGISTER_SPACING) + \ 437 (R_BCM1480_IMR_MAILBOX_0_CPU + reg)) 438 439/* ********************************************************************* 440 * System Performance Counter Registers (Section 4.7) 441 ********************************************************************* */ 442 443/* BCM1480 has four more performance counter registers, and two control 444 registers. */ 445 446#define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0 447 448#define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0 449#define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0 450#define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8 451#define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1 452 453#define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0 454#define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1 455#define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2 456#define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3 457 458#define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0 459#define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8 460#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 461#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 462 463#define BCM1480_SCD_NUM_PERF_CNT 8 464#define BCM1480_SCD_PERF_CNT_SPACING 8 465#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING)) 466 467/* ********************************************************************* 468 * System Bus Watcher Registers (Section 4.8) 469 ********************************************************************* */ 470 471 472/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ 473 474#define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8 475 476/* ********************************************************************* 477 * System Debug Controller Registers (Section 19) 478 ********************************************************************* */ 479 480/* Same as 1250 */ 481 482/* ********************************************************************* 483 * System Trace Unit Registers (Sections 4.10) 484 ********************************************************************* */ 485 486/* Same as 1250 */ 487 488/* ********************************************************************* 489 * Data Mover DMA Registers (Section 10.7) 490 ********************************************************************* */ 491 492/* Same as 1250 */ 493 494 495/* ********************************************************************* 496 * HyperTransport Interface Registers (Section 8) 497 ********************************************************************* */ 498 499#define BCM1480_HT_NUM_PORTS 3 500#define BCM1480_HT_PORT_SPACING 0x800 501#define A_BCM1480_HT_PORT_HEADER(x) (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING)) 502 503#define A_BCM1480_HT_PORT0_HEADER 0x00FE000000 504#define A_BCM1480_HT_PORT1_HEADER 0x00FE000800 505#define A_BCM1480_HT_PORT2_HEADER 0x00FE001000 506#define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000 507 508 509/* ********************************************************************* 510 * Node Controller Registers (Section 9) 511 ********************************************************************* */ 512 513#define A_BCM1480_NC_BASE 0x00DFBD0000 514 515#define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000 516#define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020 517#define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040 518#define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060 519#define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080 520#define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0 521#define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0 522 523#define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0 524#define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100 525#define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120 526#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL 0x00DFBD0140 527 528#define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200 529#define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220 530#define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240 531#define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260 532#define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280 533#define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0 534#define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0 535#define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0 536#define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300 537#define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320 538#define A_BCM1480_NC_CREDIT_STATUS_REG10 0x00DFBE0000 539#define A_BCM1480_NC_CREDIT_STATUS_REG11 0x00DFBE0020 540#define A_BCM1480_NC_CREDIT_STATUS_REG12 0x00DFBE0040 541 542#define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060 543#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080 544 545 546/* ********************************************************************* 547 * H&R Block Configuration Registers (Section 12.4) 548 ********************************************************************* */ 549 550#define A_BCM1480_HR_BASE_0 0x00DF820000 551#define A_BCM1480_HR_BASE_1 0x00DF8A0000 552#define A_BCM1480_HR_BASE_2 0x00DF920000 553#define BCM1480_HR_REGISTER_SPACING 0x80000 554 555#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) 556#define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg)) 557 558#define R_BCM1480_HR_CFG 0x0000000000 559 560#define R_BCM1480_HR_MAPPING 0x0000010010 561 562#define BCM1480_HR_RULE_SPACING 0x0000000010 563#define BCM1480_HR_NUM_RULES 16 564#define BCM1480_HR_OP_OFFSET 0x0000000100 565#define BCM1480_HR_TYPE_OFFSET 0x0000000108 566#define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) 567#define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) 568 569#define BCM1480_HR_LEAF_SPACING 0x0000000010 570#define BCM1480_HR_NUM_LEAVES 10 571#define BCM1480_HR_LEAF_OFFSET 0x0000000300 572#define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING)) 573 574#define R_BCM1480_HR_EX_LEAF0 0x00000003A0 575 576#define BCM1480_HR_PATH_SPACING 0x0000000010 577#define BCM1480_HR_NUM_PATHS 16 578#define BCM1480_HR_PATH_OFFSET 0x0000000600 579#define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING)) 580 581#define R_BCM1480_HR_PATH_DEFAULT 0x0000000700 582 583#define BCM1480_HR_ROUTE_SPACING 8 584#define BCM1480_HR_NUM_ROUTES 512 585#define BCM1480_HR_ROUTE_OFFSET 0x0000001000 586#define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING)) 587 588 589/* checked to here - ehs */ 590/* ********************************************************************* 591 * Packet Manager DMA Registers (Section 12.5) 592 ********************************************************************* */ 593 594#define A_BCM1480_PM_BASE 0x0010056000 595 596#define A_BCM1480_PMI_LCL_0 0x0010058000 597#define A_BCM1480_PMO_LCL_0 0x001005C000 598#define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE) 599#define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE) 600 601#define BCM1480_PM_LCL_REGISTER_SPACING 0x100 602#define BCM1480_PM_NUM_CHANNELS 32 603 604#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) 605#define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) 606#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) 607#define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) 608 609#define BCM1480_PM_INT_PACKING 8 610#define BCM1480_PM_INT_FUNCTION_SPACING 0x40 611#define BCM1480_PM_INT_NUM_FUNCTIONS 3 612 613/* 614 * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n) 615 */ 616 617#define R_BCM1480_PM_BASE_SIZE 0x0000000000 618#define R_BCM1480_PM_CNT 0x0000000008 619#define R_BCM1480_PM_PFCNT 0x0000000010 620#define R_BCM1480_PM_LAST 0x0000000018 621#define R_BCM1480_PM_PFINDX 0x0000000020 622#define R_BCM1480_PM_INT_WMK 0x0000000028 623#define R_BCM1480_PM_CONFIG0 0x0000000030 624#define R_BCM1480_PM_LOCALDEBUG 0x0000000078 625#define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */ 626#define R_BCM1480_PM_INT_CNFG 0x0000000088 627#define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090 628#define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */ 629#define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */ 630 631/* 632 * Global Registers (Not Channelized) 633 */ 634 635#define A_BCM1480_PMI_GLB_0 0x0010056000 636#define A_BCM1480_PMO_GLB_0 0x0010057000 637 638/* 639 * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0 640 */ 641 642#define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */ 643 644#define A_BCM1480_PM_PMO_MAPPING (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING) 645 646/* 647 * Interrupt mapping registers 648 */ 649 650 651#define A_BCM1480_PMI_INT_0 0x0010056800 652#define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8)) 653#define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE) 654#define A_BCM1480_PMO_INT_0 0x0010057800 655#define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8)) 656#define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE) 657 658/* 659 * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0 660 */ 661 662#define R_BCM1480_PM_INT_ST 0x0000000000 663#define R_BCM1480_PM_INT_MSK 0x0000000040 664#define R_BCM1480_PM_INT_CLR 0x0000000080 665#define R_BCM1480_PM_MRGD_INT 0x00000000C0 666 667/* 668 * Debug registers (global) 669 */ 670 671#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI 0x0010056000 672#define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8 673#define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8 674#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO 0x0010057000 675#define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8 676#define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8 677 678/* ********************************************************************* 679 * Switch performance counters 680 ********************************************************************* */ 681 682#define A_BCM1480_SWPERF_CFG 0xdfb91800 683#define A_BCM1480_SWPERF_CNT0 0xdfb91880 684#define A_BCM1480_SWPERF_CNT1 0xdfb91888 685#define A_BCM1480_SWPERF_CNT2 0xdfb91890 686#define A_BCM1480_SWPERF_CNT3 0xdfb91898 687 688 689/* ********************************************************************* 690 * Switch Trace Unit 691 ********************************************************************* */ 692 693#define A_BCM1480_SWTRC_MATCH_CONTROL_0 0xDFB91000 694#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 0xDFB91100 695#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0 0xDFB91108 696#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 0xDFB91200 697#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0 0xDFB91208 698#define A_BCM1480_SWTRC_EVENT_0 0xDFB91300 699#define A_BCM1480_SWTRC_SEQUENCE_0 0xDFB91400 700 701#define A_BCM1480_SWTRC_CFG 0xDFB91500 702#define A_BCM1480_SWTRC_READ 0xDFB91508 703 704#define A_BCM1480_SWDEBUG_SCHEDSTOP 0xDFB92000 705 706#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8)) 707#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8)) 708#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8)) 709 710#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16)) 711#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16)) 712#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16)) 713#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16)) 714 715 716 717/* ********************************************************************* 718 * High-Speed Port Registers (Section 13) 719 ********************************************************************* */ 720 721#define A_BCM1480_HSP_BASE_0 0x00DF810000 722#define A_BCM1480_HSP_BASE_1 0x00DF890000 723#define A_BCM1480_HSP_BASE_2 0x00DF910000 724#define BCM1480_HSP_REGISTER_SPACING 0x80000 725 726#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) 727#define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg)) 728 729#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 730#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 731#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010 732#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018 733#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN 0x0000000020 734#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028 735 736#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0 0x0000000200 737#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1 0x0000000208 738 739#define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800 740#define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808 741#define R_BCM1480_HSP_RX_TEST 0x0000000810 742#define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818 743#define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820 744#define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828 745#define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830 746#define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838 747 748#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER 0x0000000870 749 750#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020 751#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028 752#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030 753#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038 754#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040 755#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048 756#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050 757#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058 758#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx)) 759 760/* XXX Following registers were shuffled. Renamed/renumbered per errata. */ 761#define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078 762#define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080 763#define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088 764#define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090 765#define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098 766#define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0 767 768#define R_BCM1480_HSP_RX_SPI_WATERMARK_0 0x00000200B0 769#define R_BCM1480_HSP_RX_SPI_WATERMARK_1 0x00000200B8 770#define R_BCM1480_HSP_RX_SPI_WATERMARK_2 0x00000200C0 771#define R_BCM1480_HSP_RX_SPI_WATERMARK_3 0x00000200C8 772#define R_BCM1480_HSP_RX_SPI_WATERMARK_4 0x00000200D0 773#define R_BCM1480_HSP_RX_SPI_WATERMARK_5 0x00000200D8 774#define R_BCM1480_HSP_RX_SPI_WATERMARK_6 0x00000200E0 775#define R_BCM1480_HSP_RX_SPI_WATERMARK_7 0x00000200E8 776#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx) (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx)) 777 778#define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0 779#define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8 780#define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100 781#define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108 782#define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110 783#define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118 784#define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120 785 786#define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000 787#define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008 788#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT 0x0000040010 789 790#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020 791#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028 792#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030 793#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038 794#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040 795#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048 796#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050 797#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058 798#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx)) 799#define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078 800#define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080 801#define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088 802#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0 0x0000040090 803#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1 0x0000040098 804#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2 0x00000400A0 805 806#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 0x00000400B0 807#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1 0x00000400B8 808#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2 0x00000400C0 809#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3 0x00000400C8 810#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx)) 811#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0 812#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8 813 814#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 0x00000400E0 815#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1 0x00000400E8 816#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2 0x00000400F0 817#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3 0x00000400F8 818#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx)) 819#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100 820#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108 821 822#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0 0x0000040200 823#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1 0x0000040208 824 825#define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800 826#define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808 827#define R_BCM1480_HSP_TX_TEST 0x0000040810 828 829#define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840 830#define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848 831#define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850 832#define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860 833#define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868 834#define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870 835#define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878 836 837#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880 838#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN 0x0000040888 839 840#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400 841#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x)) 842 843 844 845/* ********************************************************************* 846 * Physical Address Map (Table 10 and Figure 7) 847 ********************************************************************* */ 848 849#define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 850#define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 851#define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 852#define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) 853#define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000) 854#define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000) 855#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000) 856#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000) 857#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000) 858#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000) 859#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000) 860#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000) 861#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000) 862#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000) 863#define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) 864#define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) 865#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000) 866#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000) 867#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000) 868#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000) 869#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000) 870#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000) 871#define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) 872#define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) 873#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) 874#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) 875#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) 876#define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000) 877#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) 878#define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) 879#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) 880#define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) 881#define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) 882#define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000) 883#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000) 884#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000) 885#define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000) 886#define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000) 887 888 889/* ********************************************************************* 890 * L2 Cache as RAM (Table 54) 891 ********************************************************************* */ 892 893#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) 894#define BCM1480_PHYS_L2CACHE_NUM_WAYS 8 895#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000) 896#define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000) 897#define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000) 898#define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000) 899#define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000) 900#define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000) 901#define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000) 902#define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000) 903#define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000) 904 905#endif /* _BCM1480_REGS_H */ 906