1/*  *********************************************************************
2    *  Broadcom Common Firmware Environment (CFE)
3    *
4    *  Silicon Backplane definitions       	File: sb_mips.h
5    *
6    *********************************************************************
7    *
8    *  Copyright 2003
9    *  Broadcom Corporation. All rights reserved.
10    *
11    *  This software is furnished under license and may be used and
12    *  copied only in accordance with the following terms and
13    *  conditions.  Subject to these conditions, you may download,
14    *  copy, install, use, modify and distribute modified or unmodified
15    *  copies of this software in source and/or binary form.  No title
16    *  or ownership is transferred hereby.
17    *
18    *  1) Any source code used, modified or distributed must reproduce
19    *     and retain this copyright notice and list of conditions
20    *     as they appear in the source file.
21    *
22    *  2) No right is granted to use any trade name, trademark, or
23    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
24    *     name may not be used to endorse or promote products derived
25    *     from this software without the prior written permission of
26    *     Broadcom Corporation.
27    *
28    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
29    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
30    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
31    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
32    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
33    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
34    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
36    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
37    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
38    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
39    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
40    *     THE POSSIBILITY OF SUCH DAMAGE.
41    ********************************************************************* */
42
43#ifndef _SBMIPS_H_
44#define _SBMIPS_H_
45
46/*
47 * Register and bit definitions for the CPU control registers of the
48 * MIPS (OCP ID 0x805) and MIPS33 (OCP ID 0x813) cores.
49 */
50
51
52/* MIPS Core 0x805 (Ref 1, Section 4) */
53
54#define R_CORE_CONTROL          0x000
55#define R_BIST_STATUS           0x004
56
57/* CORECTL: Core Control Register (0x000, R/W) */
58
59#define M_CORECTL_FR            _DD_MAKEMASK1(0)        /* ForceReset */
60#define M_CORECTL_DF            _DD_MAKEMASK1(1)        /* DisableFlashExceptions */
61
62/* BIST: BIST Status Register (0x00C, RO) */
63
64#define S_BIST_BS               0                       /* BistStatus */
65#define M_BIST_BS               _DD_MAKEMASK(8,S_BIST_BS)
66#define V_BIST_BS(x)            _DD_MAKEVALUE(x,S_BIST_BS)
67#define G_BIST_BS(x)            _DD_GETVALUE(x,S_BIST_BS,M_BIST_BS)
68
69
70/* MIPS33 Core 0x813 Extensions (Ref 2, Section 10). */
71
72#define R_BIST_CONTROL          0x008
73#define R_INT_STATUS            0x020
74#define R_INT_MASK              0x024
75#define R_TIMER0                0x028
76#define R_TEST_MUX_SELECT       0x030
77#define R_TEST_MUX_ENABLE       0x034
78#define R_EJTAG_PIO_EN          0x02c
79
80/* BISTCTL: BIST Control Register (0x008, R/W) */
81
82#define M_BISTCTL_BD            _DD_MAKEMASK1(0)        /* BISTDump */
83#define M_BISTCTL_BG            _DD_MAKEMASK1(1)        /* BISTDebug */
84#define M_BISTCTL_BH            _DD_MAKEMASK1(2)        /* BISTHold */
85
86/* ISR: Interrupt Status Register (0x020, R/W) */
87/* IMR: Interrupt Mask Register (0x024, R/W) */
88
89#define M_INT_T0                _DD_MAKEMASK1(0)        /* Timer0 */
90
91/* TIMER0: Timer0 Register (0x030, R/W) */
92
93/* TMUXSEL: Test Multiplexer Select Register (0x028, R/W) */
94
95#define S_TMUXSEL_SL            0                       /* SelLow */
96#define M_TMUXSEL_SL            _DD_MAKEMASK(8,S_TMUXSEL_SL)
97#define V_TMUXSEL_SL(x)         _DD_MAKEVALUE(x,S_TMUXSEL_SL)
98#define G_TMUXSEL_SL(x)         _DD_GETVALUE(x,S_TMUXSEL_SL,M_TMUXSEL_SL)
99
100#define S_TMUXSEL_SH            0                       /* SelHigh */
101#define M_TMUXSEL_SH            _DD_MAKEMASK(8,S_TMUXSEL_SH)
102#define V_TMUXSEL_SH(x)         _DD_MAKEVALUE(x,S_TMUXSEL_SH)
103#define G_TMUXSEL_SH(x)         _DD_GETVALUE(x,S_TMUXSEL_SH,M_TMUXSEL_SH)
104
105/* TMUXEN: Test Multiplexer Select Enable Register (0x034, R/W) */
106
107/* EJTAGPIOEN: EJTAG GPIO Enable Register (0x02C, R/W) */
108
109#endif /* _SBMIPS_H_ */
110