1/*  *********************************************************************
2    *  Broadcom Common Firmware Environment (CFE)
3    *
4    *  Silicon Backplane external interface        File: sb_extif.h
5    *
6    *********************************************************************
7    *
8    *  Copyright 2003
9    *  Broadcom Corporation. All rights reserved.
10    *
11    *  This software is furnished under license and may be used and
12    *  copied only in accordance with the following terms and
13    *  conditions.  Subject to these conditions, you may download,
14    *  copy, install, use, modify and distribute modified or unmodified
15    *  copies of this software in source and/or binary form.  No title
16    *  or ownership is transferred hereby.
17    *
18    *  1) Any source code used, modified or distributed must reproduce
19    *     and retain this copyright notice and list of conditions
20    *     as they appear in the source file.
21    *
22    *  2) No right is granted to use any trade name, trademark, or
23    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
24    *     name may not be used to endorse or promote products derived
25    *     from this software without the prior written permission of
26    *     Broadcom Corporation.
27    *
28    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
29    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
30    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
31    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
32    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
33    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
34    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
36    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
37    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
38    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
39    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
40    *     THE POSSIBILITY OF SUCH DAMAGE.
41    ********************************************************************* */
42
43#ifndef _SBEXTIF_H_
44#define _SBEXTIF_H_
45
46/*
47 * Register and bit definitions for the External Interface control
48 * registers (OCP ID 0x811)
49 */
50
51
52/* External Interface Core (Section 11) */
53
54#define R_CORECNTL              0x000
55#define R_EXTSTATUS             0x004
56/* PCMCIA Control Registers */
57#define R_PCMCIACONFIG          0x010
58#define R_PCMCIAMEMWAITCNT      0x014
59#define R_PCMCIAATTRWAITCNT     0x018
60#define R_PCMCIAIOWAITCNT       0x01C
61
62/* Programmable Interface Control Registers */
63#define R_PROGINTCONFIG         0x020
64#define R_PROGWAITCNT           0x024
65
66/* Flash Control Registers */
67#define R_FLASHCONFIG           0x028
68#define R_FLASHWAITCNT          0x02C
69
70#define R_WATCHDOGCNTR          0x040
71
72/* Clock Control Registers (Section 11.1) */
73#define R_CLOCKCONTROLN         0x044
74#define R_CLOCKCONTROLSB        0x048
75#define R_CLOCKCONTROLPCI       0x04C
76#define R_CLOCKCONTROLMII       0x050
77
78/* GPIO Registers (Section 11.2) */
79#define R_GPIOINPUT             0x060
80#define R_GPIOOUTPUT0           0x064
81#define R_GPIOOUTPUT1           0x06C
82#define R_GPIOOUTPUT2           0x074
83#define R_GPIOOUTPUT3           0x07C
84#define R_GPIOOUTPUT4           0x084
85#define R_GPIOOUTEN0            0x068
86#define R_GPIOOUTEN1            0x070
87#define R_GPIOOUTEN2            0x078
88#define R_GPIOOUTEN3            0x080
89#define R_GPIOOUTEN4            0x088
90#define R_EJTAGOUTEN            0x090
91#define R_GPIOINTPOLARITY       0x094
92#define R_GPIOINTMASK           0x098
93
94
95/* CORECTL: Core Control Register (0x000, R/W) */
96
97#define M_CORECTL_UE            _DD_MAKEMASK1(0)        /* UartEnable */
98
99/* EXTSTAT: External Status Register (0x004, RO) */
100
101#define M_EXTSTAT_EM            _DD_MAKEMASK1(0)        /* EndianMode */
102#define M_EXTSTAT_EI            _DD_MAKEMASK1(1)        /* ExtInt */
103#define M_EXTSTAT_GI            _DD_MAKEMASK1(2)        /* GPIOInt */
104
105
106/* PCMCIACFG: PCMCIA Configuration Register (0x010, R/W) */
107/* PROGCFG:   Programmable Interface Configuration Register (0x020, R/W) */
108/* FLASHCFG:  Flash Configuration Register (0x028, R/W) */
109
110#define M_IFCFG_EN              _DD_MAKEMASK1(0)        /* Enable */
111
112#define S_IFCFG_EM              1                       /* ExtIfMode */
113#define M_IFCFG_EM              _DD_MAKEMASK(3,S_IFCFG_EM)
114#define V_IFCFG_EM(x)           _DD_MAKEVALUE(x,S_IFCFG_EM)
115#define G_IFCFG_EM(x)           _DD_GETVALUE(x,S_IFCFG_EM,M_IFCFG_EM)
116#define K_EM_ASYNC              0
117#define K_EM_SYNC               1
118#define K_EM_PCMCIA             2
119
120#define M_IFCFG_DS              _DD_MAKEMASK1(4)        /* DestSize */
121#define M_IFCFG_BS              _DD_MAKEMASK1(5)        /* ByteSwap */
122
123#define S_IFCFG_CD              6                       /* ClockDivider */
124#define M_IFCFG_CD              _DD_MAKCDASK(2,S_IFCFG_CD)
125#define V_IFCFG_CD(x)           _DD_MAKEVALUE(x,S_IFCFG_CD)
126#define G_IFCFG_CD(x)           _DD_GETVALUE(x,S_IFCFG_CD,M_IFCFG_CD)
127
128#define M_IFCFG_CE              _DD_MAKEMASK1(8)        /* ClockEnable */
129#define M_IFCFG_SB              _DD_MAKEMASK1(9)        /* Size/ByteStrobe */
130
131
132/* WDOG: Watchdog Counter Register (0x040, R/W) */
133
134
135/* CCN: Clock Control N Register (0x044, R/W, buffered) */
136
137#define S_CCN_N1                0                       /* N1Control */
138#define M_CCN_N1                _DD_MAKEMASK(6,S_CCN_N1)
139#define V_CCN_N1(x)             _DD_MAKEVALUE(x,S_CCN_N1)
140#define G_CCN_N1(x)             _DD_GETVALUE(x,S_CCN_N1,M_CCN_N1)
141
142#define S_CCN_N2                8                       /* N2Control */
143#define M_CCN_N2                _DD_MAKEMASK(5,S_CCN_N2)
144#define V_CCN_N2(x)             _DD_MAKEVALUE(x,S_CCN_N2)
145#define G_CCN_N2(x)             _DD_GETVALUE(x,S_CCN_N2,M_CCN_N2)
146
147/* CCSB:  Clock Control SB Register (0x048, R/W, buffered) */
148/* CCPCI: Clock Control PCI Register (0x04C, R/W, buffered) */
149/* CCMII: Clock Control MII Register (0x050, R/W, buffered) */
150
151#define S_CCM_M1                0                       /* M1Control */
152#define M_CCM_M1                _DD_MAKEMASK(6,S_CCM_M1)
153#define V_CCM_M1(x)             _DD_MAKEVALUE(x,S_CCM_M1)
154#define G_CCM_M1(x)             _DD_GETVALUE(x,S_CCM_M1,M_CCM_M1)
155
156#define S_CCM_M2                8                       /* M2Control */
157#define M_CCM_M2                _DD_MAKEMASK(5,S_CCM_M2)
158#define V_CCM_M2(x)             _DD_MAKEVALUE(x,S_CCM_M2)
159#define G_CCM_M2(x)             _DD_GETVALUE(x,S_CCM_M2,M_CCM_M2)
160
161#define S_CCM_M3                16                      /* M3Control */
162#define M_CCM_M3                _DD_MAKEMASK(6,S_CCM_M3)
163#define V_CCM_M3(x)             _DD_MAKEVALUE(x,S_CCM_M3)
164#define G_CCM_M3(x)             _DD_GETVALUE(x,S_CCM_M3,M_CCM_M3)
165
166#define S_CCM_MC                24                       /* MuxControl */
167#define M_CCM_MC                _DD_MAKEMASK(5,S_CCM_MC)
168#define V_CCM_MC(x)             _DD_MAKEVALUE(x,S_CCM_MC)
169#define G_CCM_MC(x)             _DD_GETVALUE(x,S_CCM_MC,M_CCM_MC)
170
171
172#endif /* _SBEXTIF_H_ */
173