1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * Silicon Backplane definitions File: sb_bp.c 5 * 6 ********************************************************************* 7 * 8 * Copyright 2003 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and 13 * conditions. Subject to these conditions, you may download, 14 * copy, install, use, modify and distribute modified or unmodified 15 * copies of this software in source and/or binary form. No title 16 * or ownership is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions 20 * as they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products derived 25 * from this software without the prior written permission of 26 * Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 40 * THE POSSIBILITY OF SUCH DAMAGE. 41 ********************************************************************* */ 42 43#ifndef _SBBP_H_ 44#define _SBBP_H_ 45 46#define _DD_MAKEMASK1(n) (1 << (n)) 47#define _DD_MAKEMASK(v,n) ((((1)<<(v))-1) << (n)) 48#define _DD_MAKEVALUE(v,n) ((v) << (n)) 49#define _DD_GETVALUE(v,n,m) (((v) & (m)) >> (n)) 50 51/* 52 * Definitions for the address map and core configuration space 53 * registers of Broadcom SiliconBackplane products. 54 * 55 * These products contain multiple cores that communicate via a 56 * system backplane ("Silicon Backplane") internal to the chip. 57 * 58 * Each core occupies 4K (0x1000) bytes of "enumeration" space. 59 * Enumeration spaces are contiguous and begin at 0x18000000, but both 60 * the selection and ordering of cores is chip-specific. 61 * 62 * Each enumeration space includes a configuration region at offset 63 * 0xF00 consisting of registers to identify the core and map its 64 * resources. Some cores, including the MAC, have a standard DMA 65 * engine; if so, its registers appear at offset 0x200 in enumeration 66 * space. 67 */ 68 69/* Vendor and Core identifiers */ 70 71#define K_VN_BROADCOM 0x4243 72 73#define K_CR_CHIP_COMMON 0x800 74#define K_CR_ILINE20 0x801 75#define K_CR_SDRAM 0x803 76#define K_CR_PCI 0x804 77#define K_CR_MIPS 0x805 78#define K_CR_ENET 0x806 79#define K_CR_CODEC 0x807 80#define K_CR_USB 0x808 81#define K_CR_ILINE100 0x80A 82#define K_CR_IPSEC 0x80B 83#define K_CR_PCMCIA 0x80D 84#define K_CR_MEMC 0x80F 85#define K_CR_EXT 0x811 86#define K_CR_MAC11 0x812 87#define K_CR_MIPS33 0x816 88 89 90/* Each core gets a 4K window for registers. */ 91 92#define SB_CORE_SIZE 0x1000 93 94/* Core Configuration Space Registers (Section 2, Table 3) */ 95 96/* These registers are found at the top of the 4K window for each core. */ 97 98#define R_SBIPSFLAG 0xF08 99#define R_SBTPSFLAG 0xF18 100#define R_SBTMERRLOGA 0xF48 101#define R_SBTMERRLOG 0xF50 102#define R_SBADMATCH3 0xF60 103#define R_SBADMATCH2 0xF68 104#define R_SBADMATCH1 0xF70 105#define R_SBIMSTATE 0xF90 106#define R_SBINTVEC 0xF94 107#define R_SBTMSTATELOW 0xF98 108#define R_SBTMSTATEHI 0xF9C 109#define R_SBBWA0 0xFA0 110#define R_SBIMCONFIGLOW 0xFA8 111#define R_SBIMCONFIGHIGH 0xFAC 112#define R_SBADMATCH0 0xFB0 113#define R_SBTMCONFIGLOW 0xFB8 114#define R_SBTMCONFIGHIGH 0xFBC 115#define R_SBBCONFIG 0xFC0 116#define R_SBBSTATE 0xFC8 117#define R_SBACTCNFG 0xFD8 118#define R_SBFLAGST 0xFE8 119#define R_SBIDLOW 0xFF8 120#define R_SBIDHIGH 0xFFC 121 122 123/* SBISF: System Backplane Initiator Slave Flag Control Register (0xF08, R/W) */ 124 125#define S_SBISF_F1 0 /* IntFlag1 */ 126#define M_SBISF_F1 _DD_MAKEMASK(6,S_SBISF_F1) 127#define V_SBISF_F1(x) _DD_MAKEVALUE(x,S_SBISF_F1) 128#define G_SBISF_F1(x) _DD_GETVALUE(x,S_SBISF_F1,M_SBISF_F1) 129 130#define S_SBISF_F2 8 /* IntFlag2 */ 131#define M_SBISF_F2 _DD_MAKEMASK(6,S_SBISF_F2) 132#define V_SBISF_F2(x) _DD_MAKEVALUE(x,S_SBISF_F2) 133#define G_SBISF_F2(x) _DD_GETVALUE(x,S_SBISF_F2,M_SBISF_F2) 134 135#define S_SBISF_F3 16 /* IntFlag3 */ 136#define M_SBISF_F3 _DD_MAKEMASK(6,S_SBISF_F3) 137#define V_SBISF_F3(x) _DD_MAKEVALUE(x,S_SBISF_F3) 138#define G_SBISF_F3(x) _DD_GETVALUE(x,S_SBISF_F3,M_SBISF_F3) 139 140#define S_SBISF_F4 24 /* IntFlag4 */ 141#define M_SBISF_F4 _DD_MAKEMASK(6,S_SBISF_F4) 142#define V_SBISF_F4(x) _DD_MAKEVALUE(x,S_SBISF_F4) 143#define G_SBISF_F4(x) _DD_GETVALUE(x,S_SBISF_F4,M_SBISF_F4) 144 145/* SBTSF: System Backplane Target Slave Flag Control Register (0xF18, RO) */ 146 147#define S_SBTSF_FN 0 /* SBPTSFlagNum0 */ 148#define M_SBTSF_FN _DD_MAKEMASK(6,S_SBTSF_FN) 149#define V_SBTSF_FN(x) _DD_MAKEVALUE(x,S_SBTSF_FN) 150#define G_SBTSF_FN(x) _DD_GETVALUE(x,S_SBTSF_FN,M_SBTSF_FN) 151 152#define M_SBTSF_FE _DD_MAKEMASK1(6) /* SBTPSFlag0En0 */ 153 154/* SBIS: System Backplace Initiator State Register (0xF90, R/W) */ 155 156#define S_SBIS_PC 0 /* PipeCount */ 157#define M_SBIS_PC _DD_MAKEMASK(4,S_SBIS_PC) 158#define V_SBIS_PC(x) _DD_MAKEVALUE(x,S_SBIS_PC) 159#define G_SBIS_PC(x) _DD_GETVALUE(x,S_SBIS_PC,M_SBIS_PC) 160 161#define S_SBIS_PL 4 /* Policy */ 162#define M_SBIS_PL _DD_MAKEMASK(2,S_SBIS_PL) 163#define V_SBIS_PL(x) _DD_MAKEVALUE(x,S_SBIS_PL) 164#define G_SBIS_PL(x) _DD_GETVALUE(x,S_SBIS_PL,M_SBIS_PL) 165 166#define M_SBIS_IE _DD_MAKEMASK1(17) /* InbandError */ 167#define M_SBIS_TO _DD_MAKEMASK1(18) /* TimeOut */ 168 169/* SBINT: System Backplane Interrupt Vector Register (0xF94, R/W) */ 170 171#define S_SBINT_MK 0 /* Mask */ 172#define M_SBINT_MK _DD_MAKEMASK(7,S_SBINT_MK) 173#define V_SBINT_MK(x) _DD_MAKEVALUE(x,S_SBINT_MK) 174#define G_SBINT_MK(x) _DD_GETVALUE(x,S_SBINT_MK,M_SBINT_MK) 175/* XXX For the BCM4401 */ 176#define K_SBINT_ENET_MAC (1<<1) 177 178/* SBTS(LO): System Backplane Target State Low Register (0xF98, R/W) */ 179 180#define M_SBTS_RS _DD_MAKEMASK1(0) /* Reset */ 181#define M_SBTS_RJ _DD_MAKEMASK1(1) /* Reject */ 182#define M_SBTS_CE _DD_MAKEMASK1(16) /* ClockEnable */ 183#define M_SBTS_FC _DD_MAKEMASK1(17) /* ForceGatedClocks */ 184 185#define S_SBTS_FL 18 /* Flags */ 186#define M_SBTS_FL _DD_MAKEMASK(12,S_SBTS_FL) 187#define V_SBTS_FL(x) _DD_MAKEVALUE(x,S_SBTS_FL) 188#define G_SBTS_FL(x) _DD_GETVALUE(x,S_SBTS_FL,M_SBTS_FL) 189 190#define M_SBTS_PE _DD_MAKEMASK1(30) /* PMEEnable */ 191#define M_SBTS_BE _DD_MAKEMASK1(31) /* BISTEnable */ 192 193/* USB core only */ 194#define M_SBTS_UH _DD_MAKEMASK1(29) /* USBHost */ 195 196/* SBTS(HI): System Backplane Target State High Register (0xF9C, R/W) */ 197 198#define M_SBTS_SE _DD_MAKEMASK1(0) /* SError */ 199#define M_SBTS_IN _DD_MAKEMASK1(1) /* Interrupt */ 200#define M_SBTS_BY _DD_MAKEMASK1(2) /* Busy */ 201#define M_SBTS_GC _DD_MAKEMASK1(29) /* GatedClkRequest */ 202#define M_SBTS_BF _DD_MAKEMASK1(30) /* BISTFail */ 203#define M_SBTS_BD _DD_MAKEMASK1(31) /* BISTDone */ 204 205/* SBFS: System Backplane Flag Status Register (0xFE8, RO) */ 206 207#define M_SBFS_MI _DD_MAKEMASK1(7) /* MII pins disabled */ 208 209/* SBID(LO): System Backplane Identification Low Register (0xFF8, RO) */ 210 211#define S_SBID_CS 0 /* ConfigSpace */ 212#define M_SBID_CS _DD_MAKEMASK(3,S_SBID_CS) 213#define V_SBID_CS(x) _DD_MAKEVALUE(x,S_SBID_CS) 214#define G_SBID_CS(x) _DD_GETVALUE(x,S_SBID_CS,M_SBID_CS) 215 216#define S_SBID_AR 3 /* AddressRanges */ 217#define M_SBID_AR _DD_MAKEMASK(3,S_SBID_AR) 218#define V_SBID_AR(x) _DD_MAKEVALUE(x,S_SBID_AR) 219#define G_SBID_AR(x) _DD_GETVALUE(x,S_SBID_AR,M_SBID_AR) 220 221#define M_SBID_SC _DD_MAKEMASK1(6) /* Synch */ 222#define M_SBID_IT _DD_MAKEMASK1(7) /* Initiator */ 223 224#define S_SBID_MN 8 /* MinLatency */ 225#define M_SBID_MN _DD_MAKEMASK(4,S_SBID_MN) 226#define V_SBID_MN(x) _DD_MAKEVALUE(x,S_SBID_MN) 227#define G_SBID_MN(x) _DD_GETVALUE(x,S_SBID_MN,M_SBID_MN) 228 229#define S_SBID_MX 12 /* MaxLatency */ 230#define M_SBID_MX _DD_MAKEMASK(4,S_SBID_MX) 231#define V_SBID_MX(x) _DD_MAKEVALUE(x,S_SBID_MX) 232#define G_SBID_MX(x) _DD_GETVALUE(x,S_SBID_MX,M_SBID_MX) 233 234#define M_SBID_FI _DD_MAKEMASK1(16) /* FirstInitiator */ 235#define M_SBID_NT _DD_MAKEMASK1(17) /* NoTarget */ 236 237#define S_SBID_CC 18 /* CycleCounterWidth */ 238#define M_SBID_CC _DD_MAKEMASK(2,S_SBID_CC) 239#define V_SBID_CC(x) _DD_MAKEVALUE(x,S_SBID_CC) 240#define G_SBID_CC(x) _DD_GETVALUE(x,S_SBID_CC,M_SBID_CC) 241 242#define S_SBID_TP 20 /* TargetPorts */ 243#define M_SBID_TP _DD_MAKEMASK(4,S_SBID_TP) 244#define V_SBID_TP(x) _DD_MAKEVALUE(x,S_SBID_TP) 245#define G_SBID_TP(x) _DD_GETVALUE(x,S_SBID_TP,M_SBID_TP) 246 247#define S_SBID_IP 24 /* InitPorts */ 248#define M_SBID_IP _DD_MAKEMASK(4,S_SBID_IP) 249#define V_SBID_IP(x) _DD_MAKEVALUE(x,S_SBID_IP) 250#define G_SBID_IP(x) _DD_GETVALUE(x,S_SBID_IP,M_SBID_IP) 251 252/* SBID(HI): System Backplane Identification High Register (0xFFC, RO) */ 253 254#define S_SBID_RV 0 /* Revision */ 255#define M_SBID_RV _DD_MAKEMASK(4,S_SBID_RV) 256#define V_SBID_RV(x) _DD_MAKEVALUE(x,S_SBID_RV) 257#define G_SBID_RV(x) _DD_GETVALUE(x,S_SBID_RV,M_SBID_RV) 258 259#define S_SBID_CR 4 /* Core */ 260#define M_SBID_CR _DD_MAKEMASK(12,S_SBID_CR) 261#define V_SBID_CR(x) _DD_MAKEVALUE(x,S_SBID_CR) 262#define G_SBID_CR(x) _DD_GETVALUE(x,S_SBID_CR,M_SBID_CR) 263 264#define S_SBID_VN 16 /* Vendor */ 265#define M_SBID_VN _DD_MAKEMASK(16,S_SBID_VN) 266#define V_SBID_VN(x) _DD_MAKEVALUE(x,S_SBID_VN) 267#define G_SBID_VN(x) _DD_GETVALUE(x,S_SBID_VN,M_SBID_VN) 268 269#endif /* _SBBP_H_ */ 270