1/* ********************************************************************* 2 * BCM47xx Board Support Package 3 * 4 * Board-specific initialization File: bcm94704cpci_init.S 5 * 6 * This module contains the assembly-language part of the init 7 * code for this board support package. The routine 8 * "board_earlyinit" lives here. 9 * 10 ********************************************************************* 11 * 12 * Copyright 2000,2001,2002,2003 13 * Broadcom Corporation. All rights reserved. 14 * 15 * This software is furnished under license and may be used and 16 * copied only in accordance with the following terms and 17 * conditions. Subject to these conditions, you may download, 18 * copy, install, use, modify and distribute modified or unmodified 19 * copies of this software in source and/or binary form. No title 20 * or ownership is transferred hereby. 21 * 22 * 1) Any source code used, modified or distributed must reproduce 23 * and retain this copyright notice and list of conditions 24 * as they appear in the source file. 25 * 26 * 2) No right is granted to use any trade name, trademark, or 27 * logo of Broadcom Corporation. The "Broadcom Corporation" 28 * name may not be used to endorse or promote products derived 29 * from this software without the prior written permission of 30 * Broadcom Corporation. 31 * 32 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 33 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 34 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 35 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 36 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 37 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 38 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 40 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 41 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 42 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 43 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 44 * THE POSSIBILITY OF SUCH DAMAGE. 45 ********************************************************************* */ 46 47 48#include "endian.h" 49#include "cpu_config.h" 50#include "sbmips32.h" 51#include "sb_bp.h" 52#include "sb_chipc.h" 53#include "bsp_config.h" 54 55 .text 56 57/* ********************************************************************* 58 * Macros 59 ********************************************************************* */ 60 61/* LED digits are selected by M_ADDR[4:3] in this revision. */ 62 63#define LED_DIGIT(n) ((n)<<3) 64 65 66/* ********************************************************************* 67 * BOARD_EARLYINIT() 68 * 69 * Initialize board registers. This is the earliest 70 * time the BSP gets control. This routine cannot assume that 71 * memory is operational, and therefore all code in this routine 72 * must run from registers only. The $ra register must not 73 * be modified, as it contains the return address. 74 * 75 * This routine will be called from uncached space, before 76 * the caches are initialized. If you want to make 77 * subroutine calls from here, you must use the CALLKSEG1 macro. 78 * 79 * Among other things, this is where the GPIO registers get 80 * programmed to make on-board LEDs function, or other startup 81 * that has to be done before anything will work. 82 * 83 * Input parameters: 84 * nothing 85 * 86 * Return value: 87 * nothing 88 ********************************************************************* */ 89 90LEAF(board_earlyinit) 91 92 93 # 94 # Configure the external interface so we can access LEDs, etc. 95 # 96 97 li a2, PHYS_TO_K1(SB_CHIPC_BASE) 98 99 # 100 # CS0 is used to access the following devices: 101 # alphanumeric LEDs (Osram slr2016) 102 # TOD/NVRAM (Dallas ds1743) 103 # 104 # To avoid the various chipc/UART errata, the suggested workaround 105 # is to set w1+w3 < 7. We set w1 = 2 and w3 = 4 below; the w3 value 106 # is out of spec for the LEDs at backplane frequencies above 100 MHz, 107 # but the PLD (Altera epm7032ae) effectively extends w3 by its 108 # (unspecified) minimum propagation delay. 109 # 110 111 li a3, (V_CS_EM(2) | M_CS_EN) /* enable the leds */ 112 sw a3, R_CS01CONFIG(a2) 113 li a3, (V_CS_W0(16)|V_CS_W1(2)|V_CS_W2(14)|V_CS_W3(4)) 114 sw a3, R_CS01MEMWAITCNT(a2) /* 0x040E0210 */ 115 116 li a3, M_CS_EN /* enable alt flash */ 117 sw a3, R_CS4CONFIG(a2) 118 li a3, (V_CS_W0(16)|V_CS_W1(2)|V_CS_W2(14)|V_CS_W3(4)) 119 sw a3, R_CS4WAITCNT(a2) /* 0x040E0210 */ 120 121 # 122 # Use CP0 Diagnostic Register to turn on the caches (I$ and D$) 123 # 124 mfc0 v0,C0_DIAGNOSTIC 125 or v0,(M_BCM0_DE | M_BCM0_IE) 126 mtc0 v0,C0_DIAGNOSTIC 127 128 li a2, PHYS_TO_K1(BCM95836_CPCI_LED_ADDR) 129 li a3, 0x2A 130 sw a3, LED_DIGIT(0)(a2) 131 132 jr ra 133 134 135END(board_earlyinit) 136 137 138/* ********************************************************************* 139 * BOARD_SETLEDS(x) 140 * 141 * Set LEDs for boot-time progress indication. Not used if 142 * the board does not have progress LEDs. This routine 143 * must not call any other routines, since it may be invoked 144 * either from KSEG0 or KSEG1 and it may be invoked 145 * whether or not the icache is operational. 146 * 147 * Input parameters: 148 * a0 - LED value (8 bits per character, 4 characters) 149 * 150 * Return value: 151 * nothing 152 * 153 * Registers used: 154 * t0 155 ********************************************************************* */ 156 157 158LEAF(board_setleds) 159 160 li t0,PHYS_TO_K1(BCM95836_CPCI_LED_ADDR) 161 rol a0,a0,8 162 sb a0,LED_DIGIT(3)(t0) 163 rol a0,a0,8 164 sb a0,LED_DIGIT(2)(t0) 165 rol a0,a0,8 166 sb a0,LED_DIGIT(1)(t0) 167 rol a0,a0,8 168 sb a0,LED_DIGIT(0)(t0) 169 j ra 170 171END(board_setleds) 172 173 174 175/* ********************************************************************* 176 * Misc functions 177 ********************************************************************* */ 178 179 .set mips32 180 181 .globl read_config0 182read_config0: 183 mfc0 v0,C0_CONFIG,0 184 j ra 185 186 .globl read_config1 187read_config1: 188 mfc0 v0,C0_CONFIG,1 189 j ra 190 191 .globl read_bcm0 192read_bcm0: 193 mfc0 v0,C0_BRCMCFG,0 194 j ra 195 196 .globl read_bcm1 197read_bcm1: 198 mfc0 v0,C0_BRCMCFG,1 199 j ra 200 201 .globl read_bcm2 202read_bcm2: 203 mfc0 v0,C0_BRCMCFG,2 204 j ra 205 206 .globl read_bcm3 207read_bcm3: 208 mfc0 v0,C0_BRCMCFG,3 209 j ra 210 211 .globl read_bcm4 212read_bcm4: 213 mfc0 v0,C0_BRCMCFG,4 214 j ra 215 216 .globl read_bcm5 217read_bcm5: 218 mfc0 v0,C0_BRCMCFG,5 219 j ra 220 221 .globl read_bcm6 222read_bcm6: 223 mfc0 v0,C0_BRCMCFG,6 224 j ra 225 226 .globl read_bcm7 227read_bcm7: 228 mfc0 v0,C0_BRCMCFG,7 229 j ra 230