1/* ********************************************************************* 2 * BCM1280/BCM1480 Board Support Package 3 * 4 * BCM91480HT Definitions File: bcm91480ht.h 5 * 6 * This file contains I/O, chip select, and GPIO assignments 7 * for the BCM1255/BCM1280/BCM1455/BCM1480 evaluation board. 8 * 9 * Author: Binh Vo 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49/* 50 * I/O Address assignments for the bcm91480ht board 51 * 52 * Summary of address map: 53 * 54 * Address Size CSel Description 55 * --------------- ---- ------ -------------------------------- 56 * 0x1FC00000 4MB CS0 Boot ROM 57 * 0x1F800000 4MB CS1 Alternate Boot ROM 58 * CS2 Unused 59 * 0x100A0000 64KB CS4 LED display 60 * 0x100C0000 64KB CS5 CPLD and Battery Backup Control 61 * CS6 Unused 62 * CS7 Unused 63 * 64 * GPIO assignments 65 * 66 * GPIO# Direction Description 67 * ------- --------- ------------------------------------------ 68 * GPIO0 Input HT2000 Fatal 69 * GPIO1 Input HT2000 Alert 70 * GPIO2 Input HT1000 CPU Reset 71 * GPIO3 Output PCIX_CLKSEL1 72 * GPIO4 Output PCIX_CLKSEL0 73 * GPIO5 Input Temperature Sensor Alert 74 * GPIO6 Input HT2000GEIRQ1 75 * GPIO7 Input HT2000GEIRQ2 76 * GPIO8 Input SPI0 Reset 77 * GPIO9 Input PCIE_IRQ0 78 * GPIO10 Input PCIE_IRQ1 79 * GPIO11 Input PCIE_IRQ2 80 * GPIO12 Input PCIE_IRQ3 81 * GPIO13 Input Power Fail 82 * GPIO14 Input Charger IRQ 83 * GPIO15 Input SPI1 Reset 84 * 85 * SMBus assignments: 86 * 87 * Chan Dev Description 88 * ---- ------ ------------------------------------------ 89 * 0 0x70 SMBus switch 90 * 0 0x09 Charger 1759 91 * 0 0x44 A2D 92 * 0 0x Battery pack 93 * 0 0x51 MC chan 2 / J25 94 * 0 0x52 MC chan 2 / J5 95 * 0 0x55 MC chan 3 / J25 96 * 0 0x56 MC chan 3 / J5 97 * 0 0x57 MC chan 0 / J4 98 * 0 0x53 MC chan 1 / J4 99 * 1 0x70 SMBus switch 100 * 1 0x50 Microchip 24LC128 SMBus EEPROM 101 * 1 0x51 Microchip 24LC128 SMBus EEPROM 102 * 1 0x4c AD ADT7461AR Temperature Sensor 103 * 1 0x68 ST Micro M41T81M Real-time clock 104 * 1 0x6E CLK SYNTH 9FG104 105 */ 106 107/* ********************************************************************* 108 * Macros 109 ********************************************************************* */ 110 111#define MB (1024*1024) 112#define K64 65536 113#define NUM64K(x) (((x)+(K64-1))/K64) 114 115 116/* ********************************************************************* 117 * GPIO pins 118 ********************************************************************* */ 119 120#define GPIO_HT200O_FATAL 0 121#define GPIO_HT2000_ALERT 1 122#define GPIO_HT1000_RESET 2 123#define GPIO_PCIX_CLKSEL0 3 124#define GPIO_PCIX_CLKSEL1 4 125#define GPIO_TEMP_SENSOR 5 126#define GPIO_HT2000_IRQ1 6 127#define GPIO_HT2000_IRQ2 7 128#define GPIO_SPIO_RESET 8 129#define GPIO_PCIE_IRQ3 9 130#define GPIO_PCIE_IRQ2 10 131#define GPIO_PCIE_IRQ1 11 132#define GPIO_PCIE_IRQ0 12 133#define GPIO_POWER_FAIL 13 134#define GPIO_CHARGER_IRQ 14 135#define GPIO_SPI1_RESET 15 136 137#define M_GPIO_HT200O_FATAL _SB_MAKEMASK1(GPIO_HT200O_FATAL) 138#define M_GPIO_HT2000_ALERT _SB_MAKEMASK1(GPIO_HT2000_ALERT) 139#define M_GPIO_HT1000_RESET _SB_MAKEMASK1(GPIO_HT1000_RESET) 140#define M_GPIO_PCIX_CLKSEL0 _SB_MAKEMASK1(GPIO_PCIX_CLKSEL0) 141#define M_GPIO_PCIX_CLKSEL1 _SB_MAKEMASK1(GPIO_PCIX_CLKSEL1) 142#define M_GPIO_TEMP_SENSOR _SB_MAKEMASK1(GPIO_TEMP_SENSOR) 143#define M_GPIO_HT2000_IRQ1 _SB_MAKEMASK1(GPIO_HT2000_IRQ1) 144#define M_GPIO_HT2000_IRQ2 _SB_MAKEMASK1(GPIO_HT2000_IRQ2) 145#define M_GPIO_SPIO_RESET _SB_MAKEMASK1(GPIO_SPIO_RESET) 146#define M_GPIO_PCIE_IRQ3 _SB_MAKEMASK1(GPIO_PCIE_IRQ3) 147#define M_GPIO_PCIE_IRQ2 _SB_MAKEMASK1(GPIO_PCIE_IRQ2) 148#define M_GPIO_PCIE_IRQ1 _SB_MAKEMASK1(GPIO_PCIE_IRQ1) 149#define M_GPIO_PCIE_IRQ0 _SB_MAKEMASK1(GPIO_PCIE_IRQ0) 150#define M_GPIO_POWER_FAIL _SB_MAKEMASK1(GPIO_POWER_FAIL) 151#define M_GPIOCHARGER_IRQ_ _SB_MAKEMASK1(GPIO_CHARGER_IRQ) 152#define M_GPIO_SPI1_RESET _SB_MAKEMASK1(GPIO_SPI1_RESET) 153 154/* Leave bidirectional pins in "input" state at boot. */ 155 156#define GPIO_OUTPUT_MASK (M_GPIO_PCIX_CLKSEL0 | \ 157 M_GPIO_PCIX_CLKSEL1) 158 159#define GPIO_INTERRUPT_MASK (0) 160 161/* used for resetting */ 162#define M_GPIO_PCIX_FREQALL (M_GPIO_PCIX_CLKSEL0 | \ 163 M_GPIO_PCIX_CLKSEL1) 164 165/* 166 * Frequency Settings: 167 * P1 P0 Frequency 168 * 0 0 33MHz 169 * 0 1 66MHz 170 * 1 0 100MHz 171 * 1 1 133MHz 172 */ 173 174#define M_GPIO_PCIX_FREQ133 (M_GPIO_PCIX_CLKSEL0 | \ 175 M_GPIO_PCIX_CLKSEL1) 176 177#define M_GPIO_PCIX_FREQ100 (M_GPIO_PCIX_CLKSEL1) 178 179#define M_GPIO_PCIX_FREQ66 (M_GPIO_PCIX_CLKSEL0) 180 181#define M_GPIO_PCIX_FREQ33 (0) 182 183 184/* ********************************************************************* 185 * Generic Bus 186 ********************************************************************* */ 187 188/* 189 * Boot ROM: non-multiplexed, byte width, no parity, no ack 190 * XXX: These are the (very slow) default parameters. This can be sped up! 191 */ 192#define BOOTROM_CS 0 193#define BOOTROM_PHYS 0x1FC00000 /* address of boot ROM (CS0) */ 194#define BOOTROM_SIZE NUM64K(4*MB) /* size of boot ROM */ 195#define BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 196 V_IO_ALE_TO_CS(2) | \ 197 V_IO_CS_WIDTH(24) | \ 198 V_IO_RDY_SMPLE(1) 199#define BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 200 V_IO_WRITE_WIDTH(7) | \ 201 V_IO_IDLE_CYCLE(6) | \ 202 V_IO_CS_TO_OE(0) | \ 203 V_IO_OE_TO_CS(0) 204#define BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 205 206/* 207 * Alternate Boot ROM: non-multiplexed, byte width, no parity, no ack 208 * XXX: These are the (very slow) default parameters. This can be sped up! 209 */ 210#define ALT_BOOTROM_CS 1 211#define ALT_BOOTROM_PHYS 0x1F800000 /* address of alternate boot ROM (CS1) */ 212#define ALT_BOOTROM_SIZE NUM64K(4*MB) /* size of alternate boot ROM */ 213#define ALT_BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 214 V_IO_ALE_TO_CS(2) | \ 215 V_IO_CS_WIDTH(24) | \ 216 V_IO_RDY_SMPLE(1) 217#define ALT_BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 218 V_IO_WRITE_WIDTH(7) | \ 219 V_IO_IDLE_CYCLE(6) | \ 220 V_IO_CS_TO_OE(0) | \ 221 V_IO_OE_TO_CS(0) 222#define ALT_BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 223 224/* 225 * LEDs: non-multiplexed, byte width, no parity, no ack 226 * 227 */ 228#define LEDS_CS 4 229#define LEDS_PHYS 0x100A0000 /* same address as SWARM */ 230#define LEDS_SIZE NUM64K(4) 231#define LEDS_TIMING0 V_IO_ALE_WIDTH(4) | \ 232 V_IO_ALE_TO_CS(2) | \ 233 V_IO_CS_WIDTH(13) | \ 234 V_IO_RDY_SMPLE(1) 235#define LEDS_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 236 V_IO_WRITE_WIDTH(8) | \ 237 V_IO_IDLE_CYCLE(6) | \ 238 V_IO_CS_TO_OE(0) | \ 239 V_IO_OE_TO_CS(0) 240#define LEDS_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 241 242/* 243 * Battery backup settings: non-multiplexed, byte width, no parity, no ack 244 * 245 */ 246#define BATTERY_CS 5 247#define BATTERY_PHYS 0x100C0000 /* same address as SWARM */ 248#define BATTERY_SIZE NUM64K(4) 249#define BATTERY_TIMING0 V_IO_ALE_WIDTH(4) | \ 250 V_IO_ALE_TO_CS(2) | \ 251 V_IO_CS_WIDTH(13) | \ 252 V_IO_RDY_SMPLE(1) 253#define BATTERY_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 254 V_IO_WRITE_WIDTH(8) | \ 255 V_IO_IDLE_CYCLE(6) | \ 256 V_IO_CS_TO_OE(0) | \ 257 V_IO_OE_TO_CS(0) 258#define BATTERY_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 259 260 261 262/* ********************************************************************* 263 * SMBus Devices 264 ********************************************************************* */ 265 266#define TEMPSENSOR_SMBUS_CHAN 1 267#define TEMPSENSOR_SMBUS_DEV 0x4c 268 269#define BIGEEPROM_SMBUS_CHAN_1 1 /* This one is for CFE */ 270#define BIGEEPROM_SMBUS_DEV_1 0x51 271 272#define BIGEEPROM_SMBUS_CHAN 1 /* This one is for customer use */ 273#define BIGEEPROM_SMBUS_DEV 0x50 274 275#define M41T81_SMBUS_CHAN 1 276#define M41T81_SMBUS_DEV 0x68 277 278#define CLK_SYNTH_CHAN 1 279#define CLK_SYNTH_DEV 0x6E 280 281#define SMBUS_SWITCH_CHAN_0 0 282#define SMBUS_SWITCH_DEV_0 0x70 283 284#define SMBUS_SWITCH_CHAN_1 1 285#define SMBUS_SWITCH_DEV_1 0x70 286 287#define CHARGER_CHAN 0 288#define CHARGER_DEV 0x09 289 290#define A2D_CHAN 0 291#define A2D_DEV 0x44 292 293#define BATTERY_CHAN 294#define BATTERY_DEV 295 296 297#define DRAM_SMBUS_CHAN_J4_0 0 298#define DRAM_SMBUS_DEV_J4_0 0x57 299#define DRAM_SMBUS_CHAN_J4_1 0 300#define DRAM_SMBUS_DEV_J4_1 0x53 301 302#define DRAM_SMBUS_CHAN_J5_2 0 303#define DRAM_SMBUS_DEV_J5_2 0x52 304#define DRAM_SMBUS_CHAN_J5_3 0 305#define DRAM_SMBUS_DEV_J5_3 0x56 306 307#define DRAM_SMBUS_CHAN_J25_2 0 308#define DRAM_SMBUS_DEV_J25_2 0x51 309#define DRAM_SMBUS_CHAN_J25_3 0 310#define DRAM_SMBUS_DEV_J25_3 0x55 311 312 313/* ********************************************************************* 314 * FPGA defines 315 ********************************************************************* */ 316 317/* 318 * These registers are implemented on all BCM91480HT boards. 319 */ 320 321#define FPGA_PHYS_SREG0 (FPGA_PHYS + 0) 322#define FPGA_PHYS_SREG1 (FPGA_PHYS + 1) 323 324#define FPGA_SREG0_SWM4 0x01 325#define FPGA_SREG0_SWM5 0x02 326#define FPGA_SREG0_SWM6 0x04 327#define FPGA_SREG0_SWM7 0x08 328#define FPGA_SREG0_ROM_CS_SEL 0x10 /* set -> ROM */ 329/* reserved 0x20 */ 330/* reserved 0x40 */ 331/* reserved 0x80 */ 332 333#define FPGA_SREG1_HT_EN_L0 0x01 334#define FPGA_SREG1_HT_EN_L1 0x02 335#define FPGA_SREG1_SPI_EN_L0 0x04 336#define FPGA_SREG1_SPI_EN_L1 0x08 337#define FPGA_SREG1_LVDS_EN_L0 0x10 338#define FPGA_SREG1_LVDS_EN_L1 0x20 339/* reserved 0x40 */ 340/* reserved 0x80 */ 341 342/* ********************************************************************* 343 * Board revision numbers 344 ********************************************************************* */ 345 346/* Maps from SYSTEM_CFG config[1:0] register to actual board rev #'s */ 347 348#define BOARD_REV_1 0 349 350 351/* ********************************************************************* 352 * Board configuration switches 353 ********************************************************************* */ 354 355#define BOARD_CFG_REV_MASK 0x03 356 357#define BOARD_CFG_SWM0 0x04 358#define BOARD_CFG_SWM1 0x08 359#define BOARD_CFG_SWM2 0x10 360#define BOARD_CFG_SWM3 0x20 361 362#define BOARD_CFG_SWM4 (FPGA_SREG0_SWM4 << 8) 363#define BOARD_CFG_SWM5 (FPGA_SREG0_SWM5 << 8) 364#define BOARD_CFG_SWM6 (FPGA_SREG0_SWM6 << 8) 365#define BOARD_CFG_SWM7 (FPGA_SREG0_SWM7 << 8) 366#define BOARD_CFG_ROM_CS_SEL (FPGA_SREG0_ROM_CS_SEL << 8) 367 368#define BOARD_CFG_HT_EN_L0 (FPGA_SREG1_HT_EN_L0 << 16) 369#define BOARD_CFG_HT_EN_L1 (FPGA_SREG1_HT_EN_L1 << 16) 370#define BOARD_CFG_SPI_EN_L0 (FPGA_SREG1_SPI_EN_L0 << 16) 371#define BOARD_CFG_SPI_EN_L1 (FPGA_SREG1_SPI_EN_L1 << 16) 372#define BOARD_CFG_LVDS_EN_L0 (FPGA_SREG1_LVDS_EN_L0 << 16) 373#define BOARD_CFG_LVDS_EN_L1 (FPGA_SREG1_LVDS_EN_L1 << 16) 374 375 376/* Console type: 1 bit for now, maybe 2 later. */ 377#define BOARD_CFG_CONS_MASK BOARD_CFG_SWM0 378 379#define BOARD_CFG_CONS_UART0 0 /* UART0 */ 380#define BOARD_CFG_CONS_PROMICE BOARD_CFG_SWM0 /* PromICE */ 381 382/* HT node identification: 1 bit for now. */ 383#define BOARD_CFG_NODE_ID BOARD_CFG_SWM1 384 385/* Set if PCI/HT should be initialized. */ 386#define BOARD_CFG_INIT_PCI BOARD_CFG_SWM2 387 388/* Set if STARTUP environment variable should be used. */ 389#define BOARD_CFG_DO_STARTUP BOARD_CFG_SWM3 390 391#ifdef __LANGUAGE_C 392int board_get_config(void); 393#endif 394 395 396 397 398