1/* ********************************************************************* 2 * BCM1280/BCM1480 Board Support Package 3 * 4 * BCM91280E Definitions File: bcm91280e.h 5 * 6 * This file contains I/O, chip select, and GPIO assignments 7 * for the BCM1255/BCM1280/BCM1455/BCM1480 evaluation board. 8 * 9 * Author: Mitch Lichtenberg 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2005 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49/* 50 * I/O Address assignments for the bcm91280e board 51 * 52 * Summary of address map: 53 * 54 * Address Size CSel Description 55 * --------------- ---- ------ -------------------------------- 56 * 0x1FC00000 4MB CS0 Boot ROM 57 * 0x1F800000 4MB CS1 Alternate Boot ROM 58 * CS2 Unused 59 * CS3 Unused 60 * 0x100A0000 64KB CS4 LED display 61 * CS5 Unused 62 * CS6 Unused 63 * CS7 Unused 64 * 65 * GPIO assignments (GPIOs 9-15 connected to DIP switches) 66 * 67 * GPIO# Direction Description 68 * ------- --------- ------------------------------------------ 69 * GPIO0 70 * GPIO1 71 * GPIO2 72 * GPIO3 73 * GPIO4 74 * GPIO5 Input Temperature Sensor Alert 75 * GPIO6 76 * GPIO7 77 * GPIO8 78 * GPIO9 Input EXT_SWM8 79 * GPIO10 Input EXT_SWM7 80 * GPIO11 Input EXT_SWM6 81 * GPIO12 Input EXT_SWM5 82 * GPIO13 Input EXT_SWM4 83 * GPIO14 Input ROM_CS_SEL 84 * GPIO15 Input BFWP_H 85 * 86 * SMBus assignments: 87 * 88 * Chan Dev Description 89 * ---- ------ ------------------------------------------ 90 * 0 0x50 Microchip 24LC128 SMBus EEPROM 91 * 1 0x51 Microchip 24LC128 SMBus EEPROM 92 * 1 0x26 AD ADT7461AR Temperature Sensor 93 * 1 0x57 ST Micro M41T81M Real-time clock 94 */ 95 96/* ********************************************************************* 97 * Macros 98 ********************************************************************* */ 99 100#define MB (1024*1024) 101#define K64 65536 102#define NUM64K(x) (((x)+(K64-1))/K64) 103 104 105/* ********************************************************************* 106 * GPIO pins 107 ********************************************************************* */ 108 109#define GPIO_TEMP_SENSOR 5 110 111#define M_GPIO_TEMP_SENSOR _SB_MAKEMASK1(GPIO_TEMP_SENSOR) 112 113/* Leave bidirectional pins in "input" state at boot. */ 114 115#define GPIO_OUTPUT_MASK (0) 116 117#define GPIO_INTERRUPT_MASK (0) 118 119/* ********************************************************************* 120 * Generic Bus 121 ********************************************************************* */ 122 123/* 124 * Boot ROM: non-multiplexed, byte width, no parity, no ack 125 * XXX: These are the (very slow) default parameters. This can be sped up! 126 */ 127#define BOOTROM_CS 0 128#define BOOTROM_PHYS 0x1FC00000 /* address of boot ROM (CS0) */ 129#define BOOTROM_SIZE NUM64K(4*MB) /* size of boot ROM */ 130#define BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 131 V_IO_ALE_TO_CS(2) | \ 132 V_IO_CS_WIDTH(24) | \ 133 V_IO_RDY_SMPLE(1) 134#define BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 135 V_IO_WRITE_WIDTH(7) | \ 136 V_IO_IDLE_CYCLE(6) | \ 137 V_IO_CS_TO_OE(0) | \ 138 V_IO_OE_TO_CS(0) 139#define BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 140 141/* 142 * Alternate Boot ROM: non-multiplexed, byte width, no parity, no ack 143 * XXX: These are the (very slow) default parameters. This can be sped up! 144 */ 145#define ALT_BOOTROM_CS 1 146#define ALT_BOOTROM_PHYS 0x1F800000 /* address of alternate boot ROM (CS1) */ 147#define ALT_BOOTROM_SIZE NUM64K(4*MB) /* size of alternate boot ROM */ 148#define ALT_BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 149 V_IO_ALE_TO_CS(2) | \ 150 V_IO_CS_WIDTH(24) | \ 151 V_IO_RDY_SMPLE(1) 152#define ALT_BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 153 V_IO_WRITE_WIDTH(7) | \ 154 V_IO_IDLE_CYCLE(6) | \ 155 V_IO_CS_TO_OE(0) | \ 156 V_IO_OE_TO_CS(0) 157#define ALT_BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 158 159/* 160 * LEDs: non-multiplexed, byte width, no parity, no ack 161 * 162 */ 163#define LEDS_CS 4 164#define LEDS_PHYS 0x100A0000 /* same address as SWARM */ 165#define LEDS_SIZE NUM64K(4) 166#define LEDS_TIMING0 V_IO_ALE_WIDTH(4) | \ 167 V_IO_ALE_TO_CS(2) | \ 168 V_IO_CS_WIDTH(13) | \ 169 V_IO_RDY_SMPLE(1) 170#define LEDS_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 171 V_IO_WRITE_WIDTH(8) | \ 172 V_IO_IDLE_CYCLE(6) | \ 173 V_IO_CS_TO_OE(0) | \ 174 V_IO_OE_TO_CS(0) 175#define LEDS_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 176 177/* ********************************************************************* 178 * SMBus Devices 179 ********************************************************************* */ 180 181#define TEMPSENSOR_SMBUS_CHAN 1 182#define TEMPSENSOR_SMBUS_DEV 0x4C 183 184#define BIGEEPROM_SMBUS_CHAN_1 1 /* This one is for CFE */ 185#define BIGEEPROM_SMBUS_DEV_1 0x51 186 187#define BIGEEPROM_SMBUS_CHAN 0 /* This one is for customer use */ 188#define BIGEEPROM_SMBUS_DEV 0x50 189 190#define M41T81_SMBUS_CHAN 1 191#define M41T81_SMBUS_DEV 0x57 192 193/* ********************************************************************* 194 * Board revision numbers 195 ********************************************************************* */ 196 197/* Maps from SYSTEM_CFG config[1:0] register to actual board rev #'s */ 198 199#define BOARD_REV_0 0 200 201 202/* ********************************************************************* 203 * Board configuration switches 204 ********************************************************************* */ 205 206/* 207 * The board revision and configuration switches are in config[5:0] 208 * They can be obtained by calling the board_get_config() function, 209 * which returns them as: 210 * return value bits [ 5: 0]: config[5:0]. 211 */ 212 213#define BOARD_CFG_REV_MASK 0x03 214#define BOARD_CFG_SWM0 0x04 215#define BOARD_CFG_SWM1 0x08 216#define BOARD_CFG_SWM2 0x10 217#define BOARD_CFG_SWM3 0x20 218 219#define BOARD_CFG_SWM4 0 220#define BOARD_CFG_SWM5 0 221#define BOARD_CFG_SWM6 0 222#define BOARD_CFG_SWM7 0 223#define BOARD_CFG_SWM8 0 224 225/* Console type: 1 bit for now, maybe 2 later. */ 226#define BOARD_CFG_CONS_MASK BOARD_CFG_SWM0 227 228#define BOARD_CFG_CONS_UART0 0 /* UART0 */ 229#define BOARD_CFG_CONS_PROMICE BOARD_CFG_SWM0 /* PromICE */ 230 231/* Reserved: BOARD_CFG_SWM1 */ 232 233/* Set if PCI/HT should be initialized. */ 234#define BOARD_CFG_INIT_PCI BOARD_CFG_SWM2 235 236/* Set if STARTUP environment variable should be used. */ 237#define BOARD_CFG_DO_STARTUP BOARD_CFG_SWM3 238 239/* Disable all but half of L2 cache. */ 240#define BOARD_CFG_HALF_L2 BOARD_CFG_SWM4 241 242/* Disable all but two CPUs. */ 243#define BOARD_CFG_2CPU BOARD_CFG_SWM5 244 245/* Reserved: BOARD_CFG_SWM6 */ 246 247#ifdef __LANGUAGE_C 248int board_get_config(void); 249#endif 250