1/*  *********************************************************************
2    *  SB1250 Board Support Package
3    *
4    *  BCM1250CPCI  Definitions   		   File: bcm1250cpci.h
5    *
6    *  This file contains I/O, chip select, and GPIO assignments
7    *  for the BCM1250CPCI evaluation board.
8    *
9    *  Author:  Mitch Lichtenberg
10    *
11    *********************************************************************
12    *
13    *  Copyright 2000,2001,2002,2003
14    *  Broadcom Corporation. All rights reserved.
15    *
16    *  This software is furnished under license and may be used and
17    *  copied only in accordance with the following terms and
18    *  conditions.  Subject to these conditions, you may download,
19    *  copy, install, use, modify and distribute modified or unmodified
20    *  copies of this software in source and/or binary form.  No title
21    *  or ownership is transferred hereby.
22    *
23    *  1) Any source code used, modified or distributed must reproduce
24    *     and retain this copyright notice and list of conditions
25    *     as they appear in the source file.
26    *
27    *  2) No right is granted to use any trade name, trademark, or
28    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
29    *     name may not be used to endorse or promote products derived
30    *     from this software without the prior written permission of
31    *     Broadcom Corporation.
32    *
33    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
34    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
35    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
36    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
37    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
38    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
39    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
41    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
42    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
43    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
44    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
45    *     THE POSSIBILITY OF SUCH DAMAGE.
46    ********************************************************************* */
47
48
49/*
50 * I/O Address assignments for the BCM1250CPCI board
51 *
52 * Summary of address map:
53 *
54 * Address         Size   CSel    Description
55 * --------------- ----   ------  --------------------------------
56 * 0x1FC00000      4MB     CS0    Boot ROM
57 * 0x1F800000      4MB     CS1    Alternate boot ROM
58 *                         CS2    Unused
59 * 0x100A0000      64KB    CS3    LED Display
60 * 0x100B0000      64KB    CS4    IDE disk
61 * 0x100C0000      64KB    CS5    USB controller
62 * 0x11000000      64MB    CS6    PCMCIA
63 * 0x100D0000      64KB    CS7    CPCI CPLD
64 *
65 * GPIO assignments
66 *
67 * GPIO#    Direction   Description
68 * -------  ---------   ------------------------------------------
69 * GPIO0    Input       USB Interrupt (interrupt)
70 * GPIO1    Input       USB EXT_INT_L (interrupt)
71 * GPIO2    Input	PHY Interrupt (interrupt)
72 * GPIO3    Input	CPCI Interrupt (interrupt)
73 * GPIO4    Input       IDE Interrupt (interrupt)
74 * GPIO5    Input       Temperature Sensor Alert (interrupt)
75 * GPIO6    N/A         PCMCIA interface
76 * GPIO7    N/A         PCMCIA interface
77 * GPIO8    N/A         PCMCIA interface
78 * GPIO9    N/A         PCMCIA interface
79 * GPIO10   N/A         PCMCIA interface
80 * GPIO11   N/A         PCMCIA interface
81 * GPIO12   N/A         PCMCIA interface
82 * GPIO13   N/A         PCMCIA interface
83 * GPIO14   N/A         PCMCIA interface
84 * GPIO15   N/A         PCMCIA interface
85 */
86
87/*  *********************************************************************
88    *  Macros
89    ********************************************************************* */
90
91#define MB (1024*1024)
92#define K64 65536
93#define NUM64K(x) (((x)+(K64-1))/K64)
94
95
96/*  *********************************************************************
97    *  GPIO pins
98    ********************************************************************* */
99
100#define GPIO_USB_INTERRUPT	0
101#define GPIO_USB_EXT_INT	1
102#define GPIO_PHY_INTERRUPT	2
103#define GPIO_CPCI_INTERRUPT	3
104#define GPIO_IDE_INTERRUPT	4
105#define GPIO_TEMP_SENSOR_INT	5
106
107#define M_GPIO_USB_INTERRUPT	_SB_MAKEMASK1(GPIO_USB_INTERRUPT)
108#define M_GPIO_USB_EXT_INT	_SB_MAKEMASK1(GPIO_USB_EXT_INT)
109#define M_GPIO_PHY_INTERRUPT	_SB_MAKEMASK1(GPIO_PHY_INTERRUPT)
110#define M_GPIO_CPCI_INTERRUPT	_SB_MAKEMASK1(GPIO_CPCI_INTERRUPT)
111#define M_GPIO_IDE_INTERRUPT	_SB_MAKEMASK1(GPIO_IDE_INTERRUPT)
112#define M_GPIO_TEMP_SENSOR_INT	_SB_MAKEMASK1(GPIO_TEMP_SENSOR_INT)
113
114/* Leave bidirectional pins in "input" state at boot. */
115
116#define GPIO_OUTPUT_MASK (0)	/* all non-PCMCIA pins are interrupts */
117
118
119#define GPIO_INTERRUPT_MASK ((V_GPIO_INTR_TYPEX(GPIO_USB_INTERRUPT,K_GPIO_INTR_LEVEL)) | \
120                             (V_GPIO_INTR_TYPEX(GPIO_PHY_INTERRUPT,K_GPIO_INTR_LEVEL)) | \
121                             (V_GPIO_INTR_TYPEX(GPIO_IDE_INTERRUPT,K_GPIO_INTR_LEVEL)))
122
123
124
125/*  *********************************************************************
126    *  Generic Bus
127    ********************************************************************* */
128
129/*
130 * Boot ROM:  non-multiplexed, byte width, no parity, no ack
131 * XXX: These are the (very slow) default parameters.   This can be sped up!
132 */
133#define BOOTROM_CS		0
134#define BOOTROM_PHYS		0x1FC00000	/* address of boot ROM (CS0) */
135#define BOOTROM_SIZE		NUM64K(4*MB)	/* size of boot ROM */
136#define BOOTROM_TIMING0		V_IO_ALE_WIDTH(4) | \
137                                V_IO_ALE_TO_CS(2) | \
138                                V_IO_CS_WIDTH(24) | \
139                                V_IO_RDY_SMPLE(1)
140#define BOOTROM_TIMING1		V_IO_ALE_TO_WRITE(7) | \
141                                V_IO_WRITE_WIDTH(7) | \
142                                V_IO_IDLE_CYCLE(6) | \
143                                V_IO_CS_TO_OE(0) | \
144                                V_IO_OE_TO_CS(0)
145#define BOOTROM_CONFIG		V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
146
147/*
148 * Alternate Boot ROM:  non-multiplexed, byte width, no parity, no ack
149 * XXX: These are the (very slow) default parameters.   This can be sped up!
150 */
151#define ALT_BOOTROM_CS		1
152#define ALT_BOOTROM_PHYS	0x1F800000	/* address of alternate boot ROM (CS1) */
153#define ALT_BOOTROM_SIZE	NUM64K(4*MB)	/* size of alternate boot ROM */
154#define ALT_BOOTROM_TIMING0	V_IO_ALE_WIDTH(4) | \
155                                V_IO_ALE_TO_CS(2) | \
156                                V_IO_CS_WIDTH(24) | \
157                                V_IO_RDY_SMPLE(1)
158#define ALT_BOOTROM_TIMING1	V_IO_ALE_TO_WRITE(7) | \
159                                V_IO_WRITE_WIDTH(7) | \
160                                V_IO_IDLE_CYCLE(6) | \
161                                V_IO_CS_TO_OE(0) | \
162                                V_IO_OE_TO_CS(0)
163#define ALT_BOOTROM_CONFIG	V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
164
165
166/*
167 * LEDs:  non-multiplexed, byte width, no parity, no ack
168 */
169#define LEDS_CS			3
170#define LEDS_PHYS		0x100A0000
171#define LEDS_SIZE		NUM64K(4)
172#define LEDS_TIMING0		V_IO_ALE_WIDTH(4) | \
173                                V_IO_ALE_TO_CS(2) | \
174                                V_IO_CS_WIDTH(13) | \
175                                V_IO_RDY_SMPLE(1)
176#define LEDS_TIMING1		V_IO_ALE_TO_WRITE(2) | \
177                                V_IO_WRITE_WIDTH(8) | \
178                                V_IO_IDLE_CYCLE(6) | \
179                                V_IO_CS_TO_OE(0) | \
180                                V_IO_OE_TO_CS(0)
181#define LEDS_CONFIG		V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
182
183
184/*
185 * IDE: non-multiplexed, word(16) width, no parity, ack mode
186 * See BCM12500 Application Note: "BCM12500 Generic Bus Interface
187 * to ATA/ATAPI PIO Mode 3 (IDE) Hard Disk"
188 */
189#define IDE_CS			4
190#define IDE_PHYS		0x100B0000
191#define IDE_SIZE		NUM64K(256)
192#define IDE_TIMING0		V_IO_ALE_WIDTH(3) | \
193                                V_IO_ALE_TO_CS(1) | \
194                                V_IO_CS_WIDTH(8) | \
195                                V_IO_RDY_SMPLE(2)
196#define IDE_TIMING1		V_IO_ALE_TO_WRITE(4) | \
197                                V_IO_WRITE_WIDTH(0xA) | \
198                                V_IO_IDLE_CYCLE(1) | \
199                                V_IO_CS_TO_OE(3) | \
200                                V_IO_OE_TO_CS(2)
201#define IDE_CONFIG		V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2) | \
202                                M_IO_RDY_ACTIVE | \
203                                M_IO_ENA_RDY
204
205
206/*
207 * USB controller: non-multiplexed, no acknowledgement
208 * XXX: Check timing below; was borrowed from LEDs.
209 */
210#define USBCTL_CS		5
211#define USBCTL_PHYS		0x100C0000
212#define USBCTL_SIZE		NUM64K(4)
213#define USBCTL_TIMING0		V_IO_ALE_WIDTH(1) | \
214                                V_IO_ALE_TO_CS(2) | \
215                                V_IO_CS_WIDTH(9) | \
216                                V_IO_RDY_SMPLE(1)
217#define USBCTL_TIMING1		V_IO_ALE_TO_WRITE(1) | \
218                                V_IO_WRITE_WIDTH(7) | \
219                                V_IO_IDLE_CYCLE(15) | \
220                                V_IO_CS_TO_OE(1) | \
221                                V_IO_OE_TO_CS(0)
222#define USBCTL_CONFIG		V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
223
224/*
225 * PCMCIA: this information was derived from chapter 12, table 12-5
226 */
227#define PCMCIA_CS		6
228#define PCMCIA_PHYS		0x11000000
229#define PCMCIA_SIZE		NUM64K(64*MB)
230#define PCMCIA_TIMING0		V_IO_ALE_WIDTH(3) | \
231                                V_IO_ALE_TO_CS(1) | \
232                                V_IO_CS_WIDTH(17) | \
233                                V_IO_RDY_SMPLE(1)
234#define PCMCIA_TIMING1		V_IO_ALE_TO_WRITE(8) | \
235                                V_IO_WRITE_WIDTH(8) | \
236                                V_IO_IDLE_CYCLE(2) | \
237                                V_IO_CS_TO_OE(0) | \
238                                V_IO_OE_TO_CS(0)
239#define PCMCIA_CONFIG		V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2)
240
241/* These values work a PCMCIA HD I have ...., but I am going to try the original
242// #define PCMCIA_CS		6
243// #define PCMCIA_PHYS		0x11000000
244// #define PCMCIA_SIZE		NUM64K(64*MB)
245// #define PCMCIA_TIMING0		V_IO_ALE_WIDTH(3) | \
246//                                 V_IO_ALE_TO_CS(2) | \
247//                                 V_IO_CS_WIDTH(25) | \
248//                                 V_IO_RDY_SMPLE(1)
249// #define PCMCIA_TIMING1		V_IO_ALE_TO_WRITE(8) | \
250//                                 V_IO_WRITE_WIDTH(12) | \
251//                                 V_IO_IDLE_CYCLE(2) | \
252//                                 V_IO_CS_TO_OE(0) | \
253//                                 V_IO_OE_TO_CS(0)
254// #define PCMCIA_CONFIG		V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2)
255*/
256
257/*
258 * CPCI controller: non-multiplexed, no acknowledgement
259 * XXX: Check timing below; was borrowed from LEDs.
260 */
261#define CPCICPLD_CS		7
262#define CPCICPLD_PHYS		0x100D0000
263#define CPCICPLD_SIZE		NUM64K(4)
264#define CPCICPLD_TIMING0		V_IO_ALE_WIDTH(4) | \
265                                V_IO_ALE_TO_CS(2) | \
266                                V_IO_CS_WIDTH(13) | \
267                                V_IO_RDY_SMPLE(1)
268#define CPCICPLD_TIMING1		V_IO_ALE_TO_WRITE(2) | \
269                                V_IO_WRITE_WIDTH(8) | \
270                                V_IO_IDLE_CYCLE(6) | \
271                                V_IO_CS_TO_OE(0) | \
272                                V_IO_OE_TO_CS(0)
273#define CPCICPLD_CONFIG		V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
274
275/*  *********************************************************************
276    *  SMBus devices
277    ********************************************************************* */
278
279#define TEMPSENSOR_SMBUS_CHAN	0
280#define TEMPSENSOR_SMBUS_DEV	0x2A
281
282#define M24LC128_0_SMBUS_CHAN	0
283#define M24LC128_0_SMBUS_DEV	0x50
284
285#define M24LC128_1_SMBUS_CHAN	1
286#define M24LC128_1_SMBUS_DEV	0x50
287
288#define X1240_SMBUS_CHAN		1
289#define X1240_SMBUS_DEV			0x50
290
291#define M41T81_SMBUS_CHAN		1
292#define M41T81_SMBUS_DEV		0x68
293