1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Swarm (CSWARM) Definitions File: swarm.h 5 * 6 * This file contains I/O, chip select, and GPIO assignments 7 * for the BCM912500A checkout board. 8 * 9 * Author: Mitch Lichtenberg 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49/* 50 * I/O Address assignments for the CSWARM board 51 * 52 * Summary of address map: 53 * 54 * Address Size CSel Description 55 * --------------- ---- ------ -------------------------------- 56 * 0x1FC00000 2MB CS0 Boot ROM 57 * 0x1F800000 2MB CS1 Alternate boot ROM 58 * CS2 Unused 59 * 0x100A0000 64KB CS3 LED display 60 * 0x100B0000 64KB CS4 IDE Disk 61 * CS5 Unused 62 * 0x11000000 64MB CS6 PCMCIA 63 * CS7 Unused 64 * 65 * GPIO assignments 66 * 67 * GPIO# Direction Description 68 * ------- --------- ------------------------------------------ 69 * GPIO0 Output Debug LED 70 * GPIO1 Output Sturgeon NMI 71 * GPIO2 Input PHY Interrupt (interrupt) 72 * GPIO3 Input Nonmaskable Interrupt (interrupt) 73 * GPIO4 Input IDE Disk Interrupt (interrupt) 74 * GPIO5 Input Temperature Sensor Alert (interrupt) 75 * GPIO6 N/A PCMCIA interface 76 * GPIO7 N/A PCMCIA interface 77 * GPIO8 N/A PCMCIA interface 78 * GPIO9 N/A PCMCIA interface 79 * GPIO10 N/A PCMCIA interface 80 * GPIO11 N/A PCMCIA interface 81 * GPIO12 N/A PCMCIA interface 82 * GPIO13 N/A PCMCIA interface 83 * GPIO14 N/A PCMCIA interface 84 * GPIO15 N/A PCMCIA interface 85 */ 86 87/* ********************************************************************* 88 * Macros 89 ********************************************************************* */ 90 91#define MB (1024*1024) 92#define K64 65536 93#define NUM64K(x) (((x)+(K64-1))/K64) 94 95 96/* ********************************************************************* 97 * GPIO pins 98 ********************************************************************* */ 99 100#define GPIO_DEBUG_LED 0 101#define GPIO_STURGEON_NMI 1 102#define GPIO_PHY_INTERRUPT 2 103#define GPIO_NONMASKABLE_INT 3 104#define GPIO_IDE_INTERRUPT 4 105#define GPIO_TEMP_SENSOR_INT 5 106 107#define M_GPIO_DEBUG_LED _SB_MAKEMASK1(GPIO_DEBUG_LED) 108#define M_GPIO_STURGEON_NMI _SB_MAKEMASK1(GPIO_STURGEON_NMI) 109 110#define GPIO_OUTPUT_MASK (_SB_MAKEMASK1(GPIO_DEBUG_LED) | \ 111 _SB_MAKEMASK1(GPIO_STURGEON_NMI) ) 112 113#define GPIO_INTERRUPT_MASK ((V_GPIO_INTR_TYPEX(GPIO_PHY_INTERRUPT,K_GPIO_INTR_LEVEL)) | \ 114 (V_GPIO_INTR_TYPEX(GPIO_IDE_INTERRUPT,K_GPIO_INTR_LEVEL))) 115 116 117/* ********************************************************************* 118 * Generic Bus 119 ********************************************************************* */ 120 121/* 122 * Boot ROM: non-multiplexed, byte width, no parity, no ack 123 * XXX: These are the (very slow) default parameters. This can be sped up! 124 */ 125#define BOOTROM_CS 0 126#define BOOTROM_PHYS 0x1FC00000 /* address of boot ROM (CS0) */ 127#define BOOTROM_SIZE NUM64K(2*MB) /* size of boot ROM */ 128#define BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 129 V_IO_ALE_TO_CS(2) | \ 130 V_IO_CS_WIDTH(24) | \ 131 V_IO_RDY_SMPLE(1) 132#define BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 133 V_IO_WRITE_WIDTH(7) | \ 134 V_IO_IDLE_CYCLE(6) | \ 135 V_IO_CS_TO_OE(0) | \ 136 V_IO_OE_TO_CS(0) 137#define BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 138 139/* 140 * Alternate Boot ROM: non-multiplexed, byte width, no parity, no ack 141 * XXX: These are the (very slow) default parameters. This can be sped up! 142 */ 143#define ALT_BOOTROM_CS 1 144#define ALT_BOOTROM_PHYS 0x1F800000 /* address of alternate boot ROM (CS1) */ 145#define ALT_BOOTROM_SIZE NUM64K(2*MB) /* size of alternate boot ROM */ 146#define ALT_BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 147 V_IO_ALE_TO_CS(2) | \ 148 V_IO_CS_WIDTH(24) | \ 149 V_IO_RDY_SMPLE(1) 150#define ALT_BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 151 V_IO_WRITE_WIDTH(7) | \ 152 V_IO_IDLE_CYCLE(6) | \ 153 V_IO_CS_TO_OE(0) | \ 154 V_IO_OE_TO_CS(0) 155#define ALT_BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 156 157/* 158 * LEDs: non-multiplexed, byte width, no parity, no ack 159 */ 160#define LEDS_CS 3 161#define LEDS_PHYS 0x100A0000 162#define LEDS_SIZE NUM64K(4) 163#define LEDS_TIMING0 V_IO_ALE_WIDTH(4) | \ 164 V_IO_ALE_TO_CS(2) | \ 165 V_IO_CS_WIDTH(13) | \ 166 V_IO_RDY_SMPLE(1) 167#define LEDS_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 168 V_IO_WRITE_WIDTH(8) | \ 169 V_IO_IDLE_CYCLE(6) | \ 170 V_IO_CS_TO_OE(0) | \ 171 V_IO_OE_TO_CS(0) 172#define LEDS_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 173 174 175/* 176 * IDE: non-multiplexed, word(16) width, no parity, ack mode 177 * See BCM12500 Application Note: "BCM12500 Generic Bus Interface 178 * to ATA/ATAPI PIO Mode 3 (IDE) Hard Disk" 179 */ 180#define IDE_CS 4 181#define IDE_PHYS 0x100B0000 182#define IDE_SIZE NUM64K(256) 183#define IDE_TIMING0 V_IO_ALE_WIDTH(3) | \ 184 V_IO_ALE_TO_CS(1) | \ 185 V_IO_CS_WIDTH(8) | \ 186 V_IO_RDY_SMPLE(2) 187#define IDE_TIMING1 V_IO_ALE_TO_WRITE(4) | \ 188 V_IO_WRITE_WIDTH(0xA) | \ 189 V_IO_IDLE_CYCLE(1) | \ 190 V_IO_CS_TO_OE(3) | \ 191 V_IO_OE_TO_CS(2) 192#define IDE_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2) | \ 193 M_IO_RDY_ACTIVE | \ 194 M_IO_ENA_RDY 195 196 197 198/* 199 * PCMCIA: this information was derived from chapter 12, table 12-5 200 */ 201#define PCMCIA_CS 6 202#define PCMCIA_PHYS 0x11000000 203#define PCMCIA_SIZE NUM64K(64*MB) 204#define PCMCIA_TIMING0 V_IO_ALE_WIDTH(3) | \ 205 V_IO_ALE_TO_CS(1) | \ 206 V_IO_CS_WIDTH(17) | \ 207 V_IO_RDY_SMPLE(1) 208#define PCMCIA_TIMING1 V_IO_ALE_TO_WRITE(8) | \ 209 V_IO_WRITE_WIDTH(8) | \ 210 V_IO_IDLE_CYCLE(2) | \ 211 V_IO_CS_TO_OE(0) | \ 212 V_IO_OE_TO_CS(0) 213#define PCMCIA_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2) 214 215 216/* ********************************************************************* 217 * SMBus Devices 218 ********************************************************************* */ 219 220#define TEMPSENSOR_SMBUS_CHAN 0 221#define TEMPSENSOR_SMBUS_DEV 0x2A 222#define DRAM_SMBUS_CHAN 0 223#define DRAM_SMBUS_DEV 0x54 224#define BIGEEPROM_SMBUS_CHAN 0 225#define BIGEEPROM_SMBUS_DEV 0x50 226#define X1240_SMBUS_CHAN 1 227#define X1240_SMBUS_DEV 0x50 228 229