1/**
2 * \file
3 */
4
5/*
6 * Copyright (c) 2009, ETH Zurich.
7 * All rights reserved.
8 *
9 * This file is distributed under the terms in the attached LICENSE file.
10 * If you do not find this file, copies can be found by writing to:
11 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
12 */
13
14#ifndef AMD_SVM_H
15#define AMD_SVM_H
16
17#include <stdint.h>
18#include <dev/amd_vmcb_dev.h>
19
20/* EXITCODE */
21
22#define SVM_VMEXIT_CR0_READ         0x0
23#define SVM_VMEXIT_CR0_WRITE        0x10
24#define SVM_VMEXIT_CR0_SEL_WRITE    0x65
25#define SVM_VMEXIT_IDTR_WRITE       0x6a
26#define SVM_VMEXIT_GDTR_WRITE       0x6b
27#define SVM_VMEXIT_CPUID            0x72
28#define SVM_VMEXIT_SWINT            0x75
29#define SVM_VMEXIT_HLT              0x78
30#define SVM_VMEXIT_IOIO             0x7b
31#define SVM_VMEXIT_MSR              0x7c
32#define SVM_VMEXIT_VMMCALL          0x81
33#define SVM_VMEXIT_NPF              0x400
34
35/* IO ACCESS FLAGS (EXITINFO1) */
36#define SVM_IOIO_TYPE_MASK          (1 << 0)
37#define SVM_IOIO_STR_MASK           (1 << 2)
38#define SVM_IOIO_REP_MASK           (1 << 3)
39#define SVM_IOIO_SZ8_MASK           (1 << 4)
40#define SVM_IOIO_SZ16_MASK          (1 << 5)
41#define SVM_IOIO_SZ32_MASK          (1 << 6)
42#define SVM_IOIO_A16_MASK           (1 << 7)
43#define SVM_IOIO_A32_MASK           (1 << 8)
44#define SVM_IOIO_A64_MASK           (1 << 9)
45
46
47/**
48 * \brief Convenience macro to write real-mode segmentation registers
49 *
50 * Write the selector, base and limit to a selector reg according to real-mode
51 * segmentation rules to the VMCB.
52 */
53#define VMCB_WRITE_SEGREG_REALMODE(vmcb,reg,selector)                   \
54do {                                                                    \
55    amd_vmcb_ ##reg## _selector_wr((vmcb), (selector));                 \
56    amd_vmcb_ ##reg## _base_wr((vmcb), (selector) << 4);                \
57    amd_vmcb_ ##reg## _limit_wr((vmcb), ((selector) << 4) + 0xffff);    \
58} while (0)
59
60#endif // AMD_SVM_H
61