1/* 2 * cpu.h 3 * 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name Texas Instruments nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#ifndef _OMAP44XX_CPU_H 34#define _OMAP44XX_CPU_H 35 36 37/* 38 * 4430 specific Section 39 */ 40 41/* Stuff on L3 Interconnect */ 42 43/* L3 Firewall */ 44#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) 45#define A_READPERM0 (SMX_APE_BASE + 0x05050) 46#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) 47 48 49#define OMAP44XX_SDRC_BASE 0x6D000000 50#define OMAP44XX_SMS_BASE 0x6C000000 51#define SMX_APE_BASE 0x68000000 52#define OMAP44XX_GPMC_BASE 0x50000000 53#define OMAP44XX_DMM_BASE 0x4E000000 54#define OMAP44XX_L4_IO_BASE 0x4A000000 55#define OMAP44XX_WAKEUP_L4_IO_BASE 0x4A300000 56#define OMAP44XX_L4_PER 0x48000000 57 58/* 59 * L4 Peripherals - L4 Wakeup and L4 Core now 60 */ 61 62/* CONTROL */ 63#define OMAP44XX_CTRL_GEN_BASE (OMAP44XX_L4_IO_BASE+0x2000) 64#define OMAP44XX_CTRL_PADCONF_CORE_BASE 0x4a100000 65 66/* PL310 */ 67#define OMAP44XX_PL310_BASE 0x48242000 68 69/* TAP information dont know for 3430*/ 70#define OMAP44XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ 71 72/* UART */ 73#define OMAP44XX_UART1 (OMAP44XX_L4_PER+0x6a000) 74#define OMAP44XX_UART2 (OMAP44XX_L4_PER+0x6c000) 75#define OMAP44XX_UART3 (OMAP44XX_L4_PER+0x20000) 76#define OMAP44XX_UART4 (OMAP44XX_L4_PER+0x6e000) 77 78/* General Purpose Timers */ 79#define OMAP44XX_GPT1 0x48318000 80#define OMAP44XX_GPT2 0x48032000 81#define OMAP44XX_GPT3 0x48034000 82#define OMAP44XX_GPT4 0x48036000 83#define OMAP44XX_GPT5 0x40138000 84#define OMAP44XX_GPT6 0x4013A000 85#define OMAP44XX_GPT7 0x4013C000 86#define OMAP44XX_GPT8 0x4013E000 87#define OMAP44XX_GPT9 0x48040000 88#define OMAP44XX_GPT10 0x48086000 89#define OMAP44XX_GPT11 0x48088000 90#define OMAP44XX_GPT12 0x48304000 91 92/* WatchDog Timers (1 secure, 3 GP) */ 93#define WD1_BASE 0x4A322000 94#define WD2_BASE 0x4A314000 95#define WD3_BASE 0x40130000 96 97/* 32KTIMER */ 98#define SYNC_32KTIMER_BASE (0x48320000) 99#define S32K_CR (SYNC_32KTIMER_BASE+0x10) 100 101/* Register offsets of common modules */ 102/* Control */ 103#define CONTROL_ID_CODE (OMAP44XX_CTRL_GEN_BASE + 0x204) 104#define CONTROL_STATUS (OMAP44XX_CTRL_GEN_BASE + 0x2C4) 105 106/* PL310 */ 107#define OMAP44XX_PL310_AUX_CTRL (OMAP44XX_PL310_BASE + 0x104) 108 109/* Tap Information */ 110#define TAP_IDCODE_REG (OMAP44XX_TAP_BASE+0x204) 111#define PRODUCTION_ID (OMAP44XX_TAP_BASE+0x208) 112 113/* device type */ 114#define DEVICE_MASK (0x03 << 8) 115#define TST_DEVICE 0x0 116#define EMU_DEVICE 0x1 117#define HS_DEVICE 0x2 118#define GP_DEVICE 0x3 119 120/* GPMC CS3/cs4/cs6 not avaliable */ 121#define GPMC_BASE (OMAP44XX_GPMC_BASE) 122#define GPMC_SYSCONFIG (OMAP44XX_GPMC_BASE+0x10) 123#define GPMC_IRQSTATUS (OMAP44XX_GPMC_BASE+0x18) 124#define GPMC_IRQENABLE (OMAP44XX_GPMC_BASE+0x1C) 125#define GPMC_TIMEOUT_CONTROL (OMAP44XX_GPMC_BASE+0x40) 126#define GPMC_CONFIG (OMAP44XX_GPMC_BASE+0x50) 127#define GPMC_STATUS (OMAP44XX_GPMC_BASE+0x54) 128 129#define GPMC_CONFIG_CS0 (OMAP44XX_GPMC_BASE+0x60) 130#define GPMC_CONFIG_WIDTH (0x30) 131 132#define GPMC_CONFIG1 (0x00) 133#define GPMC_CONFIG2 (0x04) 134#define GPMC_CONFIG3 (0x08) 135#define GPMC_CONFIG4 (0x0C) 136#define GPMC_CONFIG5 (0x10) 137#define GPMC_CONFIG6 (0x14) 138#define GPMC_CONFIG7 (0x18) 139#define GPMC_NAND_CMD (0x1C) 140#define GPMC_NAND_ADR (0x20) 141#define GPMC_NAND_DAT (0x24) 142 143#define GPMC_ECC_CONFIG (0x1F4) 144#define GPMC_ECC_CONTROL (0x1F8) 145#define GPMC_ECC_SIZE_CONFIG (0x1FC) 146#define GPMC_ECC1_RESULT (0x200) 147#define GPMC_ECC2_RESULT (0x204) 148#define GPMC_ECC3_RESULT (0x208) 149#define GPMC_ECC4_RESULT (0x20C) 150#define GPMC_ECC5_RESULT (0x210) 151#define GPMC_ECC6_RESULT (0x214) 152#define GPMC_ECC7_RESULT (0x218) 153#define GPMC_ECC8_RESULT (0x21C) 154#define GPMC_ECC9_RESULT (0x220) 155 156#define GPMC_PREFETCH_CONFIG1 (0x1e0) 157#define GPMC_PREFETCH_CONFIG2 (0x1e4) 158#define GPMC_PREFETCH_CONTROL (0x1ec) 159#define GPMC_PREFETCH_STATUS (0x1f0) 160 161/* GPMC Mapping */ 162# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */ 163# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */ 164# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */ 165# define DEBUG_BASE 0x08000000 /* debug board */ 166# define NAND_BASE 0x30000000 /* NAND addr (actual size small port)*/ 167# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ 168# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */ 169 170/* DMM */ 171#define DMM_SYSCONFIG (OMAP44XX_DMM_BASE+0x10) 172#define DMM_LISA_MAP (OMAP44XX_DMM_BASE+0x100) 173 174/* SMS */ 175#define SMS_SYSCONFIG (OMAP44XX_SMS_BASE+0x10) 176#define SMS_RG_ATT0 (OMAP44XX_SMS_BASE+0x48) 177#define SMS_CLASS_ARB0 (OMAP44XX_SMS_BASE+0xD0) 178#define BURSTCOMPLETE_GROUP7 (1<<31) 179 180#define SDRC_CS_CFG (OMAP44XX_SDRC_BASE+0x40) 181#define OMAP44XX_SDRC_CS0 0x80000000 182#define SDRC_POWER (OMAP44XX_SDRC_BASE+0x70) 183#define SDRC_MCFG_0 (OMAP44XX_SDRC_BASE+0x80) 184#define SDRC_MR_0 (OMAP44XX_SDRC_BASE+0x84) 185 186/* timer regs offsets (32 bit regs) */ 187#define TIDR 0x0 /* r */ 188#define TIOCP_CFG 0x10 /* rw */ 189#define TISTAT 0x14 /* r */ 190#define TISR 0x18 /* rw */ 191#define TIER 0x1C /* rw */ 192#define TWER 0x20 /* rw */ 193#define TCLR 0x24 /* rw */ 194#define TCRR 0x28 /* rw */ 195#define TLDR 0x2C /* rw */ 196#define TTGR 0x30 /* rw */ 197#define TWPS 0x34 /* r */ 198#define TMAR 0x38 /* rw */ 199#define TCAR1 0x3c /* r */ 200#define TSICR 0x40 /* rw */ 201#define TCAR2 0x44 /* r */ 202#define GPT_EN 0x03 /* enable sys_clk NO-prescale /1 */ 203 204/* Watchdog */ 205#define WWPS 0x34 /* r */ 206#define WSPR 0x48 /* rw */ 207#define WD_UNLOCK1 0xAAAA 208#define WD_UNLOCK2 0x5555 209 210/* FIXME */ 211#define PRM_RSTCTRL 0x48307250 212 /* PRCM */ 213#define CM_SYS_CLKSEL 0x4a306110 214 215/* PRM.CKGEN module registers */ 216#define CM_ABE_PLL_REF_CLKSEL 0x4a30610c 217 218#define OMAP44XX_WKUP_CTRL_BASE 0x4A31E000 219 220/* PRM.WKUP_CM module registers */ 221#define CM_WKUP_CLKSTCTRL 0x4a307800 222#define CM_WKUP_L4WKUP_CLKCTRL 0x4a307820 223#define CM_WKUP_WDT1_CLKCTRL 0x4a307828 224#define CM_WKUP_WDT2_CLKCTRL 0x4a307830 225#define CM_WKUP_GPIO1_CLKCTRL 0x4a307838 226#define CM_WKUP_TIMER1_CLKCTRL 0x4a307840 227#define CM_WKUP_TIMER12_CLKCTRL 0x4a307848 228#define CM_WKUP_SYNCTIMER_CLKCTRL 0x4a307850 229#define CM_WKUP_USIM_CLKCTRL 0x4a307858 230#define CM_WKUP_SARRAM_CLKCTRL 0x4a307860 231#define CM_WKUP_KEYBOARD_CLKCTRL 0x4a307878 232#define CM_WKUP_RTC_CLKCTRL 0x4a307880 233#define CM_WKUP_BANDGAP_CLKCTRL 0x4a307888 234 235/* CM1.CKGEN module registers */ 236#define CM_CLKSEL_CORE 0x4a004100 237#define CM_CLKSEL_ABE 0x4a004108 238#define CM_DLL_CTRL 0x4a004110 239#define CM_CLKMODE_DPLL_CORE 0x4a004120 240#define CM_IDLEST_DPLL_CORE 0x4a004124 241#define CM_AUTOIDLE_DPLL_CORE 0x4a004128 242#define CM_CLKSEL_DPLL_CORE 0x4a00412c 243#define CM_DIV_M2_DPLL_CORE 0x4a004130 244#define CM_DIV_M3_DPLL_CORE 0x4a004134 245#define CM_DIV_M4_DPLL_CORE 0x4a004138 246#define CM_DIV_M5_DPLL_CORE 0x4a00413c 247#define CM_DIV_M6_DPLL_CORE 0x4a004140 248#define CM_DIV_M7_DPLL_CORE 0x4a004144 249#define CM_SSC_DELTAMSTEP_DPLL_CORE 0x4a004148 250#define CM_SSC_MODFREQDIV_DPLL_CORE 0x4a00414c 251#define CM_EMU_OVERRIDE_DPLL_CORE 0x4a004150 252#define CM_CLKMODE_DPLL_MPU 0x4a004160 253#define CM_IDLEST_DPLL_MPU 0x4a004164 254#define CM_AUTOIDLE_DPLL_MPU 0x4a004168 255#define CM_CLKSEL_DPLL_MPU 0x4a00416c 256#define CM_DIV_M2_DPLL_MPU 0x4a004170 257#define CM_SSC_DELTAMSTEP_DPLL_MPU 0x4a004188 258#define CM_SSC_MODFREQDIV_DPLL_MPU 0x4a00418c 259#define CM_BYPCLK_DPLL_MPU 0x4a00419c 260#define CM_CLKMODE_DPLL_IVA 0x4a0041a0 261#define CM_IDLEST_DPLL_IVA 0x4a0041a4 262#define CM_AUTOIDLE_DPLL_IVA 0x4a0041a8 263#define CM_CLKSEL_DPLL_IVA 0x4a0041ac 264#define CM_DIV_M4_DPLL_IVA 0x4a0041b8 265#define CM_DIV_M5_DPLL_IVA 0x4a0041bc 266#define CM_SSC_DELTAMSTEP_DPLL_IVA 0x4a0041c8 267#define CM_SSC_MODFREQDIV_DPLL_IVA 0x4a0041cc 268#define CM_BYPCLK_DPLL_IVA 0x4a0041dc 269#define CM_CLKMODE_DPLL_ABE 0x4a0041e0 270#define CM_IDLEST_DPLL_ABE 0x4a0041e4 271#define CM_AUTOIDLE_DPLL_ABE 0x4a0041e8 272#define CM_CLKSEL_DPLL_ABE 0x4a0041ec 273#define CM_DIV_M2_DPLL_ABE 0x4a0041f0 274#define CM_DIV_M3_DPLL_ABE 0x4a0041f4 275#define CM_SSC_DELTAMSTEP_DPLL_ABE 0x4a004208 276#define CM_SSC_MODFREQDIV_DPLL_ABE 0x4a00420c 277#define CM_CLKMODE_DPLL_DDRPHY 0x4a004220 278#define CM_IDLEST_DPLL_DDRPHY 0x4a004224 279#define CM_AUTOIDLE_DPLL_DDRPHY 0x4a004228 280#define CM_CLKSEL_DPLL_DDRPHY 0x4a00422c 281#define CM_DIV_M2_DPLL_DDRPHY 0x4a004230 282#define CM_DIV_M4_DPLL_DDRPHY 0x4a004238 283#define CM_DIV_M5_DPLL_DDRPHY 0x4a00423c 284#define CM_DIV_M6_DPLL_DDRPHY 0x4a004240 285#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY 0x4a004248 286 287/* CM1.ABE register offsets */ 288#define CM1_ABE_CLKSTCTRL 0x4a004500 289#define CM1_ABE_L4ABE_CLKCTRL 0x4a004520 290#define CM1_ABE_AESS_CLKCTRL 0x4a004528 291#define CM1_ABE_PDM_CLKCTRL 0x4a004530 292#define CM1_ABE_DMIC_CLKCTRL 0x4a004538 293#define CM1_ABE_MCASP_CLKCTRL 0x4a004540 294#define CM1_ABE_MCBSP1_CLKCTRL 0x4a004548 295#define CM1_ABE_MCBSP2_CLKCTRL 0x4a004550 296#define CM1_ABE_MCBSP3_CLKCTRL 0x4a004558 297#define CM1_ABE_SLIMBUS_CLKCTRL 0x4a004560 298#define CM1_ABE_TIMER5_CLKCTRL 0x4a004568 299#define CM1_ABE_TIMER6_CLKCTRL 0x4a004570 300#define CM1_ABE_TIMER7_CLKCTRL 0x4a004578 301#define CM1_ABE_TIMER8_CLKCTRL 0x4a004580 302#define CM1_ABE_WDT3_CLKCTRL 0x4a004588 303 304/* CM1.DSP register offsets */ 305#define DSP_CLKSTCTRL 0x4a004400 306#define DSP_DSP_CLKCTRL 0x4a004420 307 308/* CM2.CKGEN module registers */ 309#define CM_CLKSEL_DUCATI_ISS_ROOT 0x4a008100 310#define CM_CLKSEL_USB_60MHz 0x4a008104 311#define CM_SCALE_FCLK 0x4a008108 312#define CM_CORE_DVFS_PERF1 0x4a008110 313#define CM_CORE_DVFS_PERF2 0x4a008114 314#define CM_CORE_DVFS_PERF3 0x4a008118 315#define CM_CORE_DVFS_PERF4 0x4a00811c 316#define CM_CORE_DVFS_CURRENT 0x4a008124 317#define CM_IVA_DVFS_PERF_TESLA 0x4a008128 318#define CM_IVA_DVFS_PERF_IVAHD 0x4a00812c 319#define CM_IVA_DVFS_PERF_ABE 0x4a008130 320#define CM_IVA_DVFS_CURRENT 0x4a008138 321#define CM_CLKMODE_DPLL_PER 0x4a008140 322#define CM_IDLEST_DPLL_PER 0x4a008144 323#define CM_AUTOIDLE_DPLL_PER 0x4a008148 324#define CM_CLKSEL_DPLL_PER 0x4a00814c 325#define CM_DIV_M2_DPLL_PER 0x4a008150 326#define CM_DIV_M3_DPLL_PER 0x4a008154 327#define CM_DIV_M4_DPLL_PER 0x4a008158 328#define CM_DIV_M5_DPLL_PER 0x4a00815c 329#define CM_DIV_M6_DPLL_PER 0x4a008160 330#define CM_DIV_M7_DPLL_PER 0x4a008164 331#define CM_SSC_DELTAMSTEP_DPLL_PER 0x4a008168 332#define CM_SSC_MODFREQDIV_DPLL_PER 0x4a00816c 333#define CM_EMU_OVERRIDE_DPLL_PER 0x4a008170 334#define CM_CLKMODE_DPLL_USB 0x4a008180 335#define CM_IDLEST_DPLL_USB 0x4a008184 336#define CM_AUTOIDLE_DPLL_USB 0x4a008188 337#define CM_CLKSEL_DPLL_USB 0x4a00818c 338#define CM_DIV_M2_DPLL_USB 0x4a008190 339#define CM_SSC_DELTAMSTEP_DPLL_USB 0x4a0081a8 340#define CM_SSC_MODFREQDIV_DPLL_USB 0x4a0081ac 341#define CM_CLKDCOLDO_DPLL_USB 0x4a0081b4 342#define CM_CLKMODE_DPLL_UNIPRO 0x4a0081c0 343#define CM_IDLEST_DPLL_UNIPRO 0x4a0081c4 344#define CM_AUTOIDLE_DPLL_UNIPRO 0x4a0081c8 345#define CM_CLKSEL_DPLL_UNIPRO 0x4a0081cc 346#define CM_DIV_M2_DPLL_UNIPRO 0x4a0081d0 347#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO 0x4a0081e8 348#define CM_SSC_MODFREQDIV_DPLL_UNIPRO 0x4a0081ec 349 350/* CM2.CORE module registers */ 351#define CM_L3_1_CLKSTCTRL 0x4a008700 352#define CM_L3_1_DYNAMICDEP 0x4a008708 353#define CM_L3_1_L3_1_CLKCTRL 0x4a008720 354#define CM_L3_2_CLKSTCTRL 0x4a008800 355#define CM_L3_2_DYNAMICDEP 0x4a008808 356#define CM_L3_2_L3_2_CLKCTRL 0x4a008820 357#define CM_L3_2_GPMC_CLKCTRL 0x4a008828 358#define CM_L3_2_OCMC_RAM_CLKCTRL 0x4a008830 359#define CM_DUCATI_CLKSTCTRL 0x4a008900 360#define CM_DUCATI_STATICDEP 0x4a008904 361#define CM_DUCATI_DYNAMICDEP 0x4a008908 362#define CM_DUCATI_DUCATI_CLKCTRL 0x4a008920 363#define CM_SDMA_CLKSTCTRL 0x4a008a00 364#define CM_SDMA_STATICDEP 0x4a008a04 365#define CM_SDMA_DYNAMICDEP 0x4a008a08 366#define CM_SDMA_SDMA_CLKCTRL 0x4a008a20 367#define CM_MEMIF_CLKSTCTRL 0x4a008b00 368#define CM_MEMIF_DMM_CLKCTRL 0x4a008b20 369#define CM_MEMIF_EMIF_FW_CLKCTRL 0x4a008b28 370#define CM_MEMIF_EMIF_1_CLKCTRL 0x4a008b30 371#define CM_MEMIF_EMIF_2_CLKCTRL 0x4a008b38 372#define CM_MEMIF_DLL_CLKCTRL 0x4a008b40 373#define CM_MEMIF_EMIF_H1_CLKCTRL 0x4a008b50 374#define CM_MEMIF_EMIF_H2_CLKCTRL 0x4a008b58 375#define CM_MEMIF_DLL_H_CLKCTRL 0x4a008b60 376#define CM_D2D_CLKSTCTRL 0x4a008c00 377#define CM_D2D_STATICDEP 0x4a008c04 378#define CM_D2D_DYNAMICDEP 0x4a008c08 379#define CM_D2D_SAD2D_CLKCTRL 0x4a008c20 380#define CM_D2D_MODEM_ICR_CLKCTRL 0x4a008c28 381#define CM_D2D_SAD2D_FW_CLKCTRL 0x4a008c30 382#define CM_L4CFG_CLKSTCTRL 0x4a008d00 383#define CM_L4CFG_DYNAMICDEP 0x4a008d08 384#define CM_L4CFG_L4_CFG_CLKCTRL 0x4a008d20 385#define CM_L4CFG_HW_SEM_CLKCTRL 0x4a008d28 386#define CM_L4CFG_MAILBOX_CLKCTRL 0x4a008d30 387#define CM_L4CFG_SAR_ROM_CLKCTRL 0x4a008d38 388#define CM_L3INSTR_CLKSTCTRL 0x4a008e00 389#define CM_L3INSTR_L3_3_CLKCTRL 0x4a008e20 390#define CM_L3INSTR_L3_INSTR_CLKCTRL 0x4a008e28 391#define CM_L3INSTR_OCP_WP1_CLKCTRL 0x4a008e40 392 393/* CM2.L4PER register offsets */ 394#define CM_L4PER_CLKSTCTRL 0x4a009400 395#define CM_L4PER_DYNAMICDEP 0x4a009408 396#define CM_L4PER_ADC_CLKCTRL 0x4a009420 397#define CM_L4PER_DMTIMER10_CLKCTRL 0x4a009428 398#define CM_L4PER_DMTIMER11_CLKCTRL 0x4a009430 399#define CM_L4PER_DMTIMER2_CLKCTRL 0x4a009438 400#define CM_L4PER_DMTIMER3_CLKCTRL 0x4a009440 401#define CM_L4PER_DMTIMER4_CLKCTRL 0x4a009448 402#define CM_L4PER_DMTIMER9_CLKCTRL 0x4a009450 403#define CM_L4PER_ELM_CLKCTRL 0x4a009458 404#define CM_L4PER_GPIO2_CLKCTRL 0x4a009460 405#define CM_L4PER_GPIO3_CLKCTRL 0x4a009468 406#define CM_L4PER_GPIO4_CLKCTRL 0x4a009470 407#define CM_L4PER_GPIO5_CLKCTRL 0x4a009478 408#define CM_L4PER_GPIO6_CLKCTRL 0x4a009480 409#define CM_L4PER_HDQ1W_CLKCTRL 0x4a009488 410#define CM_L4PER_HECC1_CLKCTRL 0x4a009490 411#define CM_L4PER_HECC2_CLKCTRL 0x4a009498 412#define CM_L4PER_I2C1_CLKCTRL 0x4a0094a0 413#define CM_L4PER_I2C2_CLKCTRL 0x4a0094a8 414#define CM_L4PER_I2C3_CLKCTRL 0x4a0094b0 415#define CM_L4PER_I2C4_CLKCTRL 0x4a0094b8 416#define CM_L4PER_L4PER_CLKCTRL 0x4a0094c0 417#define CM_L4PER_MCASP2_CLKCTRL 0x4a0094d0 418#define CM_L4PER_MCASP3_CLKCTRL 0x4a0094d8 419#define CM_L4PER_MCBSP4_CLKCTRL 0x4a0094e0 420#define CM_L4PER_MGATE_CLKCTRL 0x4a0094e8 421#define CM_L4PER_MCSPI1_CLKCTRL 0x4a0094f0 422#define CM_L4PER_MCSPI2_CLKCTRL 0x4a0094f8 423#define CM_L4PER_MCSPI3_CLKCTRL 0x4a009500 424#define CM_L4PER_MCSPI4_CLKCTRL 0x4a009508 425#define CM_L4PER_MMCSD3_CLKCTRL 0x4a009520 426#define CM_L4PER_MMCSD4_CLKCTRL 0x4a009528 427#define CM_L4PER_MSPROHG_CLKCTRL 0x4a009530 428#define CM_L4PER_SLIMBUS2_CLKCTRL 0x4a009538 429#define CM_L4PER_UART1_CLKCTRL 0x4a009540 430#define CM_L4PER_UART2_CLKCTRL 0x4a009548 431#define CM_L4PER_UART3_CLKCTRL 0x4a009550 432#define CM_L4PER_UART4_CLKCTRL 0x4a009558 433#define CM_L4PER_MMCSD5_CLKCTRL 0x4a009560 434#define CM_L4PER_I2C5_CLKCTRL 0x4a009568 435#define CM_L4SEC_CLKSTCTRL 0x4a009580 436#define CM_L4SEC_STATICDEP 0x4a009584 437#define CM_L4SEC_DYNAMICDEP 0x4a009588 438#define CM_L4SEC_AES1_CLKCTRL 0x4a0095a0 439#define CM_L4SEC_AES2_CLKCTRL 0x4a0095a8 440#define CM_L4SEC_DES3DES_CLKCTRL 0x4a0095b0 441#define CM_L4SEC_PKAEIP29_CLKCTRL 0x4a0095b8 442#define CM_L4SEC_RNG_CLKCTRL 0x4a0095c0 443#define CM_L4SEC_SHA2MD51_CLKCTRL 0x4a0095c8 444#define CM_L4SEC_CRYPTODMA_CLKCTRL 0x4a0095d8 445 446/* CM2.IVAHD */ 447#define IVAHD_CLKSTCTRL 0x4a008f00 448#define IVAHD_IVAHD_CLKCTRL 0x4a008f20 449#define IVAHD_SL2_CLKCTRL 0x4a008f28 450 451/* CM2.L3INIT */ 452#define CM_L3INIT_HSMMC1_CLKCTRL 0x4a009328 453#define CM_L3INIT_HSMMC2_CLKCTRL 0x4a009330 454#define CM_L3INIT_HSI_CLKCTRL 0x4a009338 455#define CM_L3INIT_UNIPRO1_CLKCTRL 0x4a009340 456#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4a009358 457#define CM_L3INIT_HSUSBOTG_CLKCTRL 0x4a009360 458#define CM_L3INIT_HSUSBTLL_CLKCTRL 0x4a009368 459#define CM_L3INIT_P1500_CLKCTRL 0x4a009378 460#define CM_L3INIT_FSUSB_CLKCTRL 0x4a0093d0 461#define CM_L3INIT_USBPHY_CLKCTRL 0x4a0093e0 462 463/* CM2.CAM */ 464#define CM_CAM_CLKSTCTRL 0x4a009000 465#define CM_CAM_ISS_CLKCTRL 0x4a009020 466#define CM_CAM_FDIF_CLKCTRL 0x4a009028 467 468/* CM2.DSS */ 469#define CM_DSS_CLKSTCTRL 0x4a009100 470#define CM_DSS_DSS_CLKCTRL 0x4a009120 471#define CM_DSS_DEISS_CLKCTRL 0x4a009128 472 473/* CM2.SGX */ 474#define CM_SGX_CLKSTCTRL 0x4a009200 475#define CM_SGX_SGX_CLKCTRL 0x4a009220 476 477/* SMX-APE */ 478#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) 479#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) 480#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) 481#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) 482#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) 483 484#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) 485#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) 486#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) 487#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) 488 489#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) 490#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) 491#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) 492 493#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) 494#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) 495#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) 496#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) 497 498#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) 499#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) 500#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) 501 502#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) 503#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) 504#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) 505 506#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) 507#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) 508#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) 509 510#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) 511#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) 512#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) 513 514/* I2C base */ 515#define I2C_BASE1 (OMAP44XX_L4_PER + 0x70000) 516#define I2C_BASE2 (OMAP44XX_L4_PER + 0x72000) 517#define I2C_BASE3 (OMAP44XX_L4_PER + 0x60000) 518 519 520/* EMIF and DMM registers */ 521#define EMIF1_BASE 0x4c000000 522#define EMIF2_BASE 0x4d000000 523#define DMM_BASE 0x4e000000 524#define MA_BASE 0x482AF000 525 526/* EMIF */ 527#define EMIF_MOD_ID_REV 0x0000 528#define EMIF_STATUS 0x0004 529#define EMIF_SDRAM_CONFIG 0x0008 530#define EMIF_LPDDR2_NVM_CONFIG 0x000C 531#define EMIF_SDRAM_REF_CTRL 0x0010 532#define EMIF_SDRAM_REF_CTRL_SHDW 0x0014 533#define EMIF_SDRAM_TIM_1 0x0018 534#define EMIF_SDRAM_TIM_1_SHDW 0x001C 535#define EMIF_SDRAM_TIM_2 0x0020 536#define EMIF_SDRAM_TIM_2_SHDW 0x0024 537#define EMIF_SDRAM_TIM_3 0x0028 538#define EMIF_SDRAM_TIM_3_SHDW 0x002C 539#define EMIF_LPDDR2_NVM_TIM 0x0030 540#define EMIF_LPDDR2_NVM_TIM_SHDW 0x0034 541#define EMIF_PWR_MGMT_CTRL 0x0038 542#define EMIF_PWR_MGMT_CTRL_SHDW 0x003C 543#define EMIF_LPDDR2_MODE_REG_DATA 0x0040 544#define EMIF_LPDDR2_MODE_REG_CFG 0x0050 545#define EMIF_L3_CONFIG 0x0054 546#define EMIF_L3_CFG_VAL_1 0x0058 547#define EMIF_L3_CFG_VAL_2 0x005C 548#define IODFT_TLGC 0x0060 549#define EMIF_PERF_CNT_1 0x0080 550#define EMIF_PERF_CNT_2 0x0084 551#define EMIF_PERF_CNT_CFG 0x0088 552#define EMIF_PERF_CNT_SEL 0x008C 553#define EMIF_PERF_CNT_TIM 0x0090 554#define EMIF_READ_IDLE_CTRL 0x0098 555#define EMIF_READ_IDLE_CTRL_SHDW 0x009c 556#define EMIF_ZQ_CONFIG 0x00C8 557#define EMIF_DDR_PHY_CTRL_1 0x00E4 558#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00E8 559#define EMIF_DDR_PHY_CTRL_2 0x00EC 560 561#define DMM_LISA_MAP_0 0x0040 562#define DMM_LISA_MAP_1 0x0044 563#define DMM_LISA_MAP_2 0x0048 564#define DMM_LISA_MAP_3 0x004C 565 566#ifndef __ASSEMBLY__ 567 568/* structure for ddr timings */ 569struct ddr_regs{ 570 u32 tim1; 571 u32 tim2; 572 u32 tim3; 573 u32 phy_ctrl_1; 574 u32 ref_ctrl; 575 u32 config_init; 576 u32 config_final; 577 u32 zq_config; 578 u8 mr1; 579 u8 mr2; 580}; 581 582/* Used to index into DPLL parameter tables */ 583struct dpll_param { 584 unsigned int m; 585 unsigned int n; 586 unsigned int m2; 587 unsigned int m3; 588 unsigned int m4; 589 unsigned int m5; 590 unsigned int m6; 591 unsigned int m7; 592}; 593 594void omap4_ddr_init(const struct ddr_regs *ddr1, 595 const struct ddr_regs *ddr2); 596#endif 597 598#endif 599