1//===-- clear_cache.c - Implement __clear_cache ---------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "int_lib.h"
10#include <assert.h>
11#include <stddef.h>
12
13#if __APPLE__
14#include <libkern/OSCacheControl.h>
15#endif
16
17#if defined(_WIN32)
18// Forward declare Win32 APIs since the GCC mode driver does not handle the
19// newer SDKs as well as needed.
20uint32_t FlushInstructionCache(uintptr_t hProcess, void *lpBaseAddress,
21                               uintptr_t dwSize);
22uintptr_t GetCurrentProcess(void);
23#endif
24
25#if defined(__FreeBSD__) && defined(__arm__)
26#include <machine/sysarch.h>
27#include <sys/types.h>
28#endif
29
30#if defined(__NetBSD__) && defined(__arm__)
31#include <machine/sysarch.h>
32#endif
33
34#if defined(__OpenBSD__) && defined(__mips__)
35#include <machine/sysarch.h>
36#include <sys/types.h>
37#endif
38
39#if defined(__linux__) && defined(__mips__)
40#include <sys/cachectl.h>
41#include <sys/syscall.h>
42#include <unistd.h>
43#if defined(__ANDROID__) && defined(__LP64__)
44// clear_mips_cache - Invalidates instruction cache for Mips.
45static void clear_mips_cache(const void *Addr, size_t Size) {
46  __asm__ volatile(
47      ".set push\n"
48      ".set noreorder\n"
49      ".set noat\n"
50      "beq %[Size], $zero, 20f\n" // If size == 0, branch around.
51      "nop\n"
52      "daddu %[Size], %[Addr], %[Size]\n" // Calculate end address + 1
53      "rdhwr $v0, $1\n"                   // Get step size for SYNCI.
54                                          // $1 is $HW_SYNCI_Step
55      "beq $v0, $zero, 20f\n"             // If no caches require
56                                          // synchronization, branch
57                                          // around.
58      "nop\n"
59      "10:\n"
60      "synci 0(%[Addr])\n"            // Synchronize all caches around
61                                      // address.
62      "daddu %[Addr], %[Addr], $v0\n" // Add step size.
63      "sltu $at, %[Addr], %[Size]\n"  // Compare current with end
64                                      // address.
65      "bne $at, $zero, 10b\n"         // Branch if more to do.
66      "nop\n"
67      "sync\n" // Clear memory hazards.
68      "20:\n"
69      "bal 30f\n"
70      "nop\n"
71      "30:\n"
72      "daddiu $ra, $ra, 12\n" // $ra has a value of $pc here.
73                              // Add offset of 12 to point to the
74                              // instruction after the last nop.
75                              //
76      "jr.hb $ra\n"           // Return, clearing instruction
77                              // hazards.
78      "nop\n"
79      ".set pop\n"
80      : [ Addr ] "+r"(Addr), [ Size ] "+r"(Size)::"at", "ra", "v0", "memory");
81}
82#endif
83#endif
84
85// The compiler generates calls to __clear_cache() when creating
86// trampoline functions on the stack for use with nested functions.
87// It is expected to invalidate the instruction cache for the
88// specified range.
89
90void __clear_cache(void *start, void *end) {
91#if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64)
92// Intel processors have a unified instruction and data cache
93// so there is nothing to do
94#elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__))
95  FlushInstructionCache(GetCurrentProcess(), start, end - start);
96#elif defined(__arm__) && !defined(__APPLE__)
97#if defined(__FreeBSD__) || defined(__NetBSD__)
98  struct arm_sync_icache_args arg;
99
100  arg.addr = (uintptr_t)start;
101  arg.len = (uintptr_t)end - (uintptr_t)start;
102
103  sysarch(ARM_SYNC_ICACHE, &arg);
104#elif defined(__linux__)
105// We used to include asm/unistd.h for the __ARM_NR_cacheflush define, but
106// it also brought many other unused defines, as well as a dependency on
107// kernel headers to be installed.
108//
109// This value is stable at least since Linux 3.13 and should remain so for
110// compatibility reasons, warranting it's re-definition here.
111#define __ARM_NR_cacheflush 0x0f0002
112  register int start_reg __asm("r0") = (int)(intptr_t)start;
113  const register int end_reg __asm("r1") = (int)(intptr_t)end;
114  const register int flags __asm("r2") = 0;
115  const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush;
116  __asm __volatile("svc 0x0"
117                   : "=r"(start_reg)
118                   : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags));
119  assert(start_reg == 0 && "Cache flush syscall failed.");
120#else
121  compilerrt_abort();
122#endif
123#elif defined(__linux__) && defined(__mips__)
124  const uintptr_t start_int = (uintptr_t)start;
125  const uintptr_t end_int = (uintptr_t)end;
126#if defined(__ANDROID__) && defined(__LP64__)
127  // Call synci implementation for short address range.
128  const uintptr_t address_range_limit = 256;
129  if ((end_int - start_int) <= address_range_limit) {
130    clear_mips_cache(start, (end_int - start_int));
131  } else {
132    syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
133  }
134#else
135  syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
136#endif
137#elif defined(__mips__) && defined(__OpenBSD__)
138  cacheflush(start, (uintptr_t)end - (uintptr_t)start, BCACHE);
139#elif defined(__aarch64__) && !defined(__APPLE__)
140  uint64_t xstart = (uint64_t)(uintptr_t)start;
141  uint64_t xend = (uint64_t)(uintptr_t)end;
142  uint64_t addr;
143
144  // Get Cache Type Info
145  uint64_t ctr_el0;
146  __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
147
148  // dc & ic instructions must use 64bit registers so we don't use
149  // uintptr_t in case this runs in an IPL32 environment.
150  const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
151  for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
152       addr += dcache_line_size)
153    __asm __volatile("dc cvau, %0" ::"r"(addr));
154  __asm __volatile("dsb ish");
155
156  const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
157  for (addr = xstart & ~(icache_line_size - 1); addr < xend;
158       addr += icache_line_size)
159    __asm __volatile("ic ivau, %0" ::"r"(addr));
160  __asm __volatile("isb sy");
161#elif defined(__powerpc64__)
162  const size_t line_size = 32;
163  const size_t len = (uintptr_t)end - (uintptr_t)start;
164
165  const uintptr_t mask = ~(line_size - 1);
166  const uintptr_t start_line = ((uintptr_t)start) & mask;
167  const uintptr_t end_line = ((uintptr_t)start + len + line_size - 1) & mask;
168
169  for (uintptr_t line = start_line; line < end_line; line += line_size)
170    __asm__ volatile("dcbf 0, %0" : : "r"(line));
171  __asm__ volatile("sync");
172
173  for (uintptr_t line = start_line; line < end_line; line += line_size)
174    __asm__ volatile("icbi 0, %0" : : "r"(line));
175  __asm__ volatile("isync");
176#elif defined(__sparc__)
177  const size_t dword_size = 8;
178  const size_t len = (uintptr_t)end - (uintptr_t)start;
179
180  const uintptr_t mask = ~(dword_size - 1);
181  const uintptr_t start_dword = ((uintptr_t)start) & mask;
182  const uintptr_t end_dword = ((uintptr_t)start + len + dword_size - 1) & mask;
183
184  for (uintptr_t dword = start_dword; dword < end_dword; dword += dword_size)
185    __asm__ volatile("flush %0" : : "r"(dword));
186#else
187#if __APPLE__
188  // On Darwin, sys_icache_invalidate() provides this functionality
189  sys_icache_invalidate(start, end - start);
190#else
191  compilerrt_abort();
192#endif
193#endif
194}
195