1/**
2 * \file
3 * \brief ARM kernel page-table structures.
4 */
5
6/*
7 * Copyright (c) 2007, 2008, 2009, ETH Zurich.
8 * All rights reserved.
9 *
10 * This file is distributed under the terms in the attached LICENSE file.
11 * If you do not find this file, copies can be found by writing to:
12 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
13 */
14
15#ifndef KERNEL_ARCH_ARM_PAGING_H
16#define KERNEL_ARCH_ARM_PAGING_H
17
18// XXX: Not sure if these includes are required
19#include <capabilities.h>
20#include <cache.h>
21#include <barrelfish_kpi/arm_core_data.h>
22#include <barrelfish_kpi/cpu.h>
23#include <barrelfish_kpi/paging_arch.h>
24#include <cp15.h>
25
26void paging_init(lpaddr_t ram_base, size_t ram_size,
27                 struct arm_core_data *boot_core_data);
28
29void enable_mmu(lpaddr_t ttbr0, lpaddr_t ttbr1);
30
31void paging_load_pointers(struct arm_core_data *boot_core_data);
32
33void paging_map_vectors(void);
34
35/*
36 * Map a device, and return its virtual address
37 *
38 * @param base the physical address of the device
39 * @param size the size of the device's address range in bytes
40 */
41extern lvaddr_t paging_map_device(lpaddr_t base, size_t size);
42
43/**
44 * \brief Return whether we have enabled the MMU. Useful for
45 * initialization assertions
46 */
47extern bool paging_mmu_enabled(void);
48
49void paging_map_user_pages_l1(lvaddr_t table_addr, lvaddr_t vaddr, lpaddr_t paddr);
50
51void paging_set_l2_entry(uintptr_t* l2entry, lpaddr_t paddr, uintptr_t flags);
52
53void paging_context_switch(lpaddr_t table_addr);
54
55// REVIEW: [2010-05-04 orion]
56// these were deprecated in churn, enabling now to get system running again.
57
58void paging_map_memory(uintptr_t ttbase, lpaddr_t paddr, size_t bytes);
59
60static inline bool is_root_pt(enum objtype type) {
61    return type == ObjType_VNode_ARM_l1;
62}
63
64static inline size_t get_pte_size(void) {
65    // both l1_entry and l2_entry are 4 bytes
66    return 4;
67}
68#define PTABLE_ENTRY_SIZE get_pte_size()
69
70static inline void do_one_tlb_flush(genvaddr_t vaddr)
71{
72    // TODO: figure out selective flushing for ARM
73    invalidate_tlb();
74}
75
76static inline void do_selective_tlb_flush(genvaddr_t vaddr, genvaddr_t vend)
77{
78    // TODO: figure out selective flushing for ARM
79    invalidate_tlb();
80}
81
82static inline void do_full_tlb_flush(void)
83{
84    invalidate_tlb();
85}
86
87#endif // KERNEL_ARCH_ARM_PAGING_H
88