1/**
2 * \file plat_arm_vm.c
3 * \brief
4 */
5
6
7/*
8 * Copyright (c) 2016 ETH Zurich.
9 * All rights reserved.
10 *
11 * This file is distributed under the terms in the attached LICENSE file.
12 * If you do not find this file, copies can be found by writing to:
13 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
14 */
15
16#include <kernel.h>
17#include <offsets.h>
18#include <arch/arm/platform.h>
19#include <serial.h>
20#include <arch/arm/lpuart.h>
21#include <arch/arm/gic.h>
22
23#include <getopt/getopt.h>
24#include <sysreg.h>
25#include <dev/armv8_dev.h>
26#include <barrelfish_kpi/arm_core_data.h>
27#include <psci.h>
28#include <arch/armv8/global.h>
29
30/* RAM starts at 0, provided by the MMAP */
31lpaddr_t phys_memory_start= 0;
32
33/*
34 * ----------------------------------------------------------------------------
35 * GIC
36 * ----------------------------------------------------------------------------
37 */
38
39lpaddr_t platform_gic_distributor_base = 0x51a00000;
40lpaddr_t platform_gic_redistributor_base = 0x51b00000;
41
42/*
43 * ----------------------------------------------------------------------------
44 * UART
45 * ----------------------------------------------------------------------------
46 */
47
48
49/*
50 * ----------------------------------------------------------------------------
51 * Timer
52 * ----------------------------------------------------------------------------
53 */
54#define GLOBAL_TIMER_INTERRUPT 30
55
56
57/* the maximum number of UARTS supported */
58#define MAX_NUM_UARTS 1
59
60/* the serial console port */
61unsigned int serial_console_port = 0;
62
63/* the debug console port */
64unsigned int serial_debug_port = 0;
65
66/* the number of physical ports */
67unsigned serial_num_physical_ports = 1;
68
69/* uart bases */
70lpaddr_t platform_uart_base[MAX_NUM_UARTS] =
71{
72        0x5A090000
73};
74
75/* uart sizes */
76size_t platform_uart_size[MAX_NUM_UARTS] =
77{
78    0x10000
79};
80
81errval_t serial_init(unsigned port, bool initialize_hw)
82{
83    lvaddr_t base = local_phys_to_mem(platform_uart_base[port]);
84    lpuart_init(port, base, initialize_hw);
85    return SYS_ERR_OK;
86};
87
88/*
89 * Do any extra initialisation for this particular CPU (e.g. A9/A15).
90 */
91void platform_revision_init(void)
92{
93
94}
95
96/*
97 * Figure out how much RAM we have
98 */
99size_t platform_get_ram_size(void)
100{
101    return 0;
102}
103
104/*
105 * Boot secondary processors
106 */
107errval_t platform_boot_core(hwid_t target, genpaddr_t gen_entry, genpaddr_t context)
108{
109    printk(LOG_NOTE, "Invoking PSCI on: cpu=0x%lx, entry=0x%lx, context=0x%lx\n", target, gen_entry, context);
110    struct armv8_core_data *cd = (struct armv8_core_data *)local_phys_to_mem(context);
111    cd->page_table_root = armv8_TTBR1_EL1_rd(NULL);
112    cd->cpu_driver_globals_pointer = (uintptr_t)global;
113    __asm volatile("dsb   sy\n"
114                   "dmb   sy\n"
115                   "isb     \n");
116    return psci_cpu_on(target, gen_entry, context);
117}
118
119void platform_notify_bsp(lpaddr_t *mailbox)
120{
121
122}
123
124
125/*
126 * Return the core count
127 */
128size_t platform_get_core_count(void)
129{
130    return 4;
131}
132
133/*
134 * Print system identification. MMU is NOT yet enabled.
135 */
136void platform_print_id(void)
137{
138
139}
140
141/*
142 * Fill out provided `struct platform_info`
143 */
144void platform_get_info(struct platform_info *pi)
145{
146    pi->arch = PI_ARCH_ARMV8A;
147    pi->platform = PI_PLATFORM_IMX8X;
148}
149
150uint32_t platform_get_timer_interrupt(void){
151    return GLOBAL_TIMER_INTERRUPT;
152}
153
154void armv8_get_info(struct arch_info_armv8 *ai)
155{
156
157}
158