1/**
2 * \file plat_arm_vm_consts.c
3 * \brief
4 */
5
6
7/*
8 * Copyright (c) 2016 ETH Zurich.
9 * All rights reserved.
10 *
11 * This file is distributed under the terms in the attached LICENSE file.
12 * If you do not find this file, copies can be found by writing to:
13 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
14 */
15
16#include <kernel.h>
17#include <maps/cn88xx.h>
18#include <offsets.h>
19#include <arch/arm/platform.h>
20#include <arch/arm/gic.h>
21#include <serial.h>
22#include <psci.h>
23#include <arch/arm/pl011.h>
24#include <arch/armv8/global.h>
25#include <sysreg.h>
26#include <dev/armv8_dev.h>
27#include <barrelfish_kpi/arm_core_data.h>
28#include <getopt/getopt.h>
29
30
31lpaddr_t phys_memory_start = CN88XX_MAP_LMC_OFFSET;
32
33/*
34 * ----------------------------------------------------------------------------
35 * GIC
36 * ----------------------------------------------------------------------------
37 */
38
39lpaddr_t platform_gic_distributor_base = CN88XX_MAP_GIC_GICD_OFFFSET;
40lpaddr_t platform_gic_redistributor_base = CN88XX_MAP_GIC_GICRX_OFFSET;
41
42/*
43 * ----------------------------------------------------------------------------
44 * UART
45 * ----------------------------------------------------------------------------
46 */
47
48/* the maximum number of UARTS supported */
49#define MAX_NUM_UARTS 2
50
51/* the serial console port */
52unsigned int serial_console_port = 0;
53
54/* the debug console port */
55unsigned int serial_debug_port = 0;
56
57/* the number of physical ports */
58unsigned serial_num_physical_ports = 1;
59
60/* uart bases */
61lpaddr_t platform_uart_base[MAX_NUM_UARTS]= {
62    CN88XX_MAP_UART0_OFFSET,
63    CN88XX_MAP_UART1_OFFSET
64};
65
66/* uart sizes */
67size_t platform_uart_size[MAX_NUM_UARTS]= {
68    4096, 4096
69};
70
71
72errval_t serial_init(unsigned port, bool initialize_hw)
73{
74    lvaddr_t base = local_phys_to_mem(platform_uart_base[port]);
75    pl011_init(port, base, initialize_hw);
76    return SYS_ERR_OK;
77};
78
79/*
80 * Do any extra initialisation for this particular CPU (e.g. A9/A15).
81 */
82void platform_revision_init(void)
83{
84
85}
86
87/*
88 * Figure out how much RAM we have
89 */
90size_t platform_get_ram_size(void)
91{
92    return 0;
93}
94
95
96/*
97 * Boot secondary processors
98 */
99errval_t platform_boot_core(hwid_t target, genpaddr_t gen_entry, genpaddr_t context)
100{
101    printf("Invoking PSCI on: cpu=%lx, entry=%lx, context=%lx\n", target, gen_entry, context);
102    struct armv8_core_data *cd = (struct armv8_core_data *)local_phys_to_mem(context);
103    cd->page_table_root = armv8_TTBR1_EL1_rd(NULL);
104    cd->cpu_driver_globals_pointer = (uintptr_t)global;
105    __asm volatile("dsb   sy\n"
106                   "dmb   sy\n"
107                   "isb     \n");
108    return psci_cpu_on(target, gen_entry, context);
109}
110
111void platform_notify_bsp(lpaddr_t *mailbox)
112{
113
114}
115
116
117/*
118 * Return the core count
119 */
120size_t platform_get_core_count(void)
121{
122    return 48;
123}
124
125/*
126 * Print system identification. MMU is NOT yet enabled.
127 */
128void platform_print_id(void)
129{
130
131}
132
133/*
134 * Fill out provided `struct platform_info`
135 */
136void platform_get_info(struct platform_info *pi)
137{
138    pi->arch = PI_ARCH_ARMV8A;
139    pi->platform = PI_PLATFORM_CN88XX;
140}
141
142void armv8_get_info(struct arch_info_armv8 *ai)
143{
144
145}
146
147uint32_t platform_get_timer_interrupt(void){
148    return 30;
149}
150