1/* 2 * Copyright (c) 2014, University of Washington. 3 * All rights reserved. 4 * 5 * This file is distributed under the terms in the attached LICENSE file. 6 * If you do not find this file, copies can be found by writing to: 7 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich. 8 * Attn: Systems Group. 9 */ 10 11#ifndef VMX_ENCODINGS_H 12#define VMX_ENCODINGS_H 13 14// 16-bit field encodings 15 16// read-only data fields 17#define VMX_VPID 0x0 // Virtual-processor identifier (VPID) 18#define VMX_PINV 0x2 // Posted-interrupt notification vector 19#define VMX_EPTP 0x4 // EPTP index 20 21// guest-state fields 22#define VMX_GUEST_ES_SEL 0x800 // Guest ES selector 23#define VMX_GUEST_CS_SEL 0x802 // Guest CS selector 24#define VMX_GUEST_SS_SEL 0x804 // Guest SS selector 25#define VMX_GUEST_DS_SEL 0x806 // Guest DS selector 26#define VMX_GUEST_FS_SEL 0x808 // Guest FS selector 27#define VMX_GUEST_GS_SEL 0x80A // Guest GS selector 28#define VMX_GUEST_LDTR_SEL 0x80C // Guest LDTR selector 29#define VMX_GUEST_TR_SEL 0x80E // Guest TR selector 30#define VMX_GUEST_IS 0x810 // Guest interrupt status 31 32// host-state fields 33#define VMX_HOST_ES_SEL 0xC00 // Guest ES selector 34#define VMX_HOST_CS_SEL 0xC02 // Guest CS selector 35#define VMX_HOST_SS_SEL 0xC04 // Guest SS selector 36#define VMX_HOST_DS_SEL 0xC06 // Guest DS selector 37#define VMX_HOST_FS_SEL 0xC08 // Guest FS selector 38#define VMX_HOST_GS_SEL 0xC0A // Guest GS selector 39#define VMX_HOST_TR_SEL 0xC0C // Guest TR selector 40 41// 32-bit field encodings 42 43// control fields 44#define VMX_EXEC_PIN_BASED 0x4000 // Pin-based controls 45#define VMX_EXEC_PRIM_PROC 0x4002 // Primary processor-based controls 46#define VMX_EXCP_BMP 0x4004 // Exception bitmap 47#define VMX_PF_ERR_MASK 0x4006 // Page-fault error-code mask 48#define VMX_PF_ERR_MATCH 0x4008 // Page-fault error-code match 49#define VMX_CR3_TARGET_CNT 0x400A // CR3-target count 50#define VMX_EXIT_CONTROLS 0x400C // VM-exit controls 51#define VMX_EXIT_MSR_STORE_CNT 0x400E // VM-exit MSR-store count 52#define VMX_EXIT_MSR_LOAD_CNT 0x4010 // VM-exit MSR-load count 53#define VMX_ENTRY_CONTROLS 0x4012 // VM-entry controls 54#define VMX_ENTRY_MSR_LOAD_CNT 0x4014 // VM-entry MSR-load count 55#define VMX_ENTRY_INTR_INFO 0x4016 // VM-entry interruption-information field 56#define VMX_ENTRY_EXCP_ERR 0x4018 // VM-entry exception error code 57#define VMX_ENTRY_INSTR_LEN 0x401A // VM-entry instruction length 58#define VMX_TPR_THRESHOLD 0x401C // TPR threshold 59#define VMX_EXEC_SEC_PROC 0x401E // Secondary processor-based controls 60#define VMX_PLE_GAP 0x4020 // PLE_Gap 61#define VMX_PLE_WINDOW 0x4022 // PLE_Window 62 63// read-only data fields 64#define VMX_INSTR_ERROR 0x4400 // VM-instruction error 65#define VMX_EXIT_REASON 0x4402 // Exit reason 66#define VMX_EXIT_INTR_INFO 0x4404 // VM-exit interruption information 67#define VMX_EXIT_INTR_ERR 0x4406 // VM-exit interruption error code 68#define VMX_IDT_VEC_INFO 0x4408 // IDT-vectoring information field 69#define VMX_IDT_VEC_ERR 0x440A // IDT-vectoring error code 70#define VMX_EXIT_INSTR_LEN 0x440C // VM-exit instruction length 71#define VMX_EXIT_INSTR_INFO 0x440E // VM-exit instruction information 72 73// guest-state fields 74#define VMX_GUEST_ES_LIM 0x4800 // Guest ES limit 75#define VMX_GUEST_CS_LIM 0x4802 // Guest CS limit 76#define VMX_GUEST_SS_LIM 0x4804 // Guest SS limit 77#define VMX_GUEST_DS_LIM 0x4806 // Guest DS limit 78#define VMX_GUEST_FS_LIM 0x4808 // Guest FS limit 79#define VMX_GUEST_GS_LIM 0x480A // Guest GS limit 80#define VMX_GUEST_LDTR_LIM 0x480C // Guest LDTR limit 81#define VMX_GUEST_TR_LIM 0x480E // Guest TR limit 82#define VMX_GUEST_GDTR_LIM 0x4810 // Guest GDTR limit 83#define VMX_GUEST_IDTR_LIM 0x4812 // Guest IDTR limit 84#define VMX_GUEST_ES_ACCESS 0x4814 // Guest ES access rights 85#define VMX_GUEST_CS_ACCESS 0x4816 // Guest CS access rights 86#define VMX_GUEST_SS_ACCESS 0x4818 // Guest SS access rights 87#define VMX_GUEST_DS_ACCESS 0x481A // Guest DS access rights 88#define VMX_GUEST_FS_ACCESS 0x481C // Guest FS access rights 89#define VMX_GUEST_GS_ACCESS 0x481E // Guest GS access rights 90#define VMX_GUEST_LDTR_ACCESS 0x4820 // Guest LDTR access rights 91#define VMX_GUEST_TR_ACCESS 0x4822 // Guest TR access rights 92#define VMX_GUEST_INTR_STATE 0x4824 // Guest activity state 93#define VMX_GUEST_ACTIV_STATE 0x4826 // Guest activity state 94#define VMX_GUEST_SMBASE 0x4828 // Guest SMBASE 95#define VMX_GUEST_SYSENTER_CS 0x482A // Guest IA32_SYSENTER_CS 96#define VMX_GUEST_PREEMPT_TIMER 0x482E // VMX-preemption timer value 97 98// host-state fields 99#define VMX_HOST_SYSENTER_CS 0x4C00 // Host IA32_SYSENTER_CS 100 101// 64-bit field encodings 102 103// control fields 104#define VMX_IOBMP_A_F 0x2000 // Address of I/O bitmap A (full) 105#define VMX_IOBMP_A_H 0x2001 // Address of I/O bitmap A (high) 106#define VMX_IOBMP_B_F 0x2002 // Address of I/O bitmap B (full) 107#define VMX_IOBMP_B_H 0x2003 // Address of I/O bitmap B (high) 108#define VMX_MSRBMP_F 0x2004 // Address of MSR bitmaps (full) 109#define VMX_MSRBMP_H 0x2005 // Address of MSR bitmaps (high) 110#define VMX_EXIT_MSR_STORE_F 0x2006 // VM-exit MSR-store address (full) 111#define VMX_EXIT_MSR_STORE_H 0x2007 // VM-exit MSR-store address (high) 112#define VMX_EXIT_MSR_LOAD_F 0x2008 // VM-exit MSR-load address (full) 113#define VMX_EXIT_MSR_LOAD_H 0x2009 // VM-exit MSR-load address (high) 114#define VMX_ENTRY_MSR_LOAD_F 0x200A // VM-entry MSR-load address (full) 115#define VMX_ENTRY_MSR_LOAD_H 0x200B // VM-entry MSR-load address (high) 116#define VMX_EVMCS_PTR_F 0x200C // Executive-VMCS pointer (full) 117#define VMX_EVMCS_PTR_H 0x200D // Executive-VMCS pointer (high) 118#define VMX_TSC_OFF_F 0x2010 // TSC offset (full) 119#define VMX_TSC_OFF_H 0x2011 // TSC offset (high) 120#define VMX_VAPIC_F 0x2012 // Virtual-APIC address (full) 121#define VMX_VAPIC_H 0x2013 // Virtual-APIC address (high) 122#define VMX_APIC_ACC_F 0x2014 // APIC-access address (full) 123#define VMX_APIC_ACC_H 0x2015 // APIC-access address (high) 124#define VMX_PID_F 0x2016 // Posted-interrupt descriptor address (full) 125#define VMX_PID_H 0x2017 // Posted-interrupt descriptor address (high) 126#define VMX_VMFUNC_F 0x2018 // VM-function controls (full) 127#define VMX_VMFUNC_H 0x2019 // VM-function controls (high) 128#define VMX_EPTP_F 0x201A // EPT pointer (full) 129#define VMX_EPTP_H 0x201B // EPT pointer (high) 130#define VMX_EOI_EXIT_BMP0_F 0x201C // EOI-exit bitmap 0 (full) 131#define VMX_EOI_EXIT_BMP0_H 0x201D // EOI-exit bitmap 0 (high) 132#define VMX_EOI_EXIT_BMP1_F 0x201E // EOI-exit bitmap 1 (full) 133#define VMX_EOI_EXIT_BMP1_H 0x201F // EOI-exit bitmap 1 (high) 134#define VMX_EOI_EXIT_BMP2_F 0x2020 // EOI-exit bitmap 2 (full) 135#define VMX_EOI_EXIT_BMP2_H 0x2021 // EOI-exit bitmap 2 (high) 136#define VMX_EOI_EXIT_BMP3_F 0x2022 // EOI-exit bitmap 3 (full) 137#define VMX_EOI_EXIT_BMP3_H 0x2023 // EOI-exit bitmap 3 (high) 138#define VMX_EPTP_LIST_F 0x2024 // EPTP-list address (full) 139#define VMX_EPTP_LIST_H 0x2025 // EPTP-list address (high) 140#define VMX_VMREAD_BMP_F 0x2026 // VMREAD-bitmap address (full) 141#define VMX_VMREAD_BMP_H 0x2027 // VMREAD-bitmap address (high) 142#define VMX_VMWRITE_BMP_F 0x2028 // VMWRITE-bitmap address (full) 143#define VMX_VMWRITE_BMP_H 0x2029 // VMWRITE-bitmap address (high) 144#define VMX_VEXCP_INFO_F 0x202A // Virtualization-exception info. address (full) 145#define VMX_VEXCP_INFO_H 0x202B // Virtualization-exception info. address (high) 146 147// read-only data fields 148#define VMX_GPADDR_F 0x2400 // Guest-physical address (full) 149#define VMX_GPADDR_H 0x2401 // Guest-physical address (high) 150 151// guest-state fields 152#define VMX_GUEST_VMCS_LPTR_F 0x2800 // VMCS link pointer (full) 153#define VMX_GUEST_VMCS_LPTR_H 0x2801 // VMCS link pointer (high) 154#define VMX_GUEST_DCTL_F 0x2802 // Guest IA32_DEBUGCTL (full) 155#define VMX_GUEST_DCTL_H 0x2803 // Guest IA32_DEBUGCTL (high) 156#define VMX_GUEST_PAT_F 0x2804 // Guest IA32_PAT (full) 157#define VMX_GUEST_PAT_H 0x2805 // Guest IA32_PAT (high) 158#define VMX_GUEST_EFER_F 0x2806 // Guest IA32_EFER (full) 159#define VMX_GUEST_EFER_H 0x2807 // Guest IA32_EFER (high) 160#define VMX_GUEST_PGC_F 0x2808 // Guest IA32_PERF_GLOBAL_CTRL (full) 161#define VMX_GUEST_PGC_H 0x2809 // Guest IA32_PERF_GLOBAL_CTRL (high) 162#define VMX_GUEST_PDPTE0_F 0x280A // Guest PDPTE0 (full) 163#define VMX_GUEST_PDPTE0_H 0x280B // Guest PDPTE0 (high) 164#define VMX_GUEST_PDPTE1_F 0x280C // Guest PDPTE1 (full) 165#define VMX_GUEST_PDPTE1_H 0x280D // Guest PDPTE1 (high) 166#define VMX_GUEST_PDPTE2_F 0x280E // Guest PDPTE2 (full) 167#define VMX_GUEST_PDPTE2_H 0x280F // Guest PDPTE2 (high) 168#define VMX_GUEST_PDPTE3_F 0x2810 // Guest PDPTE3 (full) 169#define VMX_GUEST_PDPTE3_H 0x2811 // Guest PDPTE3 (high) 170 171// host-state fields 172#define VMX_HOST_PAT_F 0x2C00 // Host IA32_PAT (full) 173#define VMX_HOST_PAT_H 0x2C01 // Host IA32_PAT (high) 174#define VMX_HOST_EFER_F 0x2C02 // Host IA32_EFER (full) 175#define VMX_HOST_EFER_H 0x2C03 // Host IA32_EFER (high) 176#define VMX_HOST_PGC_F 0x2C04 // Host IA32_PERF_GLOBAL_CTRL (full) 177#define VMX_HOST_PGC_H 0x2C05 // Host IA32_PERF_GLOBAL_CTRL (high) 178 179// Natural-width field encodings 180 181// control fields 182#define VMX_CR0_GH_MASK 0x6000 // CR0 guest/host mask 183#define VMX_CR4_GH_MASK 0x6002 // CR4 guest/host mask 184#define VMX_CR0_RD_SHADOW 0x6004 // CR0 read shadow 185#define VMX_CR4_RD_SHADOW 0x6006 // CR4 read shadow 186#define VMX_CR3_T0 0x6008 // CR3-target value 0 187#define VMX_CR3_T1 0x600A // CR3-target value 1 188#define VMX_CR3_T2 0x600C // CR3-target value 2 189#define VMX_CR3_T3 0x600E // CR3-target value 3 190 191// read-only data fields 192#define VMX_EXIT_QUAL 0x6400 // Exit qualification 193#define VMX_IO_RCX 0x6402 // I/O RCX 194#define VMX_IO_RSI 0x6404 // I/O RSI 195#define VMX_IO_RDI 0x6406 // I/O RDI 196#define VMX_IO_RIP 0x6408 // I/O RIP 197#define VMX_GL_ADDR 0x640A // Guest-linear address 198 199// guest-state fields 200#define VMX_GUEST_CR0 0x6800 // Guest CR0 201#define VMX_GUEST_CR3 0x6802 // Guest CR3 202#define VMX_GUEST_CR4 0x6804 // Guest CR4 203#define VMX_GUEST_ES_BASE 0x6806 // Guest ES base 204#define VMX_GUEST_CS_BASE 0x6808 // Guest CS base 205#define VMX_GUEST_SS_BASE 0x680A // Guest SS base 206#define VMX_GUEST_DS_BASE 0x680C // Guest DS base 207#define VMX_GUEST_FS_BASE 0x680E // Guest FS base 208#define VMX_GUEST_GS_BASE 0x6810 // Guest GS base 209#define VMX_GUEST_LDTR_BASE 0x6812 // Guest LDTR base 210#define VMX_GUEST_TR_BASE 0x6814 // Guest TR base 211#define VMX_GUEST_GDTR_BASE 0x6816 // Guest GDTR base 212#define VMX_GUEST_IDTR_BASE 0x6818 // Guest IDTR base 213#define VMX_GUEST_DR7 0x681A // Guest DR7 214#define VMX_GUEST_RSP 0x681C // Guest RSP 215#define VMX_GUEST_RIP 0x681E // Guest RIP 216#define VMX_GUEST_RFLAGS 0x6820 // Guest RFLAGS 217#define VMX_GUEST_PDEXCP 0x6822 // Guest pending debug exceptions 218#define VMX_GUEST_SYSENTER_ESP 0x6824 // Guest IA32_SYSENTER_ESP 219#define VMX_GUEST_SYSENTER_EIP 0x6826 // Guest IA32_SYSENTER_EIP 220 221// host-state fields 222#define VMX_HOST_CR0 0x6C00 // Host CR0 223#define VMX_HOST_CR3 0x6C02 // Host CR3 224#define VMX_HOST_CR4 0x6C04 // Host CR4 225#define VMX_HOST_FS_BASE 0x6C06 // Host FS base 226#define VMX_HOST_GS_BASE 0x6C08 // Host GS base 227#define VMX_HOST_TR_BASE 0x6C0A // Host TR base 228#define VMX_HOST_GDTR_BASE 0x6C0C // Host GDTR base 229#define VMX_HOST_IDTR_BASE 0x6C0E // Host IDTR base 230#define VMX_HOST_SYSENTER_ESP 0x6C10 // Host IA32_SYSENTER_ESP 231#define VMX_HOST_SYSENTER_EIP 0x6C12 // Host IA32_SYSENTER_EIP 232#define VMX_HOST_RSP 0x6C14 // Host RSP 233#define VMX_HOST_RIP 0x6C16 // Host RIP 234 235#endif // VMX_ENCODINGS_H 236