1/* 2 * Copyright (c) 2007, 2008, 2009, 2010, 2011, 2018 ETH Zurich. 3 * All rights reserved. 4 * 5 * This file is distributed under the terms in the attached LICENSE file. 6 * If you do not find this file, copies can be found by writing to: 7 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 8 */ 9 10interface pci_driver_client "PCI driver <-> PCI server interface" { 11 /* read PCI conf header */ 12 rpc read_conf_header(in uint32 dword, out errval err, out uint32 val); 13 14 /* write PCI conf header */ 15 rpc write_conf_header(in uint32 dword, in uint32 val, out errval err); 16 17 /* Enable (legacy) interrupt */ 18 rpc irq_enable(out errval err); 19 20 /* Enable MSI-X for the specified PCI device. */ 21 rpc msix_enable_addr(in uint8 bus, in uint8 dev, in uint8 fn, 22 out errval err, 23 out uint16 vec_count); 24 rpc msix_enable(out errval err, 25 out uint16 vec_count); 26 27 /* Configure specified MSI-X vector */ 28 rpc msix_vector_init_addr(in uint8 bus, in uint8 dev, in uint8 fn, 29 in uint16 idx, /* Index of MSI-X vector */ 30 in uint8 destination, /* Interrupt Destination */ 31 in uint8 vector, /* Interrupt Vector */ 32 out errval err); 33 34 rpc msix_vector_init(in uint16 idx, /* Index of MSI-X vector */ 35 in uint8 destination, /* Interrupt Destination */ 36 in uint8 vector, /* Interrupt Vector */ 37 out errval err); 38}; 39