1/*
2 * Copyright (c) 2014 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * xeon_phi_dma.dev
11 *
12 * description: register definitions for the Xeon Phi DMA
13 */
14
15device xeon_phi_dma_chan lsbfirst(addr base) "Intel Xeon Phi DMA Channel" {
16
17    register dcar rw addr(base, 0x00) "DMA Channel Attribute Register" {
18        _ 23 "";
19        apic_irq 1 "APIC Interrupt mask bit";
20        msix_irq 1 "MSI-X Interrupt mask bit";
21        irq_status 1 "Interrupt status";
22        _ 6 "";
23    };
24
25    /*
26     * Protection Level: Ring 0
27     * Visibility: Host / Coprocessor
28     * Reset Dmain: GRPB_REset
29     * Register Access: CRU
30     * Number: 8
31     */
32    register dhpr rw addr(base, 0x04) "DMA Descriptor Head Pointer Register" {
33        index 16 "Index of the head pointer";
34        _     16 "Reserved";
35    };
36
37    /*
38     * Protection Level: Ring 0
39     * Visibility: Host / Coprocessor
40     * Reset Dmain: GRPB_REset
41     * Register Access: CRU
42     * Number: 8
43     */
44    register dtpr rw addr(base, 0x08) "DMA Descriptor Tail Pointer Register" {
45        index 16 "Index of the head pointer";
46         _    16 "Reserved";
47    };
48
49    /*
50     * Protection Level: Ring 0
51     * Visibility: Host / Coprocessor
52     * Reset Dmain: GRPB_REset
53     * Register Access: CRU
54     * Number: 8
55     */
56    register aux_lo rw addr(base, 0x0C) "DMA Auxiliary Register 0 Lo" {
57        r 32 "";
58    };
59
60    /*
61     * Protection Level: Ring 0
62     * Visibility: Host / Coprocessor
63     * Reset Dmain: GRPB_REset
64     * Register Access: CRU
65     * Number: 8
66     */
67    register aux_hi rw addr(base, 0x10)  "DMA Auxiliary Register 0 Hi" {
68        r 32 "";
69    };
70
71    constants drar_shifts "Shift amounts for the field values" {
72        drar_size_shift=2;
73        drar_base_shift=6;
74    };
75    
76    /*
77     * Protection Level: Ring 0
78     * Visibility: Host / Coprocessor
79     * Reset Dmain: GRPB_REset
80     * Register Access: CRU
81     * Number: 8
82     */
83    register drar_hi rw addr(base, 0x18) "DMA Descriptor Ring Attributes Register Lo" {
84        base     4 "base address hi part";
85        _        2 "";  
86        size    15 "size of the descriptor ring";
87        page     5 "";
88        sysbit   1 "";
89        _        5 "";
90    };
91
92    /*
93     * Protection Level: Ring 0
94     * Visibility: Host / Coprocessor
95     * Reset Dmain: GRPB_REset
96     * Register Access: CRU
97     * Number: 8
98     */
99    register drar_lo rw addr(base, 0x14) "DMA Descriptor Ring Attributes Register Lo" {
100        _        6 "";
101        base    26 "base address lo part";
102    };
103    
104
105    /*
106     * Protection Level: Ring 0
107     * Visibility: Host / Coprocessor
108     * Reset Dmain: GRPB_REset
109     * Register Access: CRU
110     * Number: 8
111     */
112    register ditr rw addr(base, 0x1C)  "DMA Interrupt Timer Register" {
113        r 32 "";
114    };
115
116    /*
117     * Protection Level: Ring 0
118     * Visibility: Host / Coprocessor
119     * Reset Dmain: GRPB_REset
120     * Register Access: CRU
121     * Number: 8
122     */
123    register dstat rw addr(base, 0x20)  "DMA Status Channel Register" {
124        completions 16 "Completition count";
125        _           16 "";
126    };
127
128    /*
129     * Protection Level: Ring 0
130     * Visibility: Host / Coprocessor
131     * Reset Dmain: GRPB_REset
132     * Register Access: CRU
133     * Number: 8
134     */
135    register dstatwb_lo rw addr(base, 0x24)  "DMA Tail Pointer Write Back Register Lo" {
136        r 32 "";
137    };
138
139    /*
140     * Protection Level: Ring 0
141     * Visibility: Host / Coprocessor
142     * Reset Dmain: GRPB_REset
143     * Register Access: CRU
144     * Number: 8
145     */
146    register dstatwb_hi rw addr(base, 0x28)  "DMA Tail Pointer Write Back Register Hi" {
147        r 32 "";
148    };
149
150    /*
151     * Protection Level: Ring 0
152     * Visibility: Host / Coprocessor
153     * Reset Dmain: GRPB_REset
154     * Register Access: CRU
155     * Number: 8
156     */
157    register dcherr rw addr(base, 0x2C)  "DMA Channel Error Register" {
158        r 32 "";
159    };
160
161    /*
162     * Protection Level: Ring 0
163     * Visibility: Host / Coprocessor
164     * Reset Dmain: GRPB_REset
165     * Register Access: CRU
166     * Number: 8
167     */
168    register dcherrmsk rw addr(base, 0x30)  "DMA Channel Error Register Mask" {
169        r 32 "";
170    };    
171};