1/* 2 * Copyright (c) 2011, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaestr. 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * uhci.dev 11 * 12 * DESCRIPTION: Universal Host Controller Interface (UHCI) description 13 * 14 * Rather old hardware - provided primarily for compatibility with qemu. 15 * Numbers in comments refer to the Intel Universal Host Controller 16 * Interface (UHCI) Design Guide Revision 1.1., March 1996. 17 */ 18 19 20device uhci msbfirst ( io base ) "UHCI USB controller" { 21 22 // 2.1.1 23 // Default value: 0x0000 24 register usbcmd rw io(base, 0x0000) "USB command" { 25 _ 8; 26 maxp 1 "Max packet (1=64 bytes, 0=32 bytes)"; 27 cf 1 "Configure flag"; 28 swdbg 1 "Software debug"; 29 fgr 1 "Force global resume"; 30 egsm 1 "Enter global suspend mode"; 31 greset 1 "Global reset"; 32 hcreset 1 "Host controller reset"; 33 rs 1 "Run/stop"; 34 }; 35 36 // 2.1.2 37 // Default value: 0x0000 38 register usbsts rwc io(base, 0x0002) "USB status" { 39 _ 10; 40 hch 1 "Host controller halted"; 41 hcpe 1 "Host controller process error"; 42 hse 1 "Host system error"; 43 rd 1 "Resume detect"; 44 uei 1 "USB error interrupt"; 45 usbint 1 "USB interrupt"; 46 }; 47 48 // 2.1.3 49 // Default value: 0x0000 50 register usbintr rw io(base, 0x0004) "USB interrupt enable" { 51 _ 12; 52 sp 1 "Short packet interrupt enable"; 53 ioc 1 "Interrupt on complete enable"; 54 ri 1 "Resume interrupt enable"; 55 tc 1 "Timeout/CRC interrupt enable"; 56 }; 57 58 // 2.1.4 59 // Default value: 0x0000 60 register frnum rw io(base, 0x0006) "Frame number" { 61 _ 5; 62 flcifn 11 "Frame list current index / frame number"; 63 }; 64 65 // 2.1.5 66 // Default value: undefined 67 // Bottom 12 bits must be zero 68 register flbaseadd rw io(base, 0x0008) "Frame list base address" 69 type(uint32); 70 71 // 2.1.6 72 // Default value: 0x40 73 // SOF cycle time = 11936 + softv; default gives 12k, which at 74 // 12MHz gives 1ms frame period. 75 register sof rw io(base, 0x000c) "Start of frame modify" { 76 _ 1; 77 softv 7 "SOF timing value"; 78 }; 79 80 // 2.1.7 81 // Default values: 0x80 82 regarray portsc io(base, 0x10)[ 2 ] "Port status and control" { 83 _ 3; 84 susp 1 rw "suspend"; 85 _ 2; 86 pr 1 rw "port reset"; 87 lsda 1 ro "low-speed device attached"; 88 _ 1; // Always read as 1 89 rd 1 rw "resume detect"; 90 ls 2 ro "line status"; 91 pedc 1 rw1c "port enable/disable change"; 92 ped 1 rw "port enabled/disabled"; 93 csc 1 rw1c "connect status change"; 94 ccs 1 ro "current connect status"; 95 }; 96 97 // 3.1 98 datatype flp "Frame list pointer" { 99 flp 28 "bits 31:4 of frame list pointer"; 100 _ 2 mbz; 101 q 1 "QH/TD select"; 102 t 1 "terminate (frame list pointer not valid)"; 103 }; 104 105 // 3.2 106 datatype td msbfirst(32) "Transfer descriptor" { 107 // link (dword 0) 108 lp 28 "bits 31:4 of link pointer"; 109 _ 1 mbz; 110 vf 1 "Depth/breadth select"; 111 q 1 "QH/TD select"; 112 t 1 "terminate (link pointer is not valid)"; 113 // control and status (dword 1) 114 _ 2; 115 spd 1 "short packet detect"; 116 ec 2 "error count"; 117 ls 1 "low speed device"; 118 ios 1 "isochronous select"; 119 ioc 1 "interrupt on complete"; 120 // Bits 23:16 of second word are status, viz: 121 active 1 "active"; 122 stalled 1 "stalled"; 123 dbe 1 "data buffer error"; 124 babble 1 "babble detected"; 125 nakr 1 "NAK received"; 126 cte 1 "CRC/Timeout error"; 127 bse 1 "bitstuff error"; 128 _ 1; 129 _ 5; 130 actlen 11 "actual length"; 131 // token (dword 2) 132 maxlen 11 "maximum length"; 133 _ 1; 134 d 1 "data toggle"; 135 endpt 4 "endpoint"; 136 devaddr 7 "device address"; 137 pid 8 "packet indentification"; 138 // buffer ptr (dword 3) 139 buffer 32 "buffer pointer"; 140 }; 141 142 // 3.3 143 datatype qhe msbfirst(32) "Queue head and element" { 144 qelp 28 "bits 31:4 of queue head or element link pointer"; 145 _ 2 mbz; 146 q 1 "QH/TD select"; 147 t 1 "terminate (qelp not valid)"; 148 }; 149 150}; 151 152