1/* 2 * Copyright (c) 2007, 2008, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * tulip.dev 11 * 12 * DESCRIPTION: DEC Tulip Ethernet controller 13 * 14 * Section numbers in this file refer to the DIGITAL Semiconductor 15 * 21140A PCI Fast Ethernet LAN Controller Hardware Reference Manual, 16 * available at http://www.intel.com/design/network/manuals/21140ahm.pdf 17 */ 18 19device tulip lsbfirst ( io base ) "Tulip Ethernet Controller" { 20 21 // 3.2.2.1 22 register CSR0 rw io ( base, 0x00 ) "Bus mode" { 23 SWR 1 "Software reset"; 24 BAR 1 "Bus arbitration"; 25 DSL 5 "Descriptor Skip Length"; 26 BLE 1 "Big/little endian"; 27 PBL 6 "Programmable burst length"; 28 CAL 2 "Cache alignment"; 29 _ 1 mbz; 30 TAP 3 "Transmit auto polling"; 31 DBO 1 "Descriptor byte ordering mode"; 32 RME 1 "Read multiple enable"; 33 _ 1 mbz; 34 RLE 1 "Read line enable"; 35 WIE 1 "Write and invalidation enable"; 36 _ 7 mbz; 37 }; 38 39 // 3.2.2.2 40 register CSR1 wo io( base, 0x08 ) "Transmit poll demand" type(uint32); 41 42 // 3.2.2.3 43 register CSR2 wo io( base, 0x10 ) "Receive poll demand" type(uint32); 44 45 // 3.2.2.4 46 register CSR3 rw io( base, 0x18 ) "Receive list base address" type(uint32); 47 register CSR4 rw io( base, 0x20 ) "Transmit list base address" type(uint32); 48 49 // 3.2.2.5 50 constants FBEBITS "Fatal bus error bits" { 51 parity = 0b000 "Parity error"; 52 mabrt = 0b001 "Master abort"; 53 tabrt = 0b010 "Target abort"; 54 }; 55 constants TPROCSTATE "Transmit process state" { 56 tpstop = 0b000 "Stopped: reset cmd or tx jabber expired"; 57 tprftd = 0b001 "Running - fetching tx desc."; 58 tprwet = 0b010 "Running - waiting for end of tx"; 59 tprrbm = 0b011 "Running - reading buf from mem & queuing tx fifo"; 60 tprset = 0b101 "Running - setup packet"; 61 tpsusp = 0b110 "Suspended - tx fifo underflow, or unavail tx desc"; 62 tprclo = 0b111 "Running - closing tx desc"; 63 }; 64 constants RPROCSTATE "Receive process state" { 65 rpstop = 0b000 "Stopped: reset or stop rx command"; 66 rprfrd = 0b001 "Running - fetching rx desc."; 67 rprcep = 0b010 "Running - checking for end of rx pkt"; 68 rprwrp = 0b011 "Running - waiting for rx packet"; 69 rpsusp = 0b100 "Suspected - unavailable rx buf"; 70 rprclo = 0b101 "Running - closing rx desc"; 71 rprflu = 0b110 "Running - flushing current frame (no rx buf)"; 72 rprqrf = 0b111 "Running - queueing rx frame to buf"; 73 }; 74 register CSR5 rw1c io( base, 0x28 ) "Status" { 75 TI 1 "Transmit interrupt"; 76 TPS 1 "Transmit process stopped"; 77 TU 1 "Transmit buffer unavailable"; 78 TJT 1 "Transmit jabber timeout"; 79 _ 1 mbz; 80 UNF 1 "Transmit underflow"; 81 RI 1 "Receive interrupt"; 82 RU 1 "Receive buffer unavailable"; 83 RPS 1 "Receive process stopped"; 84 RWT 1 "Receive watchdog timeout"; 85 ETI 1 "Early termination timeout"; 86 GTE 1 "General-purpose timer expired"; 87 _ 1 mbz; 88 FBE 1 "Fatal bus error"; 89 ERI 1 "Early receive interrupt"; 90 AIS 1 "Abnormal interrupt summary"; 91 NIS 1 "Normal interrupt summary"; 92 RS 3 ro type(RPROCSTATE) "Receive process state"; 93 TS 3 ro type(TPROCSTATE) "Transmission process state"; 94 EB 3 ro type(FBEBITS) "Error bits"; 95 _ 6 mbz; 96 } ; 97 98 // 3.2.2.6 99 register CSR6 rw io( base, 0x30 ) "Operating mode" { 100 HP 1 "Hash/perfect recieve filtering mode"; 101 SR 1 "Start/stop receive"; 102 HO 1 "Hash-only filtering mode"; 103 PB 1 "Pass bad frames"; 104 IF 1 "Inverse filtering" ; 105 SB 1 "Start/stop backoff counter"; 106 PR 1 "Promiscuous mode"; 107 PM 1 "Pass all multicast"; 108 _ 1 mbz; 109 FD 1 "Full-duplex mode"; 110 OM 2 "Operating mode"; 111 FC 1 "Force collision mode"; 112 ST 1 "Start/stop transmission command"; 113 TR 2 "Threshold control bits"; 114 _ 1 mbz; 115 CA 1 "Capture effect enable"; 116 PS 1 "Port select"; 117 HBD 1 "Heartbeat disable"; 118 _ 1 mbz; 119 SF 1 "Store and forward"; 120 TTM 1 "Transmit threshold mode"; 121 PCS 1 "PCS function"; 122 SCR 1 "Scrambler mode"; 123 _ 1 mb1; 124 _ 4 mbz; 125 RA 1 "Receive all"; 126 SC 1 "Special capture effect enable"; 127 }; 128 129 // 3.2.2.7 130 register CSR7 rw io( base, 0x38 ) "Interrupt enable" { 131 TI 1 "Transmit interrupt enable"; 132 TS 1 "Transmit stopped enable"; 133 TU 1 "Transmit buffer unavailable enable"; 134 TJ 1 "Transmit jabber timeout enable"; 135 _ 1 mbz; 136 UN 1 "Underflow interrupt enable"; 137 RI 1 "Recieve interrupt enable"; 138 RU 1 "Recieve buffer unavailable enable"; 139 RS 1 "Recieve stopped enable"; 140 RW 1 "Recieve watchdog timeout enable"; 141 ETE 1 "Early transmit interrupt enable"; 142 GPT 1 "General-purpose timer enable"; 143 _ 1 mbz; 144 FBE 1 "Fatal bus error enable"; 145 ERE 1 "Early receive enable"; 146 AI 1 "Abnormal interrupt summary enable"; 147 NI 1 "Normal interrupt summary enable"; 148 _ 15 mbz; 149 }; 150 151 // 3.2.2.8 152 register CSR8 ro io( base, 0x40 ) "Missed frames and overflow counter" { 153 MFC 16 "Missed frame counter"; 154 MFO 1 "Missed frame overflow"; 155 FOC 11 "FIFO overflow counter"; 156 OCO 1 "Overflow counter overflow"; 157 _ 3 mbz; 158 }; 159 160 // 3.2.2.9 161 register CSR9 rw io( base, 0x48 ) "Boot ROM Management" { 162 DATA 8 "Boot ROM data or serial ROM control"; 163 _ 2 mbz; 164 REG 1 "External register select"; 165 SR 1 "Serial ROM select"; 166 BR 1 "Boot ROM select"; 167 WR 1 "ROM write operation"; 168 RD 1 "ROM read operation"; 169 _ 1 mbz; 170 MDC 1 "MII management clock"; 171 MDO 1 "MII management write data"; 172 MII 1 "MII management operation mode"; 173 MDI 1 "MII management data_in"; 174 _ 12 mbz; 175 }; 176 177 // 3.2.2.10 178 register CSR10 rw io( base, 0x50 ) "Boot ROM programming address" { 179 VAL 18 "Boot ROM address"; 180 _ 14 mbz; 181 }; 182 183 // 3.2.2.11 184 register CSR11 rw io( base, 0x58 ) "General-purpose timer" { 185 VAL 16 "Timer value"; 186 CON 1 "Continuous mode"; 187 _ 15 mbz; 188 }; 189 190 // 3.2.2.12 191 register CSR12 rw io( base, 0x60 ) "General purpose port" { 192 MD 8 "General-purpose mode and data"; 193 GPC 1 "General-purpose control"; 194 _ 23 mbz; 195 }; 196 197 // 3.2.2.13 198 register CSR15 rw io( base, 0x78 ) "Watchdog timer" { 199 JBD 1 "Jabber disable"; 200 HUJ 1 "Host unjab"; 201 JCK 1 "Jabber clock"; 202 _ 1 mbz; 203 RWD 1 "Receive watchdog disable"; 204 RWR 1 "Receive watchdog release"; 205 _ 26; 206 }; 207 208 // 4.2.1 209 constants FRAMEDTYPE width(2) "Frame data type" { 210 sr = 0b00 "Serial received frame"; 211 il = 0b01 "Internal loopback frame"; 212 el = 0b10 "External loopback or serial received frame"; 213 }; 214 datatype RDES msbfirst(32) "Receive descriptor" { 215 // RDES0 216 OWN 1 "Own bit"; 217 FF 1 "Filtering fail"; 218 FL 14 "Frame length"; 219 ES 1 "Error summary"; 220 DE 1 "Descriptor error"; 221 DT 2 type(FRAMEDTYPE) "Data type"; 222 RF 1 "Runt Frame"; 223 MF 1 "Muticast frame"; 224 FS 1 "First descriptor"; 225 LS 1 "Last descriptor"; 226 TL 1 "Frame too long"; 227 CS 1 "Collision seen"; 228 FT 1 "Frame type"; 229 RW 1 "Receive watchdog"; 230 RE 1 "Report on MII error"; 231 DB 1 "Dribbling bit"; 232 CE 1 "CRC error"; 233 ZERO 1 "Zero"; 234 // RDES1 235 _ 6; 236 RER 1 "Receive end of ring"; 237 RCH 1 "Second address chained"; 238 _ 2; 239 RBS2 11 "Buffer 2 size"; 240 RBS1 11 "Buffer 1 size"; 241 // RDES2-3 242 RBA1 32 "Buffer address 1"; 243 RBA2 32 "Buffer address 2"; 244 }; 245 246 // 4.2.2 247 datatype TDES msbfirst(32) "Transmit descriptor" { 248 // TDES0 249 OWN 1 "Own bit"; 250 _ 15; 251 ES 1 "Error summary"; 252 TO 1 "Transmit jabber timeout"; 253 _ 2; 254 LO 1 "Loss of Carrier"; 255 NC 1 "No Carrier"; 256 LC 1 "Late Collision"; 257 EC 1 "Excessive Collisions"; 258 HF 1 "Heartbeat Fail"; 259 CC 4 "Collision Count"; 260 LF 1 "Link Fail Report"; 261 UF 1 "Underflow Error"; 262 DE 1 "Deferred"; 263 // TDES1 264 IC 1 "Interrupt on Completion"; 265 LS 1 "Last Segment"; 266 FS 1 "First Segment"; 267 FT1 1 "Filtering Type"; 268 SET 1 "Setup Packet"; 269 AC 1 "Add CRC Disable"; 270 TER 1 "Transmit End of Ring"; 271 TCH 1 "Second Address Chained"; 272 DPD 1 "Disabled Padding"; 273 FT0 1 "Filtering Type"; 274 TBS2 11 "Buffer 2 Size"; 275 TBS1 11 "Buffer 1 Size"; 276 // TDES2-3 277 TBA1 32 "Buffer address 1"; 278 TBA2 32 "Buffer address 2"; 279 }; 280 // Table 4-8: This value is split between FT0 and FT1 above. 281 // Unfortunately (unlike Devil) Mackerel can't express this 282 // cleanly (yet). 283 constants FILTERTYPE width(2) "Filtering type" { 284 PF = 0b00 "Perfect filtering"; 285 HF = 0b01 "Hash-based filtering"; 286 IF = 0b10 "Inverse filtering"; 287 HOF = 0b11 "Hash-only filtering"; 288 }; 289 290}; 291