1/* 2 * Copyright (c) 2011, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * sfn5122f_q.dev 11 * 12 * DESCRIPTION: Solarflare Solarstorm SFx902x Ethernet Controller Queues 13 * 14 * Numbers in comments refer to Solarstorm SFx902x Ethernet Controller family Controller Datasheet 15 * Product #: SF-103590-DS / Issue 3 16 */ 17 18device sfn5122f_q msbfirst () 19"Solarflare Solarstorm SFx902x Ethernet Controller Queues" { 20 21 // 5.156 22 datatype tx_ker_desc msbfirst(64) "Transmit physical mode descriptor" { 23 _ 1 rsvd; 24 tx_ker_cont 1 "Packet data continuation"; 25 tx_ker_byte_count 14 "Number of valid bytes in this buffer"; 26 tx_ker_buf_region 2 type(tx_ker_buf_region) 27 "Indicates which address region register should be used (upper 18 bits)"; 28 tx_ker_buf_addr 46 "Lower 46 bits of buffer's address"; 29 }; 30 31 constants tx_ker_buf_region "Address region register of buffer" { 32 tx_ker_buf_region0 = 0b00 "Address region register 0"; 33 tx_ker_buf_region1 = 0b01 "Address region register 1"; 34 tx_ker_buf_region2 = 0b10 "Address region register 2"; 35 tx_ker_buf_region3 = 0b11 "Address region register 3"; 36 }; 37 38 // 5.106 39 datatype rx_ker_desc msbfirst(64) "Receive physical mode descriptor" { 40 _ 2 rsvd; 41 rx_ker_buf_size 14 "Buffer size in bytes"; 42 rx_ker_buf_region 2 type(rx_ker_buf_region) 43 "Indicates which address region register should be used (upper 18 bits)"; 44 rx_ker_buf_addr 46 "Lower 46 bits of buffer's address"; 45 }; 46 47 constants rx_ker_buf_region "Address region register of buffer" { 48 rx_ker_buf_region0 = 0b00 "Address region register 0"; 49 rx_ker_buf_region1 = 0b01 "Address region register 1"; 50 rx_ker_buf_region2 = 0b10 "Address region register 2"; 51 rx_ker_buf_region3 = 0b11 "Address region register 3"; 52 }; 53 54 55 // advanced descriptors 56 // 5.157 57 datatype tx_user_desc msbfirst(64) "Transmit buffer mode descriptor" { 58 _ 15 rsvd; 59 tx_user_sw_ev_en 1 "Software event enable"; 60 _ 1 rsvd; 61 tx_user_cont 1 "Packet data continuation"; 62 tx_user_byte_cnt 13 "Number of valid bytes"; 63 tx_user_buf_id 20 "Buffer ID to index the buffer table"; 64 tx_user_byte_ofs 13 "Byte offset from base address"; 65 }; 66 67 // 5.107 68 datatype rx_user_desc msbfirst(32) "Receive buffer mode descriptor" { 69 rx_user_2byte_offset 12 "2-byte offset from base address of buffer"; 70 rx_user_buf_id 20 "Buffer ID to index the buffer table"; 71 }; 72 73 74 // Evevent queue 75 // 5.72 76 datatype event_entry msbfirst(64) "Event entry" { 77 ev_code 4 "Event code"; 78 ev_data 60 "Event data"; 79 }; 80 81 constants ev_code "Event code" { 82 rx_ev = 0b0000 "RX event"; 83 tx_ev = 0b0010 "TX event"; 84 driver_ev = 0b0101 "Driver event"; 85 global_ev = 0b0110 "Global event"; 86 drv_gen_ev = 0b0111 "DRV_GEN_EV"; 87 user_ev = 0b1000 "User event"; 88 mcdi_val = 0b1010 "Value used by MCDI protocol"; 89 }; 90 91 // 5.71 92 datatype driver_ev msbfirst(64) "Char or Kernel driver events" { 93 _ 4 rsvd; 94 driver_ev_subcode 4 type(driver_ev_subcode) 95 "Driver event sub-code"; 96 _ 42 rsvd; 97 driver_ev_subdata 14 "Driver event sub-data"; 98 }; 99 100 constants driver_ev_subcode "SRAM bank size" { 101 fls_evq_id = 0b0000 "FLS_EVQ_ID"; 102 rcv_desc_q_flush = 0b0001 "Receive descriptor queue flush done"; 103 event_q_init = 0b0010 "Event queue initialization done"; 104 srm_upd_ = 0b0101 "SRAM update done"; 105 wakeup_ev = 0b0110 "Wake up event"; 106 error_packet_type = 0b1001 "Packet is neither TCP nor UDP"; 107 timer_event = 0b1010 108 "Timer event happens (triggerd/immedate start mode)"; 109 rx_desc_err_event = 0b1110 "RX Descriptor Error Event"; 110 tx_desc_err_event = 0b1111 "TX Descriptor Error Event"; 111 }; 112 113 // 5.73 114 datatype rx_ev msbfirst(64) "Receive Completion event" { 115 _ 5 rsvd; 116 rx_ev_pkt_not_parsed 1 "Receive packet not parsed"; 117 rx_ev_ipv6_pkt 1 "Receive packet is IPv6"; 118 rx_ev_pkt_ok 1 "Receive packet contains no error"; 119 rx_ev_pause_frm_err 1 "Undocumented bit"; 120 rx_ev_buf_owner_id 1 121 "Receive buffer owner ID missmatch with buffer table"; 122 rx_ev_ip_frag_err 1 "Receive packet IP header checksum error"; 123 rx_ev_ip_hdr_chksum_err 1 "Receive packet IP header checksum error"; 124 rx_ev_tcp_udp_chksum_err 1 "Receive packet TCP/UDP checksum error"; 125 rx_ev_eth_crc_err 1 "Receive Ethernet CRC error"; 126 rx_ev_frm_trunc 1 "Receive frame truncated"; 127 _ 1 rsvd; 128 rx_ev_tobe_disc 1 "Receive packet to be discarded by software"; 129 rx_ev_pkt_type 3 type(rx_ev_pkt_type) 130 "Receive packet type"; 131 rx_ev_hdr_type 2 type(rx_ev_hdr_type) 132 "Receive packet header type"; 133 rx_ev_desc_q_empty 1 "Receive descriptor queue is empty"; 134 rx_ev_mcast_hask_match 1 "Receive multicast has match"; 135 rx_ev_mcast_ptk 1 "Receive packet is multicast"; 136 _ 2 rsvd; 137 rx_ev_q_label 5 "Queue label"; 138 rx_ev_jumbo_cont 1 "Receive jumbo packet (not end-of-packet)"; 139 rx_ev_port 1 "Port number of packet"; 140 rx_ev_byte_ctn 14 "Receive packet byte count"; 141 rx_ev_sop 1 "Buffer for Start of packet"; 142 rx_ev_iscsi_pkt_ok 1 "iSCSI packet no error"; 143 rx_ev_iscsi_ddig_er 1 "iSCSI data digest error"; 144 rx_ev_iscsi_hdig_err 1 "iSCSI header digest error"; 145 rx_ev_desc_ptr 12 "Receive descriptor pointer"; 146 }; 147 148 constants rx_ev_hdr_type "Receive packet header type" { 149 rx_header_tcp = 0b00 "IPv4/IPv6 TCP packet"; 150 rx_header_udp = 0b01 "IPv4/IPv6 UDP packet"; 151 rx_header_neither = 0b10 "IPv4/IPv6 neither TCP nor UDP packet"; 152 rx_header_none = 0b11 "Not IPv4/IPv6"; 153 }; 154 155 constants rx_ev_pkt_type "Receive packet type" { 156 rx_ptype_ethr = 0b000 "Plain Ethernet"; 157 rx_ptype_llc_snap = 0b001 "LLC/SNAP"; 158 rx_ptype_jumbo = 0b010 "Jumbo"; 159 rx_ptype_vlan = 0b011 "VLAN"; 160 rx_ptype_vlan_llc_snap = 0b100 "VLAN w/LLC/SNAP"; 161 rx_ptype_vlan_jumbo = 0b101 "VLAN Jumbo"; 162 }; 163 164 // 5.74 would be 128 bits 165 datatype tx_ev msbfirst(64) "Receive Completion event" { 166 _ 25 rsvd; 167 tx_ev_pkt_err 1 "Error while reading TX data"; 168 tx_ev_pkt_too_big 1 "Packet too big to fit trasnmit FIFO"; 169 tx_ev_q_label 5 170 "Queue label programmed in trasmit descriptor point table"; 171 _ 16 rsvd; 172 tx_ev_wq_ff_full 1 "TX pacing queue full"; 173 tx_ev_buf_owner_id_err 1 174 "Indicates current descriptor that has the error"; 175 _ 1 rsvd; 176 tx_ev_comp 1 "Transmit completion event"; 177 tx_ev_desc_ptr 12 "Transmit descriptor pointer"; 178 }; 179 180 // 5.75 181 // TODO user_ev_reg_value ?? 182 datatype usr_ev msbfirst(64) "User event" { 183 _ 22 rsvd; 184 user_qid 10 "Originating quid"; 185 user_ev_reg_value 32 "USR_EV_REG"; 186 }; 187 188 189 190 191}; 192