1/* 2 * Copyright (c) 2011, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * sfn5211f.dev 11 * 12 * DESCRIPTION: Solarflare Solarstorm SFx902x Ethernet Controller family 13 * 14 * Numbers in comments refer to Solarstorm SFx902x Ethernet Controller family Controller Datasheet 15 * Product #: SF-103590-DS / Issue 3 16 */ 17 18device sfn5122f msbfirst ( addr base ) 19"Solarflare SFx902x Ethernet Controller Family"{ 20 21 /************************************ 22 * 5.1 Global CSR Block 23 ***********************************/ 24 25 // 5.3 26 27 register csr_spare_reg_hi rw addr(base, 0x00000318) "Spare register low"{ 28 _ 32 rsvd; 29 memr_perr_en 32 "Memory parity error enable bits"; 30 }; 31 32 register csr_spare_reg_lo rw addr(base, 0x00000310) "Spare register high"{ 33 _ 32 rsvd; 34 csr_spare_bits 32 "Spare bits"; 35 }; 36 37 // 5.6 38 // reserved bits are not mapped 39 register cs_debug_reg_lo ro addr(base, 0x00000270) "Debug register" { 40 _ 22 rsvd; 41 cs_port_num 2 type(cs_port_num)"Port number register"; 42 _ 40 rsvd; 43 }; 44 45 // reserved bits are not mapped 46 register cs_debug_reg_hi ro addr(base, 0x00000278) "Debug register" { 47 _ 63 rsvd; 48 bit 1 ""; 49 }; 50 51 constants cs_port_num "Port Number" { 52 port_0 = 0b01 "Port 0"; 53 port_1 = 0b10 "Port 1"; 54 }; 55 56 // 5.9 57 register dp_ctrl_reg_lo rw addr(base, 0x00000250) "Datapath control register" { 58 _ 52 rsvd; 59 fls_evq_id 12 "Flush done event event queue ID"; 60 }; 61 62 register dp_ctrl_reg_hi rw addr(base, 0x00000258) "Datapath control register" { 63 _ 63 rsvd; 64 bit 1 ""; 65 }; 66 67 // 5.12 would be 128 bits 68 regarray driver_reg_lo rw addr(base, 0x00000280) [8; 0x10] "Driver scratch register" { 69 _ 32 rsvd; 70 driver_dw0 32 "Driver scratch space dword"; 71 }; 72 73 regarray driver_reg_hi rw addr(base, 0x00000288) [8; 0x10] "Driver scratch register" { 74 _ 32 rsvd; 75 driver_dw0 32 "Driver scratch"; 76 }; 77 78 79 // 5.15 would be 128 bits 80 // (bits rx_buf/txbuf_onw_int_ker not documented found in driver code) 81 82 register fatal_intr_reg_ker_lo rw addr(base, 0x00000230) 83 "Fatal interrupt register for Kernel" { 84 _ 19 rsvd; 85 sram_perr_int_p_ker_en 1 86 "SRAM memory parity error interrupt enable for opposite port"; 87 mbu_perr_int_ker_en 1 "MBU memory parrity error interrupt enable"; 88 _ 2 rsvd; 89 mem_perr_int_ker_en 1 90 "Internal memory parity error interrupt enable"; 91 rxbuf_own_int_ker_en 1 "RX buffer interrupt enable"; 92 txbuf_own_int_ker_en 1 "TX buffer interrupt enable"; 93 _ 3 rsvd; 94 evf_oflo_int_ker_en 1 "Event queue FIFO overflow interrupt enable"; 95 ill_adr_int_ker_en 1 "Illegal address error interrupt enable"; 96 srm_perr_int_ker_en 1 "SRAM parity error interrupt enable"; 97 _ 19 rsvd; 98 sram_perr_int_p_ker 1 rc 99 "SRAM memory parity error occurred in opposite port"; 100 mbu_perr_int_ker 1 rc "PCI MBU memory parity error"; 101 _ 2 rsvd; 102 mem_perr_int_ker 1 rc "Internal memory parity error interrupt"; 103 _ 5 rsvd; 104 evf_oflo_intker 1 rc "Event queue FIFO overlfow"; 105 ill_adr_int_ker 1 rc "Illegal address error"; 106 srm_perr_int_ker 1 rc "SRAM parity error"; 107 }; 108 109 register fatal_intr_reg_ker_hi rw addr(base, 0x00000238) "" { 110 bit 64 "bit"; 111 }; 112 113 // 5.18 would be 128 bits 114 register mem_stat_reg_lo ro addr(base, 0x00000260) "Memory status register" { 115 _ 29 rsvd; 116 mem_perr_vec 35 ro "Memory parity error vector"; 117 }; 118 119 register mem_stat_reg_hi ro addr(base, 0x00000268) "Memory status register" { 120 _ 63 rsvd; 121 bit 1 ""; 122 }; 123 124// Not specified in documentation 125 126 register altera_build_reg_lo rw addr(base, 0x00000300) "Altera build register" { 127 _ 32 rsvd; 128 altera_build_ver 32 "Spare bits"; 129 }; 130 131 register altera_build_reg_hi rw addr(base, 0x00000308) "Altera build register" { 132 _ 63 rsvd; 133 bit 1 ""; 134 }; 135 136 /************************************ 137 * Bus Interface Unit Block 138 ***********************************/ 139 140 141 // 5.22 142 register adr_region_reg_hi rw addr(base, 0x00000008) 143 "Address region register high bits" { 144 _ 14 rsvd; 145 adr_region1 18 "Upper 18 bits of 46-bit address region #1"; 146 _ 14 rsvd; 147 adr_region0 18 "Upper 18 bits of 46-bit address region #0"; 148 }; 149 150 register adr_region_reg_lo rw addr(base, 0x00000000) 151 "Address region register low bits" { 152 _ 14 rsvd; 153 adr_region1 18 "Upper 18 bits of 46-bit address region #1"; 154 _ 14 rsvd; 155 adr_region0 18 "Upper 18 bits of 46-bit address region #0"; 156 }; 157 158 159 160 161 // 5.25 162 register hw_init_reg_lo rw addr(base, 0x000000c0) 163 "Hardware initialization register low bits" { 164 _ 18 rsvd; 165 b2b_reg_en 1 "Enables back to back request in bdmrq"; 166 _ 1 rsvd; 167 post_wr_mask 4 168 "Space out every write to every target by this many cycles"; 169 _ 3 rsvd; 170 tlp_tc 3 "For testing read completion"; 171 tlp_attr 2 "For testing read completion"; 172 _ 16 rsvd; 173 wd_timer 8 174 "Watch dog timer for reading non-mapped or non-implemented addresses"; 175 _ 2 rsvd; 176 us_disable 1 "Disable un-supported status return"; 177 tlp_ep 1 "Testing constructing posted write"; 178 attr_sel 1 179 "For testing, when constructing a posted write TLP"; 180 _ 1 rsvd; 181 tlp_sel 1 "For testing, enables using TLP_TD"; 182 tlp_td 1 "For testing, write TLP"; 183 }; 184 185 register hw_init_reg_hi rw addr(base, 0x000000c8) 186 "Hardware initialization register high bits" { 187 _ 7 rsvd; 188 tx_mrg_tags 1 189 "Tx Descriptor Read Requests can share/use TX DMA read tags"; 190 _ 20 rsvd; 191 dorbell_drop 8 rc "Counter for dorbell with push dropped"; 192 _ 28 rsvd; 193 }; 194 195 // bits 0:63 would be legacy interrupt vecor or legacy_int_vec? 196 197 register int_adr_reg_ker_hi rw addr(base, 0x00000038) 198 "Interrupt host address for Kernel driver high bits" { 199 _ 63 rsvd; 200 norm_int_vec_dis_ker 1 "Normal interrupt vector write disable"; 201 }; 202 203 register int_adr_reg_ker_lo rw addr(base, 0x00000030) 204 "Interrupt host address for Kernel driver low bits" { 205 net_ivec_fatal_int 1 "Interrupt Generator"; 206 legacy_int_vec 63 "LEGACY_INT_VEC"; 207 }; 208 209 210 // 5.31 would be 128 bits bit 211 register int_en_reg_ker_lo rw addr(base, 0x00000010) 212 "Kernel driver Interrupt enable register" { 213 _ 50 rsvd; 214 ker_int_leve_sel 6 215 "Should always be set to 0 when MSI-X interrupts are being used"; 216 _ 4 rsvd; 217 ker_int_ker 1 "not documented"; 218 _ 2 rsvd; 219 drv_int_en_ker 1 "Interrupt enable"; 220 }; 221 222 register int_en_reg_ker_hi rw addr(base, 0x00000018) 223 "Kernel driver Interrupt enable register" { 224 _ 63 rsvd; 225 bit 1 ""; 226 }; 227 228 // 5.34 would be 128 bits (higher bits should never be read) 229 register int_isr0_reg_lo ro addr(base, 0x00000090) 230 "Interrupt Acknowlege Status register" { 231 int_isr_reg 32 ro 232 "Satus of pending interrupts of the function (non MSI/MSI-X)"; 233 }; 234 235 // 5.43 would be 128 bits 236 237 register usr_ev_cfg_lo rw addr(base, 0x00000100) 238 "Documentaion to be written for usr_ev_config" { 239 _ 47 rsvd; 240 usrev_dis 1 ""; 241 _ 6 rsvd; 242 dflt_evq 10 ""; 243 }; 244 245 register usr_ev_cfg_hi rw addr(base, 0x00000108) 246 "Documentaion to be written for usr_ev_config" { 247 _ 63 rsvd; 248 bit 1 ""; 249 }; 250 251 /* 252 // 5.46 253 regarray usr_ev_reg_lo wo addr(base, 0x00000540) [1024; 0x2000] "Table" { 254 _ 32 rsvd; 255 usr_ev_data 32 wo "31 bits of data to be posted to USER_EV"; 256 }; 257 258 regarray usr_ev_reg_hi wo addr(base, 0x00000548) [1024; 0x2000] "Table" { 259 _ 63 rsvd; 260 bit 1 ""; 261 }; 262 */ 263 /************************************ 264 * SRAM Block 265 ***********************************/ 266 267 //5.49 268 269// regarray buf_full_tbl rw addr(base, 0x00800000) [147456; 0x8] "Buffer Table" { 270 regarray buf_full_tbl rw addr(base, 0x00800000) [8196; 0x8] "Buffer Table" { 271 buf_full_unused 13 "unused bits"; 272 ip_dat_buf_size 1 type(ip_dat_buf_size) 273 "Buffer size"; 274 buf_adr_region 2 type(buf_adr_region) 275 "Address region to be used for upper 18 bits"; 276 buf_adr_fbuf 34 "Buffer physical address middle bits [45:12]"; 277 buf_owner_id_fbuf 14 "Buffer owner ID"; 278 }; 279 280 constants buf_adr_region "Address region" { 281 region_0 = 0b00 "Adress Region 0"; 282 region_1 = 0b01 "Adress Region 1"; 283 region_2 = 0b10 "Adress Region 2"; 284 region_3 = 0b11 "Adress Region 3"; 285 }; 286 287 constants ip_dat_buf_size "Buffer size" { 288 buff_size_4k = 0b00 "Buffer size 4k"; 289 buff_size_8k = 0b01 "Buffer size 8k, not supported"; 290 }; 291 292 // 5.52 would be 128 bits 293 294 register buf_tbl_cfg_reg_lo addr(base, 0x00000600) 295 "Buffer table configuration register" { 296 _ 61 rsvd; 297 buf_tbl_mode 1 type(buf_tbl_mode) 298 "Buffer table mode"; 299 _ 2 rsvd; 300 }; 301 302 register buf_tbl_cfg_reg_hi addr(base, 0x00000608) 303 "Buffer table configuration register" { 304 _ 63 rsvd; 305 bit 1 ""; 306 }; 307 308 constants buf_tbl_mode "Buffer table mode" { 309 half_mode_4b = 0b00 "4 bytes per entry"; 310 full_mobe_8b = 0b01 "8 bytes per entry"; 311 }; 312 313 // 5.55 would be 128 bits 314 315 register buf_tbl_upd_reg_lo wo addr(base, 0x00000650) 316 "Buffer table update register" { 317 buf_upd_cmd 1 "Buffer table update command"; 318 buf_clr_cmd 1 319 "Buffer table clear command. Cleared from start - end"; 320 _ 10 rsvd; 321 buf_clr_end_id 20 "Starting buffer ID to be cleared"; 322 _ 12 rsvd; 323 buf_clr_start_id 20 "Ending buffer ID to be cleared"; 324 }; 325 326 register buf_tbl_upd_reg_hi wo addr(base, 0x00000658) 327 "Buffer table update register" { 328 _ 63 rsvd; 329 bit 1 ""; 330 }; 331 332 // 5.58 would be 128 bits (bit 2 not documented) 333 register srm_parity_reg_lo rw addr(base, 0x00000670) "SRAM parity register" { 334 _ 61 rsvd; 335 bypass_ecc 1 "Puts ECC into bypass mode"; 336 sec_int 1 337 "Single/Double error corrects/detect contribute fatal interrupt register bits"; 338 _ 1 rsvd; 339 }; 340 341 register srm_parity_reg_hi rw addr(base, 0x00000678) "SRAM parity register" { 342 _ 63 rsvd; 343 bit 1 ""; 344 }; 345 346 // 5.61 would be 128 bits 347 register srm_cfg_reg_lo rw addr(base, 0x00000630) 348 "SRAM configuration register" { 349 _ 58 rsvd; 350 srn_oob_adr_inten 1 351 "SRAM out-of-bound address checking interrupt enable"; 352 srm_oob_buf_inten 1 353 "SRAM out-of-bound buffer ID checking interrupt enable"; 354 srm_init_en 1 "SRAM initialization enabled"; 355 srm_num_bank 1 type(srm_num_bank) 356 "Number of SRAM banks"; 357 srm_bank_size 2 type(srm_bank_size) 358 "On-board SRAM bank size"; 359 }; 360 361 register srm_cfg_reg_hi rw addr(base, 0x00000638) 362 "SRAM configuration register" { 363 _ 63 rsvd; 364 bit 1 ""; 365 }; 366 367 constants srm_bank_size "SRAM bank size" { 368 srm_size_72k = 0b00 "72K deep SRAM"; 369 reserved_0 = 0b01 "reserved0"; 370 reserved_1 = 0b10 "reserved1"; 371 reserved_2 = 0b11 "reserved2"; 372 }; 373 374 constants srm_num_bank "SRAM bank size" { 375 srm_num_bank_1 = 0b0 "1 bank"; 376 srm_num_bank_2 = 0b1 "2 bank"; 377 }; 378 379 // 5.64 would be 128 bits 380 register srm_rx_dc_cfg_reg_lo rw addr(base, 0x00000610) 381 "SRAM receive descriptor cache configuration regsiter" { 382 _ 42 rsvd; 383 srm_clk_tmp_en 1 "undocumented field"; 384 srm_rx_dc_base_adr 21 385 "Receive descriptor cache startilng address in SRAM"; 386 }; 387 388 register srm_rx_dc_cfg_reg_hi rw addr(base, 0x00000618) 389 "SRAM receive descriptor cache configuration regsiter" { 390 _ 63 rsvd; 391 bit 1 ""; 392 }; 393 394 395 // 5.67 would be 128 bits 396 register srm_tx_dc_cfg_reg_lo rw addr(base, 0x00000620) 397 "SRAM transmit descriptor cache configuration regsiter" { 398 _ 43 rsvd; 399 srm_tx_dc_base_adr 21 400 "Transmit descriptor cache startilng address in SRAM"; 401 }; 402 403 register srm_tx_dc_cfg_reg_hi rw addr(base, 0x00000628) 404 "SRAM transmit descriptor cache configuration regsiter" { 405 _ 63 rsvd; 406 bit 1 ""; 407 }; 408 409 // 5.70 would be 128 bits- 410 register srm_upd_evq_reg_lo rw addr(base, 0x00000660) 411 "Buffer talbe update register" { 412 _ 52 rsvd; 413 srm_upd_evq_id 12 414 "Event queue to be used to return SRAM update done events"; 415 }; 416 417 register srm_upd_evq_reg_hi rw addr(base, 0x00000668) 418 "Buffer talbe update register" { 419 _ 63 rsvd; 420 bit 1 ""; 421 }; 422 423 /************************************ 424 * Event Time Block 425 ***********************************/ 426 427 // 5.78 Must be written as DWORD 428 register drv_ev_reg_lo wo addr(base, 0x00000440) 429 "Driver generated event register low bits" { 430 drv_ev_data 64 431 "Driver writes to this register to manufacture event"; 432 }; 433 434 register drv_ev_reg_hi wo addr(base, 0x00000448) 435 "Driver generated event register high bits" { 436 _ 52 rsvd; 437 drv_ev_qid 12 "Event queue ID"; 438 }; 439 440 // 5.81 441 442 443 register evq_cnt1_reg_lo ro addr(base, 0x00000460) 444 "Event counter 1 register low bits"{ 445 evq_rx_req_cnt_lo 4 "Number of RX event requests bits 3:0"; 446 evq_em_req_cnt 20 "Number of EM event requests"; 447 evq_csr_req_cnt 20 "Number of CSR event requests"; 448 evq_err_req_cnt 20 "Number of error event requests"; 449 }; 450 451 register evq_cnt1_reg_hi ro addr(base, 0x00000468) 452 "Event counter 1 register high bits"{ 453 _ 1 rsvd; 454 evq_cnt_pre_fifo 7 "Number of entries in the event pre-FIFO"; 455 evq_cnt_tobiu 20 "Number of events delivered to the BIU"; 456 evq_tx_req_cnt 20 "Number of TX event requests"; 457 evq_rx_req_cnt_lo 16 "Number of RX event requests bits 19:4"; 458 }; 459 // 5.84 460 461 462 register evq_cnt2_reg_lo ro addr(base, 0x00000470) 463 "Event counter 2 register low bits"{ 464 evq_wu_req_cnt 4 "Number of wake-up event requests bits 3:0"; 465 evq_wet_req_cnt 20 "Number of write event timer requests"; 466 evq_init_req_cnt 20 "Number of event init event requests"; 467 evq_tm_req_cnt 20 "Number of timer event requests"; 468 }; 469 470 471 register evq_cnt2_reg_hi ro addr(base, 0x00000478) 472 "Event counter 2 register high bits"{ 473 _ 4 rsvd; 474 evq_upd_req_ctn 20 "Number of update requests"; 475 evq_clr_req_cnt 20 "Number of clear requests"; 476 evq_rdy_cnt 4 "Number of entries in event post-FIFO"; 477 evq_wu_req_cnt 16 "Number of wake-up event requests bits 19:4"; 478 }; 479 480 // 5.87 would be 128 bits 481 register evq_ctrl_reg_lo rw addr(base, 0x00000450) 482 "Event queue control register"{ 483 _ 39 rsvd; 484 rx_evq_wakeup_mask 10 "Defines how wake-up events are delivered"; 485 evq_ownerr_ctrl 1 "Ecent queue owner ID error control"; 486 evq_fifo_at_th 7 487 "Event queue FIFO almost full interrupt threshold"; 488 evq_fifo_notaf_th 7 489 "Event queue FIFO not almost full interrupt threshold"; 490 }; 491 492 register evq_ctrl_reg_hi rw addr(base, 0x00000458) 493 "Event queue control register"{ 494 _ 63 rsvd; 495 bit 1 ""; 496 }; 497 // 5.90 would be 128 bits 498 regarray evq_ptr_tbl_lo rw addr(base, 0x00f60000) [1024; 0x10] 499 "Event queue pointer table"{ 500 _ 23 rsvd; 501 evq_rptr_ign 1 ro 502 "Hardware maintainend only (Prevents DOS attack)"; 503 evq_dos_ptrotect_en 1 "Enables RPTP dos protection"; 504 evq_nxt_wptr 15 ro "Next event write pointer"; 505 evq_en 1 "Event queue enable"; 506 evq_size 3 type(evq_size)"Event queue size"; 507 evq_buf_base_id 20 "Event queue buffer base ID"; 508 }; 509 510 regarray evq_ptr_tbl_hi rw addr(base, 0x00f60008) [1024; 0x10] 511 "Event queue pointer table"{ 512 _ 63 rsvd; 513 bit 1 ""; 514 }; 515 516 constants evq_size "Event queue size" { 517 evq_size_512 = 0b000 "512 Entries"; 518 evq_size_1k = 0b001 "1k Entries"; 519 evq_size_2k = 0b010 "2k Entries"; 520 evq_size_4k = 0b011 "4k Entries"; 521 evq_size_8k = 0b100 "8k Entries"; 522 evq_size_16k = 0b101 "16k Entries"; 523 evq_size_32k = 0b110 "32k Entries"; 524 }; 525 526 // 5.93 527 // TODO two addresses ! 528 regarray evq_rptr_reg wo addr(base, 0x00fa0000) [1024; 0x10] 529 "Event queue read pointer register" { 530 _ 16 rsvd; 531 evq_rptr_vld 1 "undocumented filed"; 532 evq_rptr 15 "If written queue's pointer is update"; 533 }; 534 535 regarray evq_rptr_reg_2 wo addr(base, 0x00000400) [1024; 0x2000] 536 "Event queue read pointer register" { 537 _ 16 rsvd; 538 evq_rptr_vld 1 "undocumented filed"; 539 evq_rptr 15 "If written queue's pointer is update"; 540 }; 541 542 // 5.102 would be 128 bits 543 regarray timer_command_reg_lo wo addr(base, 0x00000420) [1024; 0x2000] 544 "Timer command register table" { 545 _ 48 rsvd; 546 tc_timer_mode 2 type(tc_timer_mode)"see TIMER_MODE"; 547 tc_timer_val 14 "see TIMER_VAL"; 548 }; 549 550 regarray timer_command_reg_hi wo addr(base, 0x00000428) [1024; 0x2000] 551 "Timer command register table" { 552 _ 63 rsvd; 553 bit 1 ""; 554 }; 555 556 constants tc_timer_mode "Event queue size" { 557 timer_mode_dis = 0b00 "Timer disabled"; 558 timer_mode_immed_start = 0b01 "Immediate start mode"; 559 timer_mode_trig_start = 0b10 "Receive trigger start mode"; 560 timer_mode_int_hldoff = 0b11 "Interrupt hold-off mode"; 561 }; 562 563 564 // 5.105 would be 128 bits 565 regarray timer_tbl_lo rw addr(base, 0x00f70000) [1024; 0x10] "Timer table" { 566 _ 30 rsvd; 567 timer_q_en 1 "tells timer logic that event queue is enabled"; 568 int_armd 1 "Used by HW"; 569 int_pend 1 "Used by HW"; 570 host_notify_mode 1 "Controls what timer modes are available"; 571 reload_timer_val 14 "Hold value to reload timer on expiration"; 572 timer_mode 2 "Timer counting mode"; 573 timer_val 14 "Timer value to be used for count-down"; 574 }; 575 576 regarray timer_tbl_hi rw addr(base, 0x00f70008) [1024; 0x10] "Timer table" { 577 _ 63 rsvd; 578 bit 1 ""; 579 }; 580 /************************************ 581 * Receive Datapath Block 582 ************************************/ 583 584 // 5.110 585 // TODO constants for rx_ownerr_ctl 586 587 register rx_cfg_reg_lo rw addr(base, 0x00000800) 588 "Receive configuration register low bits" { 589 rx_hdr_split_pld_buf_size 2 590 "Size of payload buffer(s) in 32-byte words bits 1:0"; 591 rx_hdr_split_hdr_buf_size 9 592 "Size of haeder buffer(s) in 32-byte words"; 593 rx_pre_rff_ipg 4 594 "Inter-packet gap between frames from Pre-RFF FIFO"; 595 rx_tcp_sup 1 596 "Enable for TCP packets toeplitz has based 2-tuple IP addresses"; 597 rx_ingr_en 1 "undocumented field"; 598 rx_ip_hash 1 "Enable IPv4 toeplitz has support"; 599 rx_hash_alg 1 "Enables Toeplitz has algorithm"; 600 rx_hash_insrt_hdr 1 601 "Enables Toeplitz hash result and type insertion"; 602 rx_desc_push_en 1 "undocumented field"; 603 _ 4 rsvd; 604 rx_ownerr_ctl 1 "Receive owner ID error control"; 605 rx_xon_tx_th 5 606 "Receive Xon flow control threshold for status FIFO"; 607 rx_xoff_tx_th 5 608 "Receive Xoff flow control threshold for status FIFO"; 609 rx_usr_buf_size 9 "Receive user buffer size 32-byte units"; 610 rx_xon_mac_th 9 "Receive Xon flow control threshold"; 611 rx_xoff_mac_th 9 "receive Xoff flow control threshold"; 612 rx_xoff_mac_en 1 "Receive Xoff flow control enable"; 613 }; 614 615 register rx_cfg_reg_hi rw addr(base, 0x00000808) 616 "Receive configuration register high bits" { 617 _ 42 rsvd; 618 rx_min_kbuf_size 14 "Lower bound of kernel buffer size in bytes"; 619 rx_hdr_split_en 1 "Global enable for header split feature"; 620 rx_hdr_split_pld_buf_size 7 621 "Size of payload buffer(s) in 32-byte words bits 8:2"; 622 }; 623 624 // 5.113 would be 128 bits 625 register rx_dc_cfg_reg_lo rw addr(base, 0x00000840) 626 "Receive descriptor cache configuration register" { 627 _ 62 rsvd; 628 rx_dc_size 2 type(rx_dc_size) 629 "Receive descriptor cache size"; 630 }; 631 632 register rx_dc_cfg_reg_hi rw addr(base, 0x00000848) 633 "Receive descriptor cache configuration register" { 634 _ 63 rsvd; 635 bit 1 ""; 636 }; 637 638 constants rx_dc_size "Descriptor cache size" { 639 rx_dc_size_8 = 0b00 "8 descriptors"; 640 rx_dc_size_16 = 0b01 "16 descriptors"; 641 rx_dc_size_32 = 0b10 "32 descriptors"; 642 rx_dc_size_64 = 0b11 "64 descriptors"; 643 }; 644 645 // 5.116 646 register rx_dc_pf_wm_reg_lo rw addr(base, 0x00000850) 647 "Receive descriptor cache pre-fetch watermark register" { 648 _ 52 rsvd; 649 rx_dc_pf_hwm 6 "Receive descriptor pre-fetch high wm"; 650 rx_dc_pf_lwm 6 "Receive descriptor pre-fetch low wm"; 651 }; 652 653 register rx_dc_pf_wm_reg_hi rw addr(base, 0x00000858) 654 "Receive descriptor cache pre-fetch watermark register" { 655 _ 63 rsvd; 656 bit 1 ""; 657 }; 658 659 // 5.119 660 regarray rx_desc_ptr_tbl_hi rw addr(base, 0x00f40008) [1024; 0x10] 661 "Receive descriptor pointer table high bits" { 662 _ 37 rsvd; 663 rx_hdr_split 1 "Queue is header queue of header-split pair"; 664 _ 1 rsvd; 665 rx_iscsi_ddig_en 1 "Receive iSCSI data digest enable"; 666 rx_iscsi_hdig_en 1 "Receive iSCSI header digest enable"; 667 rx_desc_pref_act 1 ro 668 "Receive descriptor pre-fetch request outstanding"; 669 rx_dc_hw_rptr 6 ro 670 "Hardware read pointer to descriptor cache"; 671 rx_descq_hw_rptr 12 ro 672 "Hardware read pointer to descriptor ring"; 673 rx_descq_sw_wptr 4 ro 674 "Software write pointer to the descriptor ring bits 11:8"; 675 }; 676 677 regarray rx_desc_ptr_tbl_lo rw addr(base, 0x00f40000) [1024; 0x10] 678 "Receive descriptor pointer table low bits " { 679 rx_descq_sw_wptr 8 ro 680 "Software write pointer to the descriptor ring bits 7:0"; 681 rx_descq_buf_base_id 20 682 "Queue buffer base ID programmed by software"; 683 rx_descq_evq_id 12 "Event queue id for descriptor queue"; 684 rx_descq_owner_id 14 "Owner of this DMA queue"; 685 rx_descq_label 5 "Queue label to be returned to event queue"; 686 rx_descq_size 2 type(rx_descq_size) "Descriptor queue size"; 687 rx_descq_type 1 "Descriptor queue type"; 688 rx_descq_jumbo 1 type(rx_descq_jumbo) 689 "Allow writing jumbo packets into memory"; 690 rx_descq_en 1 "Receive descriptor queue enable"; 691 }; 692 693 694 constants rx_descq_size "Descriptor queue size" { 695 rx_descq_size_512 = 0b00 "512 descriptors"; 696 rx_descq_size_1k = 0b01 "1K descriptors"; 697 rx_descq_size_2k = 0b10 "2K descriptors"; 698 rx_descq_size_4k = 0b11 "4K descriptors"; 699 }; 700 701 constants rx_descq_jumbo "Descriptor operatin in scatter mode " { 702 rx_descq_jumbo_non_scatter = 0b0 "Operate in non-scatter mode"; 703 rx_descq_jumbo_scatter = 0b1 "Operate in scatter mode"; 704 }; 705 706 // 5.122 707 regarray rx_desc_upd_reg_lo wo addr(base, 0x00000830) [1024; 0x2000] 708 "Receive descriptor update register low bits" { 709 rx_desc 64 "Receive descriptor"; 710 }; 711 712 regarray rx_desc_upd_reg_hi wo addr(base, 0x00000838) [1024; 0x2000] 713 "Receive descriptor update register high bits " { 714 _ 20 rsvd; 715 rx_desc_wptr 12 "Descriptor pointing to NEXT write descriptor"; 716 rx_desc_push_cmd 1 type(rx_desc_push_cmd) 717 "Descriptor pushed along with pointer update"; 718 _ 31 rsvd; 719 }; 720 constants rx_desc_push_cmd "Descriptor pushed" { 721 rx_desc_no_push = 0b0 "Just write pointer"; 722 rx_desc_push = 0b1 "Descriptor to follow in next address"; 723 }; 724 725 // 5.125 726 register rx_filter_ctl_reg_lo rw addr(base, 0x00000810) 727 "Receive filter control registers low bits" { 728 multicast_nomatch_q_id_lo 7 "Resulting queue ID if no match low bits 6:0"; 729 multicast_nomatch_rss_enabled 1 "Generate Toeplitz has if no match"; 730 multicast_nomatch_ip_override 1 "Override RX IP filter if no match"; 731 unicast_nomatch_q_id 12 "Default queue id if no match found"; 732 unicast_nomatch_rss_enabled 1 "Generate Toeplitz has if no match found"; 733 unicast_nomatch_ip_override 1 "Override RX IP Filter if no match found"; 734 scatter_enbl_no_match_q 1 735 "Enables buffer scatter for packets with no match in IP filter table"; 736 udp_full_srch_limit 8 737 "Limits the number of hops in full UDP searching"; 738 _ 8 rsvd; 739 udp_wild_srch_limit 8 740 "Limits the number of hops in wildcard UPD searching"; 741 tcp_wild_srch_limit 8 742 "Limits the number of hops in wildcard TCP searching"; 743 tcp_full_srch_limit 8 744 "Limits the number of hops in full TCP searching"; 745 }; 746 747 register rx_filter_ctl_reg_hi rw addr(base, 0x00000818) 748 "Receive filter control registers high bits" { 749 _ 26 rsvd; 750 ethernet_wildcard_search_limit 8 751 "Number of table entries to examine during wildcard filter search"; 752 ethernet_full_search_limit 8 753 "Number of table entries to examine during full filter search"; 754 rx_filter_all_vlan_ethertypes 1 "Filter VLAN IDs for all VLAN Ethertypes"; 755 rx_vlan_match_ethertype 16 "Outer VLAN Ethertype"; 756 multicast_nomatch_q_id_hi 5 "Resulting queue ID if no match high bits 11:7"; 757 }; 758 759 // 5.128 760 regarray rx_filter_tbl_lo rw addr(base, 0x00f00000) [8192; 0x20] 761 "Receive filter table low bits" { 762 dest_port_tcp 16 763 "Destination port number TCP full/wildcard"; 764 src_ip 32 "Source IP address"; 765 src_tcp_dest_udp 16 766 "Sourch port number of TCP full or destination UDP wildcard"; 767 }; 768 769 regarray rx_filter_tbl_hi rw addr(base, 0x00f00008) [8192; 0x20] 770 "Receive filter table high bits" { 771 _ 17 rsvd; 772 rss_en 1 "Enable Indirection Table"; 773 scatter_en 1 "Enable buffer scatter"; 774 tcp_udp 1 "TCP or UDP indicator"; 775 rxq_id 12 "Receive queue ID"; 776 dest_ip 32 "Destination IP address"; 777 }; 778 constants tcp_udp "TCP or UDP indicator" { 779 udp = 0b0 "UDP"; 780 tcp = 0b1 "TCP"; 781 }; 782 783 784 // 5.1231 would be 128 bits 785 register rx_flush_descq_reg_lo wo addr(base, 0x00000820) 786 "Receive flush descriptor queue register" { 787 _ 39 rsvd; 788 rx_flush_descq_cmd 1 "Command to flush indicated descriptor queue"; 789 _ 12 rsvd; 790 rx_flush_descq 12 "receive descriptor queue number to be flushed"; 791 }; 792 793 register rx_flush_descq_reg_hi wo addr(base, 0x00000828) 794 "Receive flush descriptor queue register" { 795 _ 63 rsvd; 796 bit 1 ""; 797 }; 798 799 // 5.134 800 // padded to 8 bits documentation is 7 bits 801 regarray rx_indirection_tbl rw addr(base, 0x00fb0000) [128; 0x10] 802 "RX indirection table" 803 type(it_queue); 804 805 regtype it_queue "Contains indirection result" { 806 _ 2 rsvd; 807 it_queue 6 "Contains indirection result"; 808 }; 809 810 // 5.137 811 regarray rx_mac_filter_tbl_lo rw also addr(base, 0x00f00010) [512; 0x20] 812 "Receive Ethernet filter table low bits" { 813 rmft_rxq_id_lo 3 "Receive queue ID low bits 2:0"; 814 rmft_wildcard_match 1 "Entry matches in wildcard searches only"; 815 rmft_dest_mac 44 "Destination MAC address"; 816 _ 4 rsvd; 817 rmft_vlan_id 12 "Destination VLAN ID"; 818 }; 819 820 regarray rx_mac_filter_tbl_hi rw also addr(base, 0x00f00018) [512; 0x20] 821 "Receive Ethernet filter table low bits" { 822 _ 52 rsvd; 823 rmft_rss_en 1 "Enable Indirection Table if match"; 824 rmft_scatter_en 1 "Enable buffer scatter if match"; 825 rmft_ip_override 1 826 "Match in RX Ethernet filter table will override match in RX filter talbe"; 827 rmft_rxq_id_hi 9 "Receive queue ID high bits 11:3"; 828 }; 829 830 // 5.140 would be 128 bits 831 register rx_nodesc_drop_reg_lo rc addr(base, 0x00000880) 832 "Receive dropped packet counter register" { 833 _ 32 rsvd; 834 rx_nodesc_drop_cnt 32 "Count of dropped packets by RX module"; 835 }; 836 837 register rx_nodesc_drop_reg_hi rc addr(base, 0x00000888) 838 "Receive dropped packet counter register" { 839 _ 63 rsvd; 840 bit 1 ""; 841 }; 842 // 5.143 would be 128 bits 843 register rx_push_drop_reg_lo rc addr(base, 0x000008b0) 844 "Receive descriptor push droped count register" { 845 _ 32 rsvd; 846 rx_nodesc_drop_cnt 32 "Count of descriptor pushes dropped"; 847 }; 848 849 register rx_push_drop_reg_hi rc addr(base, 0x000008b8) 850 "Receive descriptor push droped count register" { 851 _ 63 rsvd; 852 bit 1 ""; 853 }; 854 855 // 5.146 856 register rx_rss_ipv6_reg1_lo rw addr(base, 0x000008d0) 857 "IPv6 RSS Toeplitz has key bytes 63:0" { 858 rx_rss_ipv6_tkey_lo_lo 64 "IPv6 RSS Toeplitz hash key 63:0"; 859 }; 860 register rx_rss_ipv6_reg1_hi rw addr(base, 0x000008d8) 861 "IPv6 RSS Toeplitz has key bytes 127:64" { 862 rx_rss_ipv6_tkey_lo_hi 64 "IPv6 RSS Toeplitz hash key 127:64"; 863 }; 864 865 // 5.149 866 register rx_rss_ipv6_reg2_lo rw addr(base, 0x000008e0) 867 "IPv6 RSS Toeplitz has key bytes 191:128" { 868 rx_rss_ipv6_tkey_mid_lo 64 "IPv6 RSS Toeplitz hash key 191:128"; 869 }; 870 871 register rx_rss_ipv6_reg2_hi rw addr(base, 0x000008e8) 872 "IPv6 RSS Toeplitz has key bytes 255:192" { 873 rx_rss_ipv6_tkey_mid_hi 64 "IPv6 RSS Toeplitz hash key 255:128"; 874 }; 875 876 // 5.152 877 register rx_rss_ipv6_reg3_lo rw addr(base, 0x000008f0) 878 "IPv6 RSS Toeplitz has key bytes 320:256" { 879 rx_rss_ipv6_tkey_hi 64 "IPv6 RSS Toeplitz hash key 320:256"; 880 }; 881 882 register rx_rss_ipv6_reg3_hi rw addr(base, 0x000008f8) 883 "IPv6 RSS Toeplitz has key bytes 320:256" { 884 _ 61 rsvd; 885 rx_rss_ipv6_thash_enable 1 "Global enable IPv6 Toeplitz hash"; 886 rx_rss_ipv6_ip_thash_enable 1 887 "Enable generation of Toeplitz hash non-TCP IPv6"; 888 rx_rss_ipv6_tcp_suppress 1 889 "Force generation 2-tuple hash for IPv6/TCP"; 890 }; 891 892 // 5.155 893 register rx_rss_tkey_reg_lo rw addr(base, 0x00000860) 894 "RSS Toeplitz has key low bytes" { 895 rx_rss_tkey_lo 64 "RSS Toeplitz hash key low"; 896 }; 897 898 register rx_rss_tkey_reg_hi rw addr(base, 0x00000868) 899 "RSS Toeplitz has key high bytes" { 900 rx_rss_tkey_hi 64 "RSS Toeplitz hash key high"; 901 }; 902 903 904 /************************************ 905 * Transmit Datapath Block 906 ************************************/ 907 908 // 5.160 909 // TODO tx_ownerr_ctl constant ? 910 register tx_cfg_reg_lo rw addr(base, 0x00000a50) 911 "Transmit configuration register low bits" { 912 tx_vlan_match_ethertype_range 16 "Outer VLAN Ethertype"; 913 tx_filter_en_bit 1 "Enable TX filtering"; 914 _ 16 rsvd; 915 tx_ip_id_p0_ofs 15 "Transmit IP ID port 0 offset"; 916 _ 10 rsvd; 917 tx_no_eop_disc_en 1 918 "Enables discarding of corrupting TX packets"; 919 _ 2 rsvd; 920 tx_ownerr_ctl 1 "Transmit owner ID error control"; 921 _ 1 rsvd; 922 tx_ip_id_rep_en 1 923 "Transmit IP identification field replacement enable"; 924 }; 925 926 register tx_cfg_reg_hi rw addr(base, 0x00000a58) 927 "Transmit configuration register high bits" { 928 _ 6 rsvd; 929 tx_cont_lookup_thresh_range 8 930 "TX control word buffer TX filter lookup buffer threshold"; 931 tx_filter_test_mode 1 "Forces full lookup on all packets"; 932 tx_eth_filter_wild_search_range 8 933 "Wildcard search depth Ethernet filter"; 934 tx_eth_filter_full_search_range 8 "Full search depth Ethernet filter"; 935 tx_udpip_filter_wild_search_range 8 936 "Wildcard search depth for IPv4/UPD filter"; 937 tx_udpip_filter_full_search_range 8 "Full search depth IPv4/UDP filter"; 938 tx_tcpip_filter_wild_search_range 8 939 "Wildcard search depth for IPv4/TCP filter"; 940 tx_tcpip_filter_full_search_range 8 "Full search depth IPv4/TCP filter"; 941 tx_filter_all_vlan_ethertype_range 1 942 "Filter VLAN IDs for all VLAN Ethertypes"; 943 }; 944 945 // 5.163 would be 128 bits 946 register tx_dc_cfg_reg_lo rw addr(base, 0x00000a20) 947 "Transmit descriptor cache configuration register" { 948 _ 62 rsvd; 949 tx_dc_size 2 type(tx_dc_size) 950 "Transmit descriptor cache size"; 951 }; 952 953 register tx_dc_cfg_reg_hi rw addr(base, 0x00000a28) 954 "Transmit descriptor cache configuration register" { 955 _ 63 rsvd; 956 bit 1 ""; 957 }; 958 959 constants tx_dc_size " TX Descriptor cache size" { 960 tx_dc_size_8 = 0b00 "8 descriptors"; 961 tx_dc_size_16 = 0b01 "16 descriptors"; 962 tx_dc_size_32 = 0b10 "32 descriptors"; 963 tx_dc_size_r = 0b11 "reserved"; 964 }; 965 966 // 5.166 967 regarray tx_desc_ptr_tbl_lo rw addr(base, 0x00f50000) [1024; 0x10] 968 "Transmit descriptor pointer table low bits" { 969 tx_descq_sw_wptr 8 ro 970 "Software write pointer to the descriptor ring bits 7:0"; 971 tx_descq_buf_base_id 20 "Queue buffer base ID programmed by software"; 972 tx_descq_evq_id 12 "Event queue id for descriptor queue"; 973 tx_descq_owner_id 14 "Owner of this DMA queue"; 974 tx_descq_label 5 "Queue label to be returned to event queue"; 975 tx_descq_size 2 "Descriptor queue size"; 976 tx_descq_type 2 type(tx_descq_size) 977 "Descriptor adressing mode"; 978 tx_descq_flush 1 "Descriptor queue flush"; 979 }; 980 981 regarray tx_desc_ptr_tbl_hi rw addr(base, 0x00f50008) [1024; 0x10] 982 "Transmit descriptor pointer table high bits" { 983 _ 32 rsvd; 984 tx_dpt_q_mask_widht 2 985 "Masks out the lower TX_DPT_Q_MAS_WIDHT bits"; 986 tx_dtp_eth_filter_en 1 "Enable Ethernet filtering"; 987 tx_dtp_ip_filter_en 1 "Enable IPv4 TCP/UDP filtering"; 988 tx_non_ip_drop_dis 1 989 "Disable IPv4 TCP/UDP filtering if 0 non-IPv4 TCP/UDP filter enable"; 990 tx_ip_chksm_dis 1 "Disables IP checksum offload"; 991 tx_tcp_chksm_dis 1 "Disables TCP/UDP checksum offload"; 992 tx_descq_en 1 "Transmit descriptor queue enable"; 993 tx_iscsi_ddig_en 1 "Transmit iSCSI data digest enable"; 994 tx_iscsi_hdig_en 1 "Transmit iSCSI header digest enable"; 995 tx_dc_hw_rptr 6 ro "Hardware read pointer to descriptor cache"; 996 tx_descq_hw_rptr 12 ro "Hardware read pointer to descriptor ring"; 997 tx_descq_sw_wptr 4 ro 998 "Software write pointer to the descriptor ring bits 11:8"; 999 1000 }; 1001 1002 constants tx_descq_size "Descriptor queue size" { 1003 tx_descq_size_512 = 0b00 "512 descriptors"; 1004 tx_descq_size_1k = 0b01 "1K descriptors"; 1005 tx_descq_size_2k = 0b10 "2K descriptors"; 1006 tx_descq_size_4k = 0b11 "4K descriptors"; 1007 }; 1008 1009 // 5.169 1010 regarray tx_desc_upd_reg_lo wo addr(base, 0x00000a10) [1024; 0x2000] 1011 "Char & user transmit descriptor update register low bits" { 1012 tx_desc 64 "Transmit descriptor bits 63:0"; 1013 }; 1014 1015 regarray tx_desc_upd_reg_hi wo addr(base, 0x00000a18) [1024; 0x2000] 1016 "Char & user transmit descriptor update register" { 1017 _ 20 rsvd; 1018 tx_desc_wptr 12 "Decriptor write pointer"; 1019 tx_desc_push_cmd 1 "push descriptor into next address"; 1020 tx_desc 31 "Transmit descriptor bits 94:64"; 1021 }; 1022 1023 // 5.172 1024 /* Don't need it for now 1025 regarray tx_filter_tbl_lo rw addr(base, 0x00fc0000) [8192; 0x10] 1026 "Transmit filter table low bits" { 1027 tift_dest_port_tcp 16 1028 "Destination port number TCP full/wildcard"; 1029 tift_src_ip 32 "Source IP address"; 1030 tift_src_tcp_dest_udp 16 1031 "Sourc port number TCP full or destination UDP wildcard"; 1032 }; 1033 */ 1034 /* TODO no support for transmit filtering in code yet 1035 regarray tx_filter_tbl_hi rw addr(base, 0x00fc0008) [8192; 0x10] 1036 "Transmit filter table" { 1037 _ 19 rsvd; 1038 tift_tcp_udp 1 type(tift_tcp_udp) 1039 "TCP or UDP indicator"; 1040 tift_txq_id 12 "Transmit queue ID"; 1041 tift_dest_ip 32 "Destination IP address"; 1042 }; 1043 1044 constants tift_tcp_udp "TCP or UDP indicator" { 1045 tift_udp = 0b0 "UDP"; 1046 tift_tcp = 0b1 "TCP"; 1047 }; 1048 */ 1049 1050 // 5.175 would be 128 bits 1051 register tx_flush_descq_reg_lo wo addr(base, 0x00000a00) 1052 "Transmit flush descriptor queue register" { 1053 _ 51 rsvd; 1054 tx_flush_descq_cmd 1 "Flush indicated Trasmit descriptor queue"; 1055 tx_flush_descq 12 "Transmit descriptor queue number flushed"; 1056 }; 1057 1058 register tx_flush_descq_reg_hi wo addr(base, 0x00000a08) 1059 "Transmit flush descriptor queue register" { 1060 _ 63 rsvd; 1061 bit 1 ""; 1062 }; 1063 1064 // 5.178 1065 /* 1066 regarray tx_mac_filter_tbl_lo rw also addr(base, 0x00fe0000) [512; 0x10] 1067 "Transmit Ethernet filter table low bits" { 1068 tmft_txq_id 3 "Transmit queue ID bits 2:0"; 1069 tmft_wildcard_match 1 "Match wildcard searches only"; 1070 tmft_src_mac 44 "Source MAC address"; 1071 _ 4 rsvd; 1072 tmft_vlan_id 12 "Destination VLAN ID"; 1073 }; 1074 1075 regarray tx_mac_filter_tbl_hi rw also addr(base, 0x00fe0008) [512; 0x10] 1076 "Transmit Ethernet filter table high bits" { 1077 _ 55 rsvd; 1078 tmft_txq_id 9 "Transmit queue ID bits 11:3"; 1079 }; 1080 */ 1081 // 5.181 would be 128 bits 1082 register tx_pace_drop_qid_lo_reg rc addr(base, 0x00000aa0) 1083 "PACE Drop QID Counter" { 1084 _ 48 rsvd; 1085 tx_pace_qid_drp_cnt 16 "Count of Dropped QIDs"; 1086 }; 1087 1088 register tx_pace_drop_qid_hi_reg rc addr(base, 0x00000aa8) 1089 "PACE Drop QID Counter" { 1090 _ 63 rsvd; 1091 bit 1 ""; 1092 }; 1093 1094 // 5.184 would be 128 bits 1095 register tx_pace_reg_lo rw addr(base, 0x00000a90) 1096 "Transmit pace control register" { 1097 _ 55 rsvd; 1098 tx_pace_fb_base 4 1099 "Transmit pace fast bin base starting location"; 1100 tx_pace_bin_th 5 "Transmit pacing binning threshold"; 1101 }; 1102 1103 register tx_pace_reg_hi rw addr(base, 0x00000a98) 1104 "Transmit pace control register" { 1105 _ 63 rsvd; 1106 bit 1 ""; 1107 }; 1108 1109 // 5.187 would be 128 bits 1110 regarray tx_pace_tbl_lo rw addr(base, 0x00f80000) [1024; 0x10] "Transmit pacing table" { 1111 _ 59 rsvd; 1112 tx_pace 5 "Descriptor queue flush"; 1113 }; 1114 1115 regarray tx_pace_tbl_hi rw addr(base, 0x00f80008) [1024; 0x10] "Transmit pacing table" { 1116 _ 63 rsvd; 1117 bit 1 ""; 1118 }; 1119 // TODO right constants ? problems with c code 1120 /* 1121 constants tx_pace "Descriptor queue size" { 1122 tx_pace_00 = 0b00000 "0 micro sec"; 1123 tx_pace_02 = 0b00001 "0.2 micro sec"; 1124 tx_pace_04 = 0b00010 "0.4 micro sec"; 1125 tx_pace_08 = 0b00011 "0.8 micro sec"; 1126 tx_pace_1_6 = 0b00100 "1.6 micro sec"; 1127 tx_pace_3_2 = 0b00101 "3.2 micro sec"; 1128 tx_pace_6_4 = 0b00110 "6.4 micro sec"; 1129 tx_pace_12_8 = 0b00111 "12.8 micro sec"; 1130 tx_pace_25_6 = 0b01000 "25.6 micro sec"; 1131 tx_pace_51_2 = 0b01001 "51.2 micro sec"; 1132 tx_pace_100 = 0b01010 "100 micro sec"; 1133 tx_pace_200 = 0b01011 "200 micro sec"; 1134 tx_pace_400 = 0b01100 "400 micro sec"; 1135 tx_pace_800 = 0b01101 "800 micro sec"; 1136 tx_pace_1_6n = 0b01110 "1.6 nano sec"; 1137 tx_pace_3_2n = 0b01111 "3.2 nano sec"; 1138 tx_pace_6_4n = 0b10000 "6.4 nano sec"; 1139 tx_pace_12_8n = 0b10001 "12.8 nano sec"; 1140 tx_pace_25_6n = 0b10010 "25.6 nano sec"; 1141 tx_pace_51_2n = 0b10011 "51.2 nano sec"; 1142 tx_pace_100n = 0b10100 "100 nano sec"; 1143 tx_pace_200n = 0b10101 "200 nano sec"; 1144 tx_pace_400n = 0b10110 "400 nano sec"; 1145 tx_pace_800n = 0b10111 "800 nano sec"; 1146 tx_pace_1_6m = 0b11000 "1.6 msec"; 1147 tx_pace_3_2m = 0b11010 "3.2 msec"; 1148 tx_pace_50k = 0b10011 "5 msec"; 1149 tx_pace_100k = 0b10100 "10 msec "; 1150 }; 1151 */ 1152 // 5.190 would be 128 bits 1153 register tx_push_drop_reg_lo rc addr(base, 0x00000a60) 1154 "Transmit push dropped register" { 1155 _ 32 rsvd; 1156 tx_push_drop_cnt 32 1157 "Number of pushed descriptor not taken by hw"; 1158 }; 1159 1160 register tx_push_drop_reg_hi rc addr(base, 0x00000a68) 1161 "Transmit push dropped register" { 1162 _ 63 rsvd; 1163 bit 1 ""; 1164 }; 1165 // 5.193 1166 register tx_reserved_reg_lo rw addr(base, 0x00000a80) 1167 "Transmit configuration register low bits" { 1168 _ 3 rsvd; 1169 tx_drop_abort_en 1 "TX drop aborted DLLP enable"; 1170 tx_soft_evt_en 1 1171 "Software TX user per descriptor event enable"; 1172 _ 1 rsvd; 1173 tx_rx_spacer_en 1 "TX DMA spacer enable when exceed threshold"; 1174 _ 5 rsvd; 1175 tx_pref_spacer 8 "TX pre-fetch slowdown spacer"; 1176 tx_pref_wd_tmr 22 "Transmit pre-fetch watch-dog timer"; 1177 tx_only1tag 1 1178 "Transmit read limit to one outstanding request at a time"; 1179 tx_pref_threshold 2 type(tx_pref_threshold) 1180 "Transmit pre_fetch threshold"; 1181 tx_one_pkt_per_q 1 "One packet per queue"; 1182 tx_dis_non_ip_ev 1 1183 "Disable generation of TX_PKT_NON_TCP_UDP event"; 1184 _ 1 rsvd; 1185 tx_dma_spacer 8 "Transmit DMA spacer (slow down DMA)"; 1186 tx_flush_min_len_en 1 "Transmit owner ID error control"; 1187 _ 3 rsvd; 1188 tx_max_cpl 2 type(tx_max_cpl) 1189 "Number of transmit descriptor per batched transmit event"; 1190 tx_max_pref 2 type(tx_max_pref) 1191 "Max number of descriptor pre-fetches per queue"; 1192 }; 1193 1194 // Field tx_push_en not documentet (from linux driver) 1195 register tx_reserved_reg_hi rw addr(base, 0x00000a88) 1196 "Transmit configuration register high bits" { 1197 _ 7 rsvd; 1198 tx_pref_age_cnt 2 ro "Count of pre-fetch aging occurances"; 1199 _ 28 rsvd; 1200 tx_push_en 1 "TX_PUSH_EN"; 1201 tx_push_chk_dis 1 "Push checksum disable"; 1202 _ 17 rsvd; 1203 tx_rx_spacer 8 "TX DMA spacer when exceeds high threshold"; 1204 }; 1205 1206 1207 constants tx_max_pref "Max number of descriptor pre-fetches per queue" { 1208 tx_max_pref_0 = 0b00 "no limit"; 1209 tx_max_pref_8 = 0b01 "8 descriptors"; 1210 tx_max_pref_16 = 0b10 "16 descriptors"; 1211 tx_max_pref_32 = 0b11 "32 descriptors"; 1212 }; 1213 1214 constants tx_max_cpl 1215 "Number of transmit descriptor per batched transmit event" { 1216 tx_max_max_0 = 0b00 "no limit"; 1217 tx_max_max_8 = 0b01 "4 descriptors"; 1218 tx_max_max_16 = 0b10 "8 descriptors"; 1219 tx_max_max_32 = 0b11 "16 descriptors"; 1220 }; 1221 1222 constants tx_pref_threshold "Transmit pre-fetch threshold" { 1223 tx_pre_threshold_0 = 0b00 "pre-fetch when <= 0 descriptors"; 1224 tx_pre_threshold_2 = 0b01 "pre-fetch when <= 2 descriptors"; 1225 tx_pre_threshold_4 = 0b10 "pre-fetch when <= 4 descriptors"; 1226 tx_pre_threshold_6 = 0b11 "pre-fetch when <= 6 descriptors"; 1227 }; 1228 1229 /************************************ 1230 * Sideband Management Block 1231 ***********************************/ 1232 1233 // 5.599 1234 regarray mc_dma_buf_state_0 ro addr(base, 0x0018c060) [4;0x4] 1235 "Word 0 of buffer state (one for each buffer)" { 1236 mc_dma_buf_state_rd_ptr 16 "Read pointer 16-byte words"; 1237 mc_dma_buf_state_wr_ptr 16 "Write pointer in 16-byte words"; 1238 }; 1239 1240 // 5.602 1241 regarray mc_dma_buf_state_1 rw addr(base, 0x0018c070) [4;0x4] 1242 "Word 1 of buffer state (one for each buffer)" { 1243 _ 3 rsvd; 1244 mc_dma_buf_state_fill 13 ro "Num. of 16 byte words in buffer"; 1245 _ 3 rsvd; 1246 mc_dma_buf_state_af_wmark 13 1247 "Buffer almost full watermark (16-byte words)"; 1248 }; 1249 1250 // 5.605 1251 regarray mc_dma_buf_state_2 rw addr(base, 0x0018c080) [4;0x4] 1252 "Word 2 of buffer state (one for each buffer)" { 1253 _ 1 rsvd; 1254 mc_dma_buf_state_empty 1 ro "buffer is empty"; 1255 mc_dma_buf_state_full 1 ro "buffer is full"; 1256 mc_dma_buf_state_af 1 ro "buffer is almost full"; 1257 _ 16 rsvd; 1258 mc_dma_buf_state_eaddr 6 "buffer end addr in 1K-byte words"; 1259 mc_dma_buf_state_saddr 6 "Buffer start addr in 1K-byte words"; 1260 }; 1261 1262 // 5.608 1263 register mc_dma_buf_status_reg rc addr(base, 0x0018c0a4) 1264 "DMA buffer status register" { 1265 _ 28 rsvd; 1266 mc_dma_tx_cmd_cntr_decr 4 1267 "One bit for each DMA buffer, set when TX command completes for that buffer"; 1268 }; 1269 1270 // 5.611 1271 register mc_dma_indr_buf_acc_reg rw addr(base, 0x0018c090) 1272 "" { 1273 _ 30 rsvd; 1274 mc_dma_indr_buf_acc_val 2 type(buffer); 1275 }; 1276 1277 constants buffer "Selected Buffer" { 1278 buffer_ncsi_mac = 0b00 "Buffer 0/NCSI-MAC"; 1279 buffer_port_0 = 0b01 "Buffer 1/Network port 0"; 1280 buffer_port_1 = 0b10 "Buffer 2/Network port 1"; 1281 buffer_all = 0b11 "Buffer 3 (all of packet memory)"; 1282 }; 1283 1284 // 5.614 1285 regarray mc_dma_pkt_drop_buf_full_cntr rc addr(base, 0x0018c040) [3;0x4] 1286 "Packet drop count for each port due to buffer full" { 1287 dma_pkt_drop_buf_full_cntr 32 1288 "Packet drop count for each port (buffer full)"; 1289 }; 1290 1291 // 5.617 1292 regarray mc_dma_pkt_drop_data_ff_full_cntr rc addr(base, 0x0018c030) [3;0x4] 1293 "Packet drop count due to FIFO full" { 1294 dma_pkt_drop_data_data_ff_full_cntr 32 1295 "Packet drop count for each port (FIFO full)"; 1296 }; 1297 1298 // 5.620 1299 regarray mc_dma_pkt_drop_evq_full_cntr rc addr(base, 0x0018c050) [3;0x4] 1300 "Packet drop count due to rx event queue full" { 1301 dma_pkt_drop_evq_full_full_cntr 32 1302 "Packet drop count for each port (RX event q full)"; 1303 }; 1304 1305 // MC_DMA_PMEM not in yet -> too big 1306 1307 // 5.626 1308 regarray mc_dma_rx_evq ro addr(base, 0x0018c010) [3;0x4] 1309 "RX event queues" { 1310 _ 3 rsvd; 1311 mc_dma_rx_evq_len 16 "Packet length in bytes including padding"; 1312 mc_dma_rx_evq_addr 12 "Packet starts at this 16-byte address"; 1313 mc_dma_rx_evq_crc_err 1 "packet has MAC CRC error"; 1314 }; 1315 1316 // 5.629 1317 regarray mc_dma_rx_evq_checksum ro addr(base, 0x0018c094) [3;0x4] 1318 "RX event queues" { 1319 mc_dma_rx_evq_chksum 16 ""; 1320 }; 1321 1322 // 5.632 padded to 8 bits documentation is 4 1323 register mc_dma_status_reg ro addr(base, 0x0018c000) 1324 "DMA command andevent queue statsu register" { 1325 _ 4 rsvd; 1326 mc_dma_status_rx_evq_vld2 1 1327 "RX event queue for port 2 (Network port 1) has event"; 1328 mc_dma_status_rx_evq_vld1 1 1329 "RX event queue for port 1 (Network port 0) has event"; 1330 mc_dma_status_rx_evq_vld0 1 1331 "RX event queue for port 0 (NCSI) has event"; 1332 mc_dma_status_tx_cmq_rdy 1 1333 "TX command queue has room for more commands"; 1334 }; 1335 1336 // 5.635 1337 regarray mc_dma_tx_cmd_cntr ro addr(base, 0x0018c020) [4;0x4] 1338 "RX event queues" { 1339 dma_tx_cmd_cntr 32 ""; 1340 }; 1341 1342 // 5.638 1343 register mc_dma_tx_cmq_reg wo addr(base, 0x0018c008) 1344 "RX event queues" { 1345 mc_dma_tx_cmq_prt_sel 2 type(interface) 1346 "Select transmit interface"; 1347 mc_dma_tx_cmq_buf_sel 2 type(buffer) 1348 "Selected source buffer (use 3 if op == 1)"; 1349 mc_dma_tx_cmq_len 14 1350 "Number of bytes to transmit or to pop including 2 byte header"; 1351 mc_dma_tx_cmq_addr 12 "Address in 16-byte words (only optcode 1)"; 1352 mc_dma_tx_cmq_op 2 type(opcode) "Opcode"; 1353 }; 1354 1355 constants interface "Selected Interface" { 1356 interface_ncsi_mac = 0b00 "NCSI-MAC"; 1357 interface_port_0 = 0b01 "Network MAC port 0"; 1358 interface_port_1 = 0b10 "Network MAC port 1"; 1359 }; 1360 1361 constants opcode "Selected Interface" { 1362 transmit_circular_buffer = 0b00 1363 "Transmit (len) bytes using circular buffer state"; 1364 supplied_address = 0b01 1365 "Transmit (len) bytes starting from supplied address"; 1366 pop_circular_buffer = 0b10 1367 "Pop (len) bytes using circular buffer state"; 1368 }; 1369 1370 // 5.997 padded to 8 bits documentation is 3 1371 register mc_rstctrl_reg rw addr(base, 0x00480030) 1372 "Reset configuration Control register" { 1373 _ 5 rsvd; 1374 mc_swrst_slfclr_en_reset 1 "Enables global soft reset self clearing"; 1375 mc_swrst_mst_en_reset 1 "Enables global master soft reset"; 1376 mc_swrst_en_reset 1 "Enables global soft reset"; 1377 }; 1378 1379 // 5.1003 1380 register mc_rstvec_biu_mst_reg rw addr(base, 0x00480038) 1381 "BIU and PCIE Reset control register (Master reset)" { 1382 mc_pciesd_aux_mst_reset 1 "PCIE Serdes Aux reset"; 1383 mc_pciesd_mst_reset 1 "PCIE Serdes reset"; 1384 mc_biu_cs_mst_reset 1 "Not implemented"; 1385 mc_pcie_stky_mst_reset 1 "PCIE core Sticky reset"; 1386 mc_pcie_nstky_mst_reset 1 "PCIE core non-Sticky reset"; 1387 mc_pcie_core_mst_reset 1 "PCIE core reset if set"; 1388 mc_biu_mst_reset 1 "BIU reset"; 1389 mc_pcie_pwr_mst_reset 1 "PCIE core PWR reset if set"; 1390 }; 1391 1392 // 5.1006 1393 register mc_rstvec_biu_reg rw addr(base, 0x00480028) 1394 "BIU and PCIE Reset control register (Soft reset)" { 1395 mc_pciesd_aux_reset 1 "PCIE Serdes Aux reset"; 1396 mc_pciesd_reset 1 "PCIE Serdes reset"; 1397 mc_biu_cs_reset 1 "Not implemented"; 1398 mc_pcie_stky_reset 1 "PCIE core Sticky reset"; 1399 mc_pcie_nstky_reset 1 "PCIE core non-Sticky reset"; 1400 mc_pcie_core_reset 1 "PCIE core reset if set"; 1401 mc_biu_reset 1 "BIU reset"; 1402 mc_pcie_pwr_reset 1 "PCIE core PWR reset if set"; 1403 }; 1404 1405 // 5.1009 1406 regtype mc_rstvec_bpx_mst_reg 1407 "Reset Control register for BPX port (Master reset)" { 1408 mc_autoneg_mst_reset 1 "Auto neg Port reset"; 1409 mc_sgmii_mst_reset 1 "SGMII Port reset"; 1410 mc_xgbr_mst_reset 1 "XGBR Port reset"; 1411 mc_xgxs_mst_reset 1 "XGXS Port reset"; 1412 mc_xfidp_mst_reset 1 "XFI Port digital reset"; 1413 mc_xfiap_mst_reset 1 "XFI Port analog reset"; 1414 mc_sdp_mst_reset 1 "XAUI Serdes Port reset"; 1415 mc_pbx_mst_reset 1 "BPX port reset"; 1416 }; 1417 1418 register p0_mc_rstvec_bpx_mst_reg rw addr(base, 0x00480210) 1419 "Port 0 Reset control register for BPX Port (Master reset)" 1420 type(mc_rstvec_bpx_mst_reg); 1421 1422 register p1_mc_rstvec_bpx_mst_reg rw addr(base, 0x00480214) 1423 "Port 1 Reset control register for BPX Port (Master reset)" 1424 type(mc_rstvec_bpx_mst_reg); 1425 1426 // 5.1012 1427 regtype mc_rstvec_bpx_reg 1428 "Reset Control register for BPX port (Soft reset)" { 1429 mc_autoneg_reset 1 "Auto neg Port reset"; 1430 mc_sgmii_reset 1 "SGMII Port reset"; 1431 mc_xgbr_reset 1 "XGBR Port reset"; 1432 mc_xgxs_reset 1 "XGXS Port reset"; 1433 mc_xfidp_reset 1 "XFI Port digital reset"; 1434 mc_xfiap_reset 1 "XFI Port analog reset"; 1435 mc_sdp_reset 1 "XAUI Serdes Port reset"; 1436 mc_pbx_reset 1 "BPX port reset"; 1437 }; 1438 1439 register p0_mc_rstvec_bpx_reg rw addr(base, 0x00480200) 1440 "Port 0 Reset control register for BPX Port (Soft reset)" 1441 type(mc_rstvec_bpx_reg); 1442 1443 register p1_mc_rstvec_bpx_reg rw addr(base, 0x00480204) 1444 "Port 1 Reset control register for BPX Port (Soft reset)" 1445 type(mc_rstvec_bpx_reg); 1446 1447 // 5.1015 padded to 32 bits documentation is 21 1448 register mc_rstvec_mc_mst_reg rw addr(base, 0x0048003c) 1449 "Reset Control register for BPX port (Master reset)" { 1450 _ 11 rsvd; 1451 mc_flow_mngr_mst_reset 1 "MC FLOW_MNGR reset"; 1452 mc_mips_mst_reset 1 "MC MIPS 1 reset"; 1453 mc_mdio1_mst_reset 1 "MC MDIO 1 reset"; 1454 mc_mdio0_mst_reset 1 "MC MDIO 0 reset"; 1455 mc_rmii_gmac_mst_reset 1 "MC Management GMAC reset"; 1456 mc_spi_mst_reset 1 "MC SPI reset"; 1457 mc_i2c_mst_reset 1 "MC I2C reset"; 1458 mc_uart1_mst_reset 1 "MC UART 1 reset"; 1459 mc_uart0_mst_reset 1 "MC UART 0 reset"; 1460 mc_vmi_mst_reset 1 "MC VMI reset"; 1461 mc_dbi_mst_reset 1 "MC DBI reset"; 1462 mc_tlp_mst_reset 1 "MC TLP reset"; 1463 mc_ktchn_mst_reset 1 "MC PCIE Kitchen Sink reset"; 1464 mc_treg_mst_reset 1 "MC TREG reset"; 1465 mc_ireg1_mst_reset 1 "MC IREG 1 reset"; 1466 mc_ireg0_mst_reset 1 "MC IREG 0 reset"; 1467 mc_prsr1_mst_reset 1 "MC Parser 1 reset"; 1468 mc_prsr0_mst_reset 1 "MC Parser 0 reset"; 1469 mc_dma_mst_reset 1 "MC DMA reset"; 1470 mc_gpio_mst_reset 1 "MC GPIO reset"; 1471 mc_mc_mst_reset 1 "MC reset"; 1472 }; 1473 1474 // 5.1018 padded to 32 bits documentation is 21 1475 register mc_rstvec_mc_reg rw addr(base, 0x0048002c) 1476 "Reset Control register for BPX port (Soft reset)" { 1477 _ 11 rsvd; 1478 mc_flow_mngr_reset 1 "MC FLOW_MNGR reset"; 1479 mc_mips_reset 1 "MC MIPS 1 reset"; 1480 mc_mdio1_reset 1 "MC MDIO 1 reset"; 1481 mc_mdio0_reset 1 "MC MDIO 0 reset"; 1482 mc_rmii_gmac_reset 1 "MC Management GMAC reset"; 1483 mc_spi_reset 1 "MC SPI reset"; 1484 mc_i2c_reset 1 "MC I2C reset"; 1485 mc_uart1_reset 1 "MC UART 1 reset"; 1486 mc_uart0_reset 1 "MC UART 0 reset"; 1487 mc_vmi_reset 1 "MC VMI reset"; 1488 mc_dbi_reset 1 "MC DBI reset"; 1489 mc_tlp_reset 1 "MC TLP reset"; 1490 mc_ktchn_reset 1 "MC PCIE Kitchen Sink reset"; 1491 mc_treg_reset 1 "MC TREG reset"; 1492 mc_ireg1_reset 1 "MC IREG 1 reset"; 1493 mc_ireg0_reset 1 "MC IREG 0 reset"; 1494 mc_prsr1_reset 1 "MC Parser 1 reset"; 1495 mc_prsr0_reset 1 "MC Parser 0 reset"; 1496 mc_dma_reset 1 "MC DMA reset"; 1497 mc_gpio_reset 1 "MC GPIO reset"; 1498 mc_mc_reset 1 "MC reset"; 1499 }; 1500 1501 // 5.1021 padded to 32 bits documentation is 14 1502 regtype mc_rstvec_ntwrkpt_mst_reg 1503 "Reset Control register for BPX port (Master reset)" { 1504 _ 18 rsvd; 1505 mc_sr_mst_reset 1 "Global SRAM port reset"; 1506 mc_extphy_mst_reset 1 "MC external PHY port reset"; 1507 mc_xgtxfifo_mst_reset 1 "MC XG Async TX FIFO module port reset"; 1508 mc_xgrxfifo_mst_reset 1 "MC XG Async RX FIFO module port reset"; 1509 mc_1gfifo_mst_reset 1 "MC 1G Async FIFO module port reset"; 1510 mc_grmon_mst_reset 1 "MC 1G RMON module port reset"; 1511 mc_xgtx_mst_reset 1 "MC XG MAC TX module port reset "; 1512 mc_xgrx_mst_reset 1 "MC XG MAC RX module port reset "; 1513 mc_gmac_mst_reset 1 "MC 1G MAC module port reset"; 1514 mc_em_mst_reset 1 "MC EM module port reset"; 1515 mc_ev_mst_reset 1 "MC Event module port"; 1516 mc_rxdp_mst_reset 1 "MC RXDP port reset"; 1517 mc_txdp_mst_reset 1 "MC TXDP port reset"; 1518 mc_ntwrkpt_mst_reset 1 "MC Network port reset"; 1519 }; 1520 1521 register p0_mc_rstvec_ntwrkpt_mst_reg rw addr(base, 0x00480218) 1522 "Port 0 Reset Control register for BPX port (Master reset)" 1523 type(mc_rstvec_ntwrkpt_mst_reg); 1524 1525 register p1_mc_rstvec_ntwrkpt_mst_reg rw addr(base, 0x0048021c) 1526 "Port 1 Reset Control register for BPX port (Master reset)" 1527 type(mc_rstvec_ntwrkpt_mst_reg); 1528 1529 // 5.1021 padded to 32 bits documentation is 14 1530 regtype mc_rstvec_ntwrkpt_reg 1531 "Reset Control register for BPX port (Soft reset)" { 1532 _ 18 rsvd; 1533 mc_sr_reset 1 "Global SRAM port reset"; 1534 mc_extphy_reset 1 "MC external PHY port reset"; 1535 mc_xgtxfifo_reset 1 "MC XG Async TX FIFO module port reset"; 1536 mc_xgrxfifo_reset 1 "MC XG Async RX FIFO module port reset"; 1537 mc_1gfifo_reset 1 "MC 1G Async FIFO module port reset"; 1538 mc_grmon_reset 1 "MC 1G RMON module port reset"; 1539 mc_xgtx_reset 1 "MC XG MAC TX module port reset "; 1540 mc_xgrx_reset 1 "MC XG MAC RX module port reset "; 1541 mc_gmac_reset 1 "MC 1G MAC module port reset"; 1542 mc_em_reset 1 "MC EM module port reset"; 1543 mc_ev_reset 1 "MC Event module port"; 1544 mc_rxdp_reset 1 "MC RXDP port reset"; 1545 mc_txdp_reset 1 "MC TXDP port reset"; 1546 mc_ntwrkpt_reset 1 "MC Network port reset"; 1547 }; 1548 1549 1550 register p0_mc_rstvec_ntwrkpt_reg rw addr(base, 0x00480208) 1551 "Port 0 Reset Control register for BPX port (Soft reset)" 1552 type(mc_rstvec_ntwrkpt_reg); 1553 1554 register p1_mc_rstvec_ntwrkpt_reg rw addr(base, 0x0048020c) 1555 "Port 1 Reset Control register for BPX port (Soft reset)" 1556 type(mc_rstvec_ntwrkpt_reg); 1557 1558 // 5.1062 1559 regarray mc_treg_smem rw addr(base, 0x00ff0000) [512;0x4] 1560 "Shared memory" { 1561 mc_treg_smem_row 32; 1562 }; 1563 1564}; 1565