1/* 2 * Copyright (c) 2012, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * sdhc.dev 11 * 12 * DESCRIPTION: SD Host Controller 13 * 14 * See: 15 * SD Specifications Part A2: SD Host Controller Simplified Specification 16 * Version 3.00, February 25, 2011. 17 * Technical Committee, SD Association 18 * 19 * Note that the specification specifies 16-bit registers. Here we 20 * merge adjacent registers into 32-bit ones, so they are accessed 21 * two-at-a-time as 32-bit words. This is how they are implemented on 22 * the TI OMAP SoCs, for example. 23 */ 24 25 device sdhc msbfirst (addr base) "SD Host Controller" { 26 27 // 28 // Command formats (the non-trival ones) 29 // 30 // The following section numbers refer to: 31 // SD Specifications Part 1: Physical Layer Simplified Specification 32 // Version 3.01, May 18, 2010. 33 // Technical Committee, SD Card Association 34 // 35 36 // 4.7.4 37 datatype cmd4 msbfirst(32) "SET_DSR command" { 38 dsr 16 "DSR value"; 39 _ 16; 40 }; 41 42 datatype rcacmd msbfirst(32) "Commands 7,9,10,13,15,55" { 43 rca 16 "RCA value"; 44 _ 16; 45 }; 46 47 datatype cmd8 msbfirst(32) "SEND_IF_COND command" { 48 _ 20 mbz; 49 vhs 4 "Voltage supplied (VHS)"; 50 pattern 8 "Check pattern"; 51 }; 52 53 54 55 // 56 // Host controller registers 57 // 58 // The following section numbers refer to: 59 // SD Specifications Part A2: SD Host Controller Simplified Specification 60 // Version 3.00, February 25, 2011. 61 // Technical Committee, SD Association 62 // 63 64 // 2.2.1 65 register sdmasa rw addr(base, 0x00) "SDMA system address" 66 type(uint32); 67 68 register arg2 rw also addr(base, 0x00) "Argument 2" 69 type(uint32); 70 71 // 2.2.2/3 72 register blckcnt rw addr(base, 0x04) "Block count" { 73 nblk 16 "Block count"; 74 _ 1 mbz; 75 hsbb 3 "Host SDMA buffer boundary (4k . 2^x)"; 76 blen 12 "Transfer block size (bytes)"; 77 }; 78 79 // 2.2.4 80 register arg1 rw addr(base, 0x08) "Argument 1" 81 type(uint32); 82 83 // 2.2.5/6 84 constants auto_en "Auto command enable values" { 85 auto_en_dis = 0b00 "Auto Command Disabled"; 86 auto_en_12 = 0b01 "Auto CMD12 Enable"; 87 auto_en_23 = 0b10 "Auto CMD23 Enable"; 88 }; 89 constants cmd_tp "Command type" { 90 cmd_tp_abrt = 0b11 "Abort CMD12, CMD52 for writing I/O Abort"; 91 cmd_tp_rsme = 0b10 "Resume CMD52 for writing Function Select"; 92 cmd_tp_susp = 0b01 "Suspend CMD52 for writing Bus Suspend"; 93 cmd_tp_norm = 0b00 "Normal; other commands"; 94 }; 95 constants rsp_tp "Response type" { 96 rsp_tp_none = 0b00 "No response"; 97 rsp_tp_136 = 0b01 "Response length 136"; 98 rsp_tp_48 = 0b10 "Response length 48"; 99 rsp_tp_48cb = 0b11 "Response length 48 check busy after response"; 100 }; 101 register ctm rw addr(base, 0x0C) "Command and transfer mode" { 102 _ 2 mbz; 103 index 6 "Command index"; 104 cmd_type 2 type(cmd_tp) "Command type"; 105 dp 1 "Data present select"; 106 cice 1 "Command index check enable"; 107 ccce 1 "Command CRC check enable"; 108 _ 1 mbz; 109 rsp_type 2 "Response type select"; 110 _ 10 mbz; 111 msbs 1 "Multi/single block select (1=multi)"; 112 ddir 1 "Data transfer direction select (1=read)"; 113 acen 2 type(auto_en) "Auto command enable"; 114 bce 1 "Block count enable"; 115 de 1 "DMA enable"; 116 }; 117 118 // 2.2.7 119 regarray resp rw addr(base, 0x10)[4] "Response" 120 type(uint32); 121 122 // 2.2.8 123 register bdp rw addr(base, 0x20) "Buffer data port" 124 type(uint32); 125 126 // 2.2.9 127 register ps ro addr(base, 0x24) "Present state" { 128 _ 7 mbz; 129 clsl 1 "CMD line signal level"; 130 dlsl 4 "DAT[3:0] line signal level"; 131 wp 1 "Write protect switch pin level (0=ro)"; 132 cdpl 1 "Card detect pin level (1=present)"; 133 css 1 "Card state stable"; 134 cins 1 "Card inserted"; 135 _ 4 mbz; 136 bre 1 "Buffer read enable"; 137 bwe 1 "Buffer write enable"; 138 rta 1 "Read transfer active"; 139 wta 1 "Write transfer active"; 140 _ 4 mbz; 141 rtr 1 "Re-tuning request"; 142 dla 1 "DAT line active"; 143 dati 1 "Command inhibit (DAT)"; 144 cmdi 1 "Command inhibit (CMD)"; 145 }; 146 147 // 2.2.10-13 148 constants voltage "Bus voltage select" { 149 voltage_33 = 0b111 "3.3V (typ.)"; 150 voltage_30 = 0b110 "3.0V (typ.)"; 151 voltage_18 = 0b101 "1.8V (typ.)"; 152 }; 153 register hctl rw addr(base, 0x28) "Host control" { 154 _ 5 mbz; 155 rem 1 "Wakeup event enable on SD card removal"; 156 ins 1 "Wakeup event enable on SD card insertion"; 157 iwe 1 "Wakeup event enable on card interrupt"; 158 _ 4 mbz; 159 ibg 1 "Interrupt at block gap"; 160 rwc 1 "Read wait control"; 161 cr 1 "Continue request"; 162 sbgr 1 "Stop at block gap request"; 163 _ 4 mbz; 164 sdvs 3 type(voltage) "SD bus voltage select"; 165 sdbp 1 "SD bus power"; 166 cdss 1 "Card detect signal selection"; 167 cdtl 1 "Card detect test level"; 168 edtw 1 "Extended data transfer width"; 169 dmas 2 "DMA select"; 170 hspe 1 "High speed enable"; 171 dtw 1 "Data transfer width"; 172 lc 1 "LED control"; 173 }; 174 175 // 2.2.14-16 176 register sysctl rw addr(base, 0x2C) "System control" { 177 _ 5 mbz; 178 srd 1 "Software reset for DAT line"; 179 src 1 "Software reset for CMD line"; 180 sra 1 "Software reset for all"; 181 _ 4 mbz; 182 dto 4 "Data timeout counter value"; 183 clkd 10 "SDCLK frequency select"; 184 cgs 1 "Clock generator select"; 185 _ 2 mbz; 186 cen 1 "SD clock enable"; 187 ics 1 ro "Internal clock stable"; 188 ice 1 "Internal clock enable"; 189 }; 190 191 // 2.2.17/18 192 register stat addr(base, 0x30) "Interrupt status" { 193 // 4 bits in the spec, but we have two bits in the OMAP 44xx 194 // adaptor which we also specify here. Might need to change 195 // this if we encounter another SDHC reader with different 196 // use of these bits. 197 vses 2 rw "Vendor specific error status"; 198 bada 1 rw1c "Bad access to data space"; 199 cerr 1 rw1c "Card error"; 200 _ 1 mbz; 201 te 1 rw1c "Tuning error"; 202 admae 1 rw1c "ADMA error"; 203 ace 1 rw1c "Auto CMD error"; 204 cle 1 rw1c "Current limit error"; 205 deb 1 rw1c "Data end bit error"; 206 dcrc 1 rw1c "Data CRC error"; 207 dto 1 rw1c "Data timeout error"; 208 cie 1 rw1c "Command index error"; 209 ceb 1 rw1c "Command end bit error"; 210 ccrc 1 rw1c "Command CRC error"; 211 cto 1 rw1c "Command timeout error"; 212 erri 1 ro "Error interrupt"; 213 _ 2 mbz; 214 rte 1 ro "Re-tuning event"; 215 intc 1 ro "INT_C"; 216 intb 1 ro "INT_B"; 217 inta 1 ro "INT_A"; 218 cirq 1 ro "Card interrupt"; 219 crem 1 rw1c "Card removal"; 220 cins 1 rw1c "Card insertion"; 221 brr 1 rw1c "Buffer read ready"; 222 bwr 1 rw1c "Buffer write ready"; 223 dma 1 rw1c "DMA interrupt"; 224 bge 1 rw1c "Block gap event"; 225 tc 1 rw1c "Transfer complete"; 226 cc 1 rw1c "Command complete"; 227 }; 228 229 230 231 // 2.2.19-22 232 regtype ir "Interrupt register" { 233 // 4 bits in the spec, but we have two bits in the OMAP 44xx 234 // adaptor which we also specify here. Might need to change 235 // this if we encounter another SDHC reader with different 236 // use of these bits. 237 vses 2 rw "Vendor specific error status"; 238 bada 1 rw "Bad access to data space"; 239 cerr 1 rw "Card error"; 240 _ 1 mbz; 241 te 1 rw "Tuning error"; 242 admae 1 rw "ADMA error"; 243 ace 1 rw "Auto CMD error"; 244 cle 1 rw "Current limit error"; 245 deb 1 rw "Data end bit error"; 246 dcrc 1 rw "Data CRC error"; 247 dto 1 rw "Data timeout error"; 248 cie 1 rw "Command index error"; 249 ceb 1 rw "Command end bit error"; 250 ccrc 1 rw "Command CRC error"; 251 cto 1 rw "Command timeout error"; 252 _ 3 mbz; 253 rte 1 rw "Re-tuning event"; 254 intc 1 rw "INT_C"; 255 intb 1 rw "INT_B"; 256 inta 1 rw "INT_A"; 257 cirq 1 rw "Card interrupt"; 258 crem 1 rw "Card removal"; 259 cins 1 rw "Card insertion"; 260 brr 1 rw "Buffer read ready"; 261 bwr 1 rw "Buffer write ready"; 262 dma 1 rw "DMA interrupt"; 263 bge 1 rw "Block gap event"; 264 tc 1 rw "Transfer complete"; 265 cc 1 rw "Command complete"; 266 }; 267 268 register ie addr(base, 0x34) "Interrupt enable" 269 type(ir); 270 register ise addr(base, 0x38) "Interrupt signal enable" 271 type(ir); 272 273 // 2.2.23-24 274 constants uhs_mode "UHS mode" { 275 uhs_sdr12 = 0b000 "SDR12"; 276 uhs_sdr25 = 0b001 "SDR25"; 277 uhs_sdr50 = 0b010 "SDR50"; 278 uhs_sdr104 = 0b011 "SDR104"; 279 uhs_ddr50 = 0b100 "DDR50"; 280 }; 281 register aces addr(base, 0x3c) "Auto CMD error status / Host control 2" { 282 pve 1 rw "Preset value enable"; 283 aie 1 rw "Asynchronous interrupt enable"; 284 _ 6 mbz; 285 scs 1 rw "Sampling clock select"; 286 et 1 rw "Execute tuning"; 287 dss 2 rw "Driver strength select"; 288 lvse 1 rw "1.8V signaling enable"; 289 ums 3 rw type(uhs_mode) "UHS mode select"; 290 _ 8 mbz; 291 cni 1 ro "Command not issued by Auto CMD12 error"; 292 _ 2 mbz; 293 acie 1 ro "Auto CMD index error"; 294 acebe 1 ro "Auto CMD end bit error"; 295 acce 1 ro "Auto CMD CRC error"; 296 acte 1 ro "Auto CMD timeout error"; 297 acne 1 ro "Auto CMD12 not executed"; 298 }; 299 300 // 2.2.25 301 // This register is, bizarrely, writeable on the OMAP44xx, and 302 // needs to be written to configure the controller. 303 constants slot_tp "Slot type" { 304 slot_rem = 0b00 "Removable card slot"; 305 slot_emb = 0b01 "Embedded slot for one device"; 306 slot_shr = 0b10 "Shared bus slot"; 307 }; 308 register capa rw addr(base, 0x40) "Capability register A" { 309 slottp 2 type(slot_tp) "Slot type"; 310 ais 1 "Asynchronous interrupt support"; 311 bit64 1 "64-bit system bus support"; 312 _ 1 mbz; 313 vs18 1 "Voltage support 1.8V"; 314 vs30 1 "Voltage support 3.0V"; 315 vs33 1 "Voltage support 3.3V"; 316 srs 1 "Suspend/resume support"; 317 ds 1 "SDMA support"; 318 hss 1 "High speed support"; 319 _ 1 mbz; 320 ad2s 1 "ADMA2 support"; 321 bit8 1 "8-bit support for embedded device"; 322 mbl 2 "Max block length"; 323 bcf 8 "Base clock frequency for SD clock"; 324 tcu 1 "Timeout clock unit"; 325 _ 1 mbz; 326 tcf 6 "Tileout clock frequency"; 327 }; 328 329 register capb ro addr(base, 0x44) "Capability register B" { 330 _ 8 mbz; 331 cm 8 "Clock multiplier"; 332 rtm 2 "Re-tuning modes"; 333 utsdr50 1 "Use tuning for SDR50"; 334 _ 1 mbz; 335 tcrt 4 "Timer count for re-tuning"; 336 _ 1 mbz; 337 dtd 1 "Driver type D support"; 338 dtc 1 "Driver type C support"; 339 dta 1 "Driver type A support"; 340 _ 1 mbz; 341 ddr50 1 "DDR50 support"; 342 sdr104 1 "SDR104 support"; 343 sdr50 1 "SDR50 support"; 344 }; 345 346 // 2.2.26 347 register mcc ro addr(base, 0x48) "Maximum current capabilities" { 348 _ 8 mbz; 349 mc18 8 "Maximum current for 1.8V"; 350 mc30 8 "Maximum current for 3.0V"; 351 mc33 8 "Maximum current for 3.3V"; 352 }; 353 354 // 2.2.27 355 register fer wo addr(base, 0x50) "Force event register" { 356 vses 4 wo "Vendor specific error status"; 357 _ 2 mbz; 358 ae 1 wo "ADMA error"; 359 ace 1 wo "Auto CMD error"; 360 cle 1 wo "Current limit error"; 361 debe 1 wo "Data end bit error"; 362 dce 1 wo "Data CRC error"; 363 dte 1 wo "Data timeout error"; 364 cie 1 wo "Command index error"; 365 cebe 1 wo "Command end bit error"; 366 cce 1 wo "Command CRC error"; 367 cte 1 wo "Command timeout error"; 368 _ 8 mbz; 369 cni 1 wo "Command not issued by Auto CMD12 error"; 370 _ 2 mbz; 371 acie 1 wo "Auto CMD index error"; 372 acebe 1 wo "Auto CMD end bit error"; 373 acce 1 wo "Auto CMD CRC error"; 374 acte 1 wo "Auto CMD timeout error"; 375 acne 1 wo "Auto CMD12 not executed"; 376 }; 377 378 // 2.2.29 379 register admaes ro addr(base, 0x54) "ADMA error status" { 380 _ 29 mbz; 381 lme 1 "ADMA length mismatch error"; 382 aes 2 "ADMA error state"; 383 }; 384 385 // 2.2.30 386 register admasl rw addr(base, 0x58) "ADMA system address low" 387 type(uint32); 388 register admash rw addr(base, 0x5C) "ADMA system address high" 389 type(uint32); 390 391 // 392 // We do not, at present, implement the Preset Value registers. 393 // 394 395 // 2.2.32 396 register sbc rw addr(base, 0xE0) "Shared bus control" { 397 _ 1 mbz; 398 bepc 7 rw "Back-end power control"; 399 _ 1 mbz; 400 ips 3 rw "Interrupt pin select"; 401 _ 1 mbz; 402 cps 3 rw "Clock pin select"; 403 _ 1 mbz; 404 bwp 7 ro "Bus width preset"; 405 _ 2 mbz; 406 niip 2 ro "Number of interrupt input pins"; 407 _ 1 mbz; 408 ncp 3 ro "Number of clock pins"; 409 }; 410 411 // 2.2.33/34 412 register rev rw addr(base, 0xFC) "Version / Slot int. status" { 413 vrev 8 ro "Vendor version number"; 414 srev 8 ro "Specification version number"; 415 _ 8 mbz; 416 slots 8 "Interrupt status per slot"; 417 }; 418 419 }; 420