1/* 2 * Copyright (c) 2018, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * rpi3_miniuart_.dev 11 * 12 * DESCRIPTION: Raspberry Pi 3 mini UART 13 * 14 */ 15 16device rpi3_miniuart msbfirst ( addr base ) "Raspberry Pi3 mini UART" { 17 18 constants word_len "Word Length" { 19 bits7 = 0b00 "7 bits"; 20 bits8 = 0b11 "8 bits"; 21 }; 22 23 register DR addr (base, 0x00) "I/O Data" { 24 _ 24; 25 data 8 rw "Data character when DLAB=0"; 26 }; 27 28 register IER addr (base, 0x04) "Interrupt Enable" { 29 _ 30; 30 txirqen 1 rw "Enable transmit interrupts when DLAB=0"; 31 rxirqen 1 rw "Enable receive interrupts when DLAB=0"; 32 }; 33 34 register IIR addr (base, 0x08) "Interrupt Identify" { 35 _ 24; 36 fifoen 2 ro "FIFO enabled"; 37 _ 3; 38 irqid_fifoclear 2 rw "read Interrupt ID/write FIFO clear"; 39 irqpen 1 ro "Interrupt pending"; 40 }; 41 42 register LCR addr (base, 0x0c) "Line Control" { 43 _ 24; 44 dlab 1 rw "DLAB access"; 45 break 1 rw "Break"; 46 _ 4; 47 datasize 2 rw type(word_len) "Data size"; 48 }; 49 50 register MCR addr (base, 0x10) "Modem Control" { 51 _ 30; 52 rts 1 rw "RTS line"; 53 _ 1; 54 }; 55 56 register LSR addr (base, 0x14) "Line Status" { 57 _ 25; 58 txid 1 ro "Transmitter idle"; 59 txem 1 ro "Transmitter empty"; 60 _ 3; 61 rxor 1 ro "Receiver overrun/clear on read"; 62 dtready 1 ro "Data ready"; 63 }; 64 65 register MSR addr (base, 0x18) "Modem Status" { 66 _ 26; 67 cts 1 ro "CTS status"; 68 _ 5; 69 }; 70 71 register SCRATCH addr (base, 0x1c) "Scratch" { 72 _ 24; 73 scratch 8 rw "Scratch byte"; 74 }; 75 76 register CNTL addr (base, 0x20) "Extra Control" { 77 _ 24; 78 cts 1 rw "CTS assert level"; 79 rts 1 rw "RTS assert level"; 80 rtsauto 2 rw "RTS auto flow level"; 81 txflow 1 rw "Enable transmit auto flow-control using CTS"; 82 rxflow 1 rw "Enable receive auto flow-control using RTS"; 83 txen 1 rw "Transmitter enable"; 84 rxen 1 rw "Receiver enable"; 85 }; 86 87 register STAT addr (base, 0x24) "Extra Status" { 88 _ 22; 89 txdone 1 ro "Transmitter done"; 90 txfe 1 ro "Transmit FIFO is empty"; 91 cts 1 ro "CTS line"; 92 rts 1 ro "RTS line"; 93 txff 1 ro "Transmit FIFO is full"; 94 rxov 1 ro "Receiver overrun"; 95 txid 1 ro "Transmitter is idle"; 96 rxid 1 ro "Receiver is idle"; 97 spav 1 ro "Space available"; 98 symav 1 ro "Symbol available"; 99 }; 100 101 register BAUD addr (base, 0x28) "Baudrate" { 102 _ 16; 103 baudrate 16 rw "Baudrate counter"; 104 }; 105}; 106