1/*
2 * Copyright (c) 2012, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr 6, CH-8092 Zurich.
7 * Attn: Systems Group.
8 */
9
10/*
11 * pl390_gic_cpuif.dev
12 *
13 * DESCRIPTION: PrimeCell PL390 Generic Interrupt Controller
14 *
15 * This is derived from:
16 *
17 * [1] PrimeCell Generic Interrupt Controller PL390
18 *     (DDI0416B_gic_pl390_r0p0_trm.pdf)
19 * [2] ARM Cortex A9 MPCore TRM r2p0
20 * [3] ARM Generic Interrupt Controller v1.0
21 *
22 * Updated to work on PandaBoard according to [2] Table 3-1
23 *
24 * Register map for distributor: [3], chp 4.1.2
25 * Register map for CPU interface: [3], chp 4.1.3
26 */
27
28device pl390_gic_cpuif msbfirst (addr cpu_base)
29    "PrimeCell PL390 Generic Interrupt Controller CPU interface"
30{
31
32
33    //
34    // CPU interface register map
35    //
36
37    register ICCICR addr(cpu_base, 0x0) "CPU Interface Control" {
38        _               31;
39        enable          1       "en. fwding to connected processors";
40    };
41
42    register ICCPMR addr(cpu_base, 0x4) "Interrupt Priority Mask" {
43        _               24;
44        priority        8       "Priority mask level for CPU Interface";
45    };
46
47    register ICCBPR addr(cpu_base, 0x8) "Binary Point" {
48        _               29;
49        binary_point    3       "Split Group- and subpriority";
50    };
51
52    register ICCIAR ro addr(cpu_base, 0xc) "Interrupt Acknowledge" {
53        _               19;
54        cpu_id          3       "Processor ID of interrupting processor";
55        ack_int_id      10      "Interrupt ID";
56    };
57
58    register ICCEOIR wo addr(cpu_base, 0x10) "End of Interrupt" {
59        _               19 mbz;
60        cpu_id          3       "Proc ID of ICCIAR access";
61        eoi_int_id      10      "ACKINTID of ICCIAR access";
62    };
63
64    register ICCRPR ro addr(cpu_base, 0x14) "Running Priority" {
65        _               24;
66        priority        8       "Highest priority active interrupt";
67    };
68
69    register ICCHPIR ro addr(cpu_base, 0x18) "Highest Pending Interrupt" {
70        _               19;
71        cpu_id          3       "ID of interrupting processor";
72        pend_int_id     10      "ID of highest pri. pending int.";
73    };
74
75    register ICCABPR addr(cpu_base, 0x1c) "Aliased Binary Point" {
76        _               29 rsvd;
77        binary_point    3       "Split Group- and subpriority";
78    };
79
80    register ICCIIDR ro addr(cpu_base, 0xfc) "CPU Interface Identification" {
81        product_id      12      "Product ID";
82        arch_version    4       "Implemented GIC architecture version";
83        revision        4       "Revision number for the CPU Interface";
84        implementer     12      "JEP106 code of the implementer";
85    };
86 };
87